i2c_master: port to STM32F4
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lib/i2c_master.c
488
lib/i2c_master.c
@ -1,4 +1,4 @@
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/** library to communicate using I²C as master (code)
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/** library to communicate using I²C as master
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* @file
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* @author King Kévin <kingkevin@cuvoodoo.info>
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* @copyright SPDX-License-Identifier: GPL-3.0-or-later
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@ -21,275 +21,100 @@
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#include "global.h" // global utilities
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#include "i2c_master.h" // I²C header and definitions
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/** get RCC for I²C based on I²C identifier
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* @param[in] i2c I²C base address
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* @return RCC address for I²C peripheral
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/** @defgroup i2c_master_i2c I²C peripheral used for I²C communication
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* @{
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*/
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static uint32_t RCC_I2C(uint32_t i2c)
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#define I2C_MASTER_I2C 1 /**< I²C peripheral ID */
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#define I2C_MASTER_SCL PB6 /**< GPIO pin for I²C SCL */
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#define I2C_MASTER_SDA PB7 /**< GPIO pin for I²C SDA */
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#define I2C_MASTER_AF GPIO_AF4 /**< alternate function for GPIO pin */
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/** @} */
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void i2c_master_setup(uint16_t frequency)
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{
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cm3_assert(I2C1 == i2c || I2C2 == i2c);
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switch (i2c) {
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case I2C1:
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return RCC_I2C1;
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break;
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case I2C2:
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return RCC_I2C2;
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break;
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default:
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return 0;
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}
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}
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/** get RCC for GPIO port for SCL pin based on I²C identifier
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* @param[in] i2c I²C base address
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* @return RCC GPIO address
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*/
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static uint32_t RCC_GPIO_PORT_SCL(uint32_t i2c)
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{
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cm3_assert(I2C1 == i2c || I2C2 == i2c);
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switch (i2c) {
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case I2C1:
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case I2C2:
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return RCC_GPIOB;
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break;
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default:
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return 0;
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}
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}
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/** get RCC for GPIO port for SDA pin based on I²C identifier
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* @param[in] i2c I²C base address
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* @return RCC GPIO address
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*/
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static uint32_t RCC_GPIO_PORT_SDA(uint32_t i2c)
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{
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cm3_assert(I2C1 == i2c || I2C2 == i2c);
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switch (i2c) {
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case I2C1:
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case I2C2:
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return RCC_GPIOB;
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break;
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default:
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return 0;
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}
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}
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/** get GPIO port for SCL pin based on I²C identifier
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* @param[in] i2c I²C base address
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* @return GPIO address
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*/
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static uint32_t GPIO_PORT_SCL(uint32_t i2c)
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{
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cm3_assert(I2C1 == i2c || I2C2 == i2c);
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switch (i2c) {
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case I2C1:
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if (AFIO_MAPR & AFIO_MAPR_I2C1_REMAP) {
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return GPIO_BANK_I2C1_RE_SCL;
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} else {
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return GPIO_BANK_I2C1_SCL;
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}
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break;
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case I2C2:
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return GPIO_BANK_I2C2_SCL;
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break;
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default:
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return 0;
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}
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}
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/** get GPIO port for SDA pin based on I²C identifier
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* @param[in] i2c I²C base address
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* @return GPIO address
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*/
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static uint32_t GPIO_PORT_SDA(uint32_t i2c)
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{
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cm3_assert(I2C1 == i2c || I2C2 == i2c);
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switch (i2c) {
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case I2C1:
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if (AFIO_MAPR & AFIO_MAPR_I2C1_REMAP) {
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return GPIO_BANK_I2C1_RE_SDA;
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} else {
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return GPIO_BANK_I2C1_SDA;
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}
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break;
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case I2C2:
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return GPIO_BANK_I2C2_SDA;
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break;
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default:
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return 0;
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}
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}
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/** get GPIO pin for SCL pin based on I²C identifier
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* @param[in] i2c I²C base address
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* @return GPIO address
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*/
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static uint32_t GPIO_PIN_SCL(uint32_t i2c)
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{
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cm3_assert(I2C1 == i2c || I2C2 == i2c);
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switch (i2c) {
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case I2C1:
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if (AFIO_MAPR & AFIO_MAPR_I2C1_REMAP) {
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return GPIO_I2C1_RE_SCL;
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} else {
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return GPIO_I2C1_SCL;
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}
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break;
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case I2C2:
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return GPIO_I2C2_SCL;
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break;
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default:
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return 0;
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}
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}
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/** get GPIO pin for SDA pin based on I²C identifier
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* @param[in] i2c I²C base address
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* @return GPIO address
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*/
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static uint32_t GPIO_PIN_SDA(uint32_t i2c)
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{
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cm3_assert(I2C1 == i2c || I2C2 == i2c);
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switch (i2c) {
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case I2C1:
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if (AFIO_MAPR & AFIO_MAPR_I2C1_REMAP) {
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return GPIO_I2C1_RE_SDA;
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} else {
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return GPIO_I2C1_SDA;
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}
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break;
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case I2C2:
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return GPIO_I2C2_SDA;
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break;
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default:
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return 0;
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}
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}
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void i2c_master_setup(uint32_t i2c, uint16_t frequency)
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{
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cm3_assert(I2C1 == i2c || I2C2 == i2c);
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// configure I²C peripheral
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rcc_periph_clock_enable(RCC_GPIO_PORT_SCL(i2c)); // enable clock for I²C I/O peripheral
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gpio_set(GPIO_PORT_SCL(i2c), GPIO_PIN_SCL(i2c)); // already put signal high to avoid small pulse
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gpio_set_mode(GPIO_PORT_SCL(i2c), GPIO_MODE_OUTPUT_10_MHZ, GPIO_CNF_OUTPUT_ALTFN_OPENDRAIN, GPIO_PIN_SCL(i2c)); // setup I²C I/O pins
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rcc_periph_clock_enable(RCC_GPIO_PORT_SDA(i2c)); // enable clock for I²C I/O peripheral
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gpio_set(GPIO_PORT_SDA(i2c), GPIO_PIN_SDA(i2c)); // already put signal high to avoid small pulse
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gpio_set_mode(GPIO_PORT_SDA(i2c), GPIO_MODE_OUTPUT_10_MHZ, GPIO_CNF_OUTPUT_ALTFN_OPENDRAIN, GPIO_PIN_SDA(i2c)); // setup I²C I/O pins
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rcc_periph_clock_enable(RCC_AFIO); // enable clock for alternate function
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rcc_periph_clock_enable(RCC_I2C(i2c)); // enable clock for I²C peripheral
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i2c_reset(i2c); // reset peripheral domain
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i2c_peripheral_disable(i2c); // I²C needs to be disable to be configured
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I2C_CR1(i2c) |= I2C_CR1_SWRST; // reset peripheral
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I2C_CR1(i2c) &= ~I2C_CR1_SWRST; // clear peripheral reset
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if (0==frequency) { // don't allow null frequency
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rcc_periph_clock_enable(GPIO_RCC(I2C_MASTER_SCL)); // enable clock for I²C I/O peripheral
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gpio_set(GPIO_PORT(I2C_MASTER_SCL), GPIO_PIN(I2C_MASTER_SCL)); // already put signal high to avoid small pulse
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gpio_mode_setup(GPIO_PORT(I2C_MASTER_SCL), GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO_PIN(I2C_MASTER_SCL)); // set SCL pin to alternate function
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gpio_set_output_options(GPIO_PORT(I2C_MASTER_SCL), GPIO_OTYPE_OD, GPIO_OSPEED_25MHZ, GPIO_PIN(I2C_MASTER_SCL)); // set SCL pin output as open-drain
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gpio_set_af(GPIO_PORT(I2C_MASTER_SCL), I2C_MASTER_AF, GPIO_PIN(I2C_MASTER_SCL)); // set alternate function to I²C SCL pin
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rcc_periph_clock_enable(GPIO_RCC(I2C_MASTER_SDA)); // enable clock for I²C I/O peripheral
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gpio_set(GPIO_PORT(I2C_MASTER_SDA), GPIO_PIN(I2C_MASTER_SDA)); // already put signal high to avoid small pulse
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gpio_mode_setup(GPIO_PORT(I2C_MASTER_SDA), GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO_PIN(I2C_MASTER_SDA)); // set SDA pin to alternate function
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gpio_set_output_options(GPIO_PORT(I2C_MASTER_SDA), GPIO_OTYPE_OD, GPIO_OSPEED_25MHZ, GPIO_PIN(I2C_MASTER_SDA)); // set SDA pin output as open-drain
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gpio_set_af(GPIO_PORT(I2C_MASTER_SDA), I2C_MASTER_AF, GPIO_PIN(I2C_MASTER_SDA)); // set alternate function to I²C SDA pin
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rcc_periph_clock_enable(RCC_I2C(I2C_MASTER_I2C)); // enable clock for I²C peripheral
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i2c_reset(I2C(I2C_MASTER_I2C)); // reset peripheral domain
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i2c_peripheral_disable(I2C(I2C_MASTER_I2C)); // I²C needs to be disable to be configured
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I2C_CR1(I2C(I2C_MASTER_I2C)) |= I2C_CR1_SWRST; // reset peripheral
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I2C_CR1(I2C(I2C_MASTER_I2C)) &= ~I2C_CR1_SWRST; // clear peripheral reset
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if (0 == frequency) { // don't allow null frequency
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frequency = 1;
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} else if (frequency > 400) { // limit frequency to 400 kHz
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frequency = 400;
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}
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i2c_set_clock_frequency(i2c, rcc_apb1_frequency / 1000000); // configure the peripheral clock to the APB1 freq (where it is connected to)
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if (frequency>100) { // use fast mode for frequencies over 100 kHz
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i2c_set_fast_mode(i2c); // set fast mode (Fm)
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i2c_set_ccr(i2c, rcc_apb1_frequency / (frequency * 1000 * 2)); // set Thigh/Tlow to generate frequency (fast duty not used)
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i2c_set_trise(i2c, (300 / (1000 / (rcc_apb1_frequency / 1000000))) + 1); // max rise time for Fm mode (< 400) kHz is 300 ns
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i2c_set_clock_frequency(I2C(I2C_MASTER_I2C), rcc_apb1_frequency / 1000000); // configure the peripheral clock to the APB1 freq (where it is connected to)
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if (frequency > 100) { // use fast mode for frequencies over 100 kHz
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i2c_set_fast_mode(I2C(I2C_MASTER_I2C)); // set fast mode (Fm)
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i2c_set_ccr(I2C(I2C_MASTER_I2C), rcc_apb1_frequency / (frequency * 1000 * 2)); // set Thigh/Tlow to generate frequency (fast duty not used)
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i2c_set_trise(I2C(I2C_MASTER_I2C), (300 / (1000 / (rcc_apb1_frequency / 1000000))) + 1); // max rise time for Fm mode (< 400) kHz is 300 ns
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} else { // use fast mode for frequencies below 100 kHz
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i2c_set_standard_mode(i2c); // set standard mode (Sm)
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i2c_set_ccr(i2c, rcc_apb1_frequency / (frequency * 1000 * 2)); // set Thigh/Tlow to generate frequency of 100 kHz
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i2c_set_trise(i2c, (1000 / (1000 / (rcc_apb1_frequency / 1000000))) + 1); // max rise time for Sm mode (< 100 kHz) is 1000 ns (~1 MHz)
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i2c_set_standard_mode(I2C(I2C_MASTER_I2C)); // set standard mode (Sm)
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i2c_set_ccr(I2C(I2C_MASTER_I2C), rcc_apb1_frequency / (frequency * 1000 * 2)); // set Thigh/Tlow to generate frequency of 100 kHz
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i2c_set_trise(I2C(I2C_MASTER_I2C), (1000 / (1000 / (rcc_apb1_frequency / 1000000))) + 1); // max rise time for Sm mode (< 100 kHz) is 1000 ns (~1 MHz)
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}
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i2c_peripheral_enable(i2c); // enable I²C after configuration completed
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i2c_peripheral_enable(I2C(I2C_MASTER_I2C)); // enable I²C after configuration completed
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}
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void i2c_master_release(uint32_t i2c)
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void i2c_master_release(void)
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{
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cm3_assert(I2C1 == i2c || I2C2 == i2c);
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i2c_reset(i2c); // reset I²C peripheral configuration
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i2c_peripheral_disable(i2c); // disable I²C peripheral
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rcc_periph_clock_disable(RCC_I2C(i2c)); // disable clock for I²C peripheral
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gpio_set_mode(GPIO_PORT_SCL(i2c), GPIO_MODE_INPUT, GPIO_CNF_INPUT_FLOAT, GPIO_PIN_SCL(i2c)); // put I²C I/O pins back to floating
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gpio_set_mode(GPIO_PORT_SDA(i2c), GPIO_MODE_INPUT, GPIO_CNF_INPUT_FLOAT, GPIO_PIN_SDA(i2c)); // put I²C I/O pins back to floating
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i2c_reset(I2C(I2C_MASTER_I2C)); // reset I²C peripheral configuration
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i2c_peripheral_disable(I2C(I2C_MASTER_I2C)); // disable I²C peripheral
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rcc_periph_clock_disable(RCC_I2C(I2C_MASTER_I2C)); // disable clock for I²C peripheral
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gpio_mode_setup(GPIO_PORT(I2C_MASTER_SCL), GPIO_MODE_INPUT, GPIO_PUPD_NONE, GPIO_PIN(I2C_MASTER_SCL)); // set SCL pin back to input
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gpio_mode_setup(GPIO_PORT(I2C_MASTER_SDA), GPIO_MODE_INPUT, GPIO_PUPD_NONE, GPIO_PIN(I2C_MASTER_SDA)); // set SDA pin back to input
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}
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bool i2c_master_check_signals(uint32_t i2c)
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bool i2c_master_check_signals(void)
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{
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cm3_assert(I2C1 == i2c || I2C2 == i2c);
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// enable GPIOs to read SDA and SCL
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rcc_periph_clock_enable(RCC_GPIO_PORT_SDA(i2c)); // enable clock for I²C I/O peripheral
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rcc_periph_clock_enable(RCC_GPIO_PORT_SCL(i2c)); // enable clock for I²C I/O peripheral
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rcc_periph_clock_enable(GPIO_RCC(I2C_MASTER_SDA)); // enable clock for I²C I/O peripheral
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rcc_periph_clock_enable(GPIO_RCC(I2C_MASTER_SCL)); // enable clock for I²C I/O peripheral
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// pull SDA and SDC low to check if there are pull-up resistors
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uint32_t sda_crl = GPIO_CRL(GPIO_PORT_SDA(i2c)); // backup port configuration
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uint32_t sda_crh = GPIO_CRH(GPIO_PORT_SDA(i2c)); // backup port configuration
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uint32_t sda_bsrr = GPIO_BSRR(GPIO_PORT_SDA(i2c)); // backup port configuration
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uint32_t scl_crl = GPIO_CRL(GPIO_PORT_SCL(i2c)); // backup port configuration
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uint32_t scl_crh = GPIO_CRH(GPIO_PORT_SCL(i2c)); // backup port configuration
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uint32_t scl_bsrr = GPIO_BSRR(GPIO_PORT_SCL(i2c)); // backup port configuration
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gpio_set_mode(GPIO_PORT_SDA(i2c), GPIO_MODE_INPUT, GPIO_CNF_INPUT_PULL_UPDOWN, GPIO_PIN_SDA(i2c)); // configure signal as pull down
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gpio_set_mode(GPIO_PORT_SCL(i2c), GPIO_MODE_INPUT, GPIO_CNF_INPUT_PULL_UPDOWN, GPIO_PIN_SCL(i2c)); // configure signal as pull down
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gpio_clear(GPIO_PORT_SDA(i2c), GPIO_PIN_SDA(i2c)); // pull down
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gpio_clear(GPIO_PORT_SCL(i2c), GPIO_PIN_SCL(i2c)); // pull down
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bool to_return = (0 != gpio_get(GPIO_PORT_SCL(i2c), GPIO_PIN_SCL(i2c)) && 0 != gpio_get(GPIO_PORT_SDA(i2c), GPIO_PIN_SDA(i2c))); // check if the signals are still pulled high by external stronger pull-up resistors
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GPIO_CRL(GPIO_PORT_SDA(i2c)) = sda_crl; // restore port configuration
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GPIO_CRH(GPIO_PORT_SDA(i2c)) = sda_crh; // restore port configuration
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GPIO_BSRR(GPIO_PORT_SDA(i2c)) = sda_bsrr; // restore port configuration
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GPIO_CRL(GPIO_PORT_SCL(i2c)) = scl_crl; // restore port configuration
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GPIO_CRH(GPIO_PORT_SCL(i2c)) = scl_crh; // restore port configuration
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GPIO_BSRR(GPIO_PORT_SCL(i2c)) = scl_bsrr; // restore port configuration
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const uint32_t sda_moder = GPIO_MODER(GPIO_PORT(I2C_MASTER_SDA)); // backup port configuration
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const uint32_t sda_pupdr = GPIO_PUPDR(GPIO_PORT(I2C_MASTER_SDA)); // backup port configuration
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const uint32_t scl_moder = GPIO_MODER(GPIO_PORT(I2C_MASTER_SCL)); // backup port configuration
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const uint32_t scl_pupdr = GPIO_PUPDR(GPIO_PORT(I2C_MASTER_SCL)); // backup port configuration
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gpio_mode_setup(GPIO_PORT(I2C_MASTER_SDA), GPIO_MODE_INPUT, GPIO_PUPD_PULLDOWN, GPIO_PIN(I2C_MASTER_SDA)); // set SDA to input and pull down (weak) to check if there is an external pull up (strong)
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gpio_mode_setup(GPIO_PORT(I2C_MASTER_SCL), GPIO_MODE_INPUT, GPIO_PUPD_PULLDOWN, GPIO_PIN(I2C_MASTER_SCL)); // set SCL to input and pull down (weak) to check if there is an external pull up (strong)
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sleep_us(100); // let signal settle
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const bool to_return = (gpio_get(GPIO_PORT(I2C_MASTER_SCL), GPIO_PIN(I2C_MASTER_SCL)) && gpio_get(GPIO_PORT(I2C_MASTER_SDA), GPIO_PIN(I2C_MASTER_SDA))); // check if the signals are still pulled high by external stronger pull-up resistors
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GPIO_MODER(GPIO_PORT(I2C_MASTER_SDA)) = sda_moder; // restore port configuration
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GPIO_PUPDR(GPIO_PORT(I2C_MASTER_SDA)) = sda_pupdr; // restore port configuration
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GPIO_MODER(GPIO_PORT(I2C_MASTER_SCL)) = scl_moder; // restore port configuration
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GPIO_PUPDR(GPIO_PORT(I2C_MASTER_SCL)) = scl_pupdr; // restore port configuration
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return to_return;
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}
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bool i2c_master_reset(uint32_t i2c)
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void i2c_master_reset(void)
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{
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cm3_assert(I2C1 == i2c || I2C2 == i2c);
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bool to_return = true;
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// follow procedure described in STM32F10xxC/D/E Errata sheet, Section 2.14.7
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i2c_peripheral_disable(i2c); // disable I²C peripheral
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gpio_set_mode(GPIO_PORT_SCL(i2c), GPIO_MODE_OUTPUT_10_MHZ, GPIO_CNF_OUTPUT_OPENDRAIN, GPIO_PIN_SCL(i2c)); // put I²C I/O pins to general output
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gpio_set(GPIO_PORT_SCL(i2c), GPIO_PIN_SCL(i2c)); // set high
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to_return &= !gpio_get(GPIO_PORT_SCL(i2c), GPIO_PIN_SCL(i2c)); // ensure it is high
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gpio_set_mode(GPIO_PORT_SDA(i2c), GPIO_MODE_OUTPUT_10_MHZ, GPIO_CNF_OUTPUT_OPENDRAIN, GPIO_PIN_SDA(i2c)); // put I²C I/O pins to general output
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gpio_set(GPIO_PORT_SDA(i2c), GPIO_PIN_SDA(i2c)); // set high
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to_return &= !gpio_get(GPIO_PORT_SDA(i2c), GPIO_PIN_SDA(i2c)); // ensure it is high
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gpio_clear(GPIO_PORT_SDA(i2c), GPIO_PIN_SDA(i2c)); // set low (try first transition)
|
||||
to_return &= gpio_get(GPIO_PORT_SDA(i2c), GPIO_PIN_SDA(i2c)); // ensure it is low
|
||||
gpio_clear(GPIO_PORT_SCL(i2c), GPIO_PIN_SCL(i2c)); // set low (try first transition)
|
||||
to_return &= gpio_get(GPIO_PORT_SCL(i2c), GPIO_PIN_SCL(i2c)); // ensure it is low
|
||||
gpio_set(GPIO_PORT_SCL(i2c), GPIO_PIN_SCL(i2c)); // set high (try second transition)
|
||||
to_return &= !gpio_get(GPIO_PORT_SCL(i2c), GPIO_PIN_SCL(i2c)); // ensure it is high
|
||||
gpio_set(GPIO_PORT_SDA(i2c), GPIO_PIN_SDA(i2c)); // set high (try second transition)
|
||||
to_return &= !gpio_get(GPIO_PORT_SDA(i2c), GPIO_PIN_SDA(i2c)); // ensure it is high
|
||||
gpio_set_mode(GPIO_PORT_SCL(i2c), GPIO_MODE_OUTPUT_10_MHZ, GPIO_CNF_OUTPUT_ALTFN_OPENDRAIN, GPIO_PIN_SCL(i2c)); // set I²C I/O pins back
|
||||
gpio_set_mode(GPIO_PORT_SDA(i2c), GPIO_MODE_OUTPUT_10_MHZ, GPIO_CNF_OUTPUT_ALTFN_OPENDRAIN, GPIO_PIN_SDA(i2c)); // set I²C I/O pins back
|
||||
I2C_CR1(i2c) |= I2C_CR1_SWRST; // reset device
|
||||
I2C_CR1(i2c) &= ~I2C_CR1_SWRST; // reset device
|
||||
i2c_peripheral_enable(i2c); // re-enable device
|
||||
|
||||
return to_return;
|
||||
i2c_peripheral_disable(I2C(I2C_MASTER_I2C)); // disable I²C peripheral
|
||||
I2C_CR1(I2C(I2C_MASTER_I2C)) |= I2C_CR1_SWRST; // reset device
|
||||
I2C_CR1(I2C(I2C_MASTER_I2C)) &= ~I2C_CR1_SWRST; // reset device
|
||||
i2c_peripheral_enable(I2C(I2C_MASTER_I2C)); // re-enable device
|
||||
}
|
||||
|
||||
enum i2c_master_rc i2c_master_start(uint32_t i2c)
|
||||
enum i2c_master_rc i2c_master_start(void)
|
||||
{
|
||||
cm3_assert(I2C1 == i2c || I2C2 == i2c);
|
||||
|
||||
bool retry = true; // retry after reset if first try failed
|
||||
enum i2c_master_rc to_return; // return code
|
||||
uint16_t sr1; // read register once, since reading/writing other registers or other events clears some flags
|
||||
try:
|
||||
to_return = I2C_MASTER_RC_NONE; // return code
|
||||
// send (re-)start condition
|
||||
if (I2C_CR1(i2c) & (I2C_CR1_START | I2C_CR1_STOP)) { // ensure start or stop operations are not in progress
|
||||
if (I2C_CR1(I2C(I2C_MASTER_I2C)) & (I2C_CR1_START | I2C_CR1_STOP)) { // ensure start or stop operations are not in progress
|
||||
return I2C_MASTER_RC_START_STOP_IN_PROGESS;
|
||||
}
|
||||
// prepare timer in case the peripheral hangs on sending stop condition (see errata 2.14.4 Wrong behavior of I²C peripheral in master mode after a misplaced Stop)
|
||||
@ -298,20 +123,20 @@ try:
|
||||
systick_clear(); // reset SysTick (set to 0)
|
||||
systick_interrupt_disable(); // disable interrupt to prevent ISR to read the flag
|
||||
systick_get_countflag(); // reset flag (set when counter is going for 1 to 0)
|
||||
i2c_send_start(i2c); // send start condition to start transaction
|
||||
i2c_send_start(I2C(I2C_MASTER_I2C)); // send start condition to start transaction
|
||||
bool timeout = false; // remember if the timeout has been reached
|
||||
systick_counter_enable(); // start timer
|
||||
while ((I2C_CR1(i2c) & I2C_CR1_START) && !((sr1 = I2C_SR1(i2c)) & (I2C_SR1_BERR | I2C_SR1_ARLO)) && !timeout) { // wait until start condition has been accepted and cleared
|
||||
while ((I2C_CR1(I2C(I2C_MASTER_I2C)) & I2C_CR1_START) && !((sr1 = I2C_SR1(I2C(I2C_MASTER_I2C))) & (I2C_SR1_BERR | I2C_SR1_ARLO)) && !timeout) { // wait until start condition has been accepted and cleared
|
||||
timeout |= systick_get_countflag(); // verify if timeout has been reached
|
||||
}
|
||||
sr1 = I2C_SR1(i2c); // be sure to get the current value
|
||||
sr1 = I2C_SR1(I2C(I2C_MASTER_I2C)); // be sure to get the current value
|
||||
if (sr1 & (I2C_SR1_BERR | I2C_SR1_ARLO)) {
|
||||
to_return = I2C_MASTER_RC_BUS_ERROR;
|
||||
}
|
||||
while (!((sr1 = I2C_SR1(i2c)) & (I2C_SR1_SB | I2C_SR1_BERR | I2C_SR1_ARLO)) && !timeout && I2C_MASTER_RC_NONE == to_return) { // wait until start condition is transmitted
|
||||
while (!((sr1 = I2C_SR1(I2C(I2C_MASTER_I2C))) & (I2C_SR1_SB | I2C_SR1_BERR | I2C_SR1_ARLO)) && !timeout && I2C_MASTER_RC_NONE == to_return) { // wait until start condition is transmitted
|
||||
timeout |= systick_get_countflag(); // verify if timeout has been reached
|
||||
}
|
||||
sr1 = I2C_SR1(i2c); // be sure to get the current value
|
||||
sr1 = I2C_SR1(I2C(I2C_MASTER_I2C)); // be sure to get the current value
|
||||
if (sr1 & (I2C_SR1_BERR|I2C_SR1_ARLO)) {
|
||||
to_return = I2C_MASTER_RC_BUS_ERROR;
|
||||
} else if (!(sr1 & I2C_SR1_SB)) { // the start bit has not been set although we the peripheral is not busy anymore
|
||||
@ -324,8 +149,8 @@ try:
|
||||
|
||||
if (I2C_MASTER_RC_NOT_MASTER == to_return && retry) { // error happened
|
||||
retry = false; // don't retry a second time
|
||||
I2C_CR1(i2c) |= I2C_CR1_SWRST; // assert peripheral reset
|
||||
I2C_CR1(i2c) &= ~I2C_CR1_SWRST; // release peripheral reset
|
||||
I2C_CR1(I2C(I2C_MASTER_I2C)) |= I2C_CR1_SWRST; // assert peripheral reset
|
||||
I2C_CR1(I2C(I2C_MASTER_I2C)) &= ~I2C_CR1_SWRST; // release peripheral reset
|
||||
goto try;
|
||||
}
|
||||
systick_counter_disable(); // we don't need to timer anymore
|
||||
@ -349,25 +174,25 @@ static enum i2c_master_rc i2c_master_wait_stop(uint32_t i2c)
|
||||
systick_get_countflag(); // reset flag (set when counter is going for 1 to 0)
|
||||
bool timeout = false; // remember if the timeout has been reached
|
||||
systick_counter_enable(); // start timer
|
||||
while ((I2C_CR1(i2c) & I2C_CR1_STOP) && !(I2C_SR1(i2c) & (I2C_SR1_BERR | I2C_SR1_ARLO)) && !timeout) { // wait until stop condition is accepted and cleared
|
||||
while ((I2C_CR1(I2C(I2C_MASTER_I2C)) & I2C_CR1_STOP) && !(I2C_SR1(I2C(I2C_MASTER_I2C)) & (I2C_SR1_BERR | I2C_SR1_ARLO)) && !timeout) { // wait until stop condition is accepted and cleared
|
||||
timeout |= systick_get_countflag(); // verify if timeout has been reached
|
||||
}
|
||||
if (I2C_SR1(i2c) & (I2C_SR1_BERR | I2C_SR1_ARLO)) {
|
||||
if (I2C_SR1(I2C(I2C_MASTER_I2C)) & (I2C_SR1_BERR | I2C_SR1_ARLO)) {
|
||||
to_return = I2C_MASTER_RC_BUS_ERROR;
|
||||
}
|
||||
while ((I2C_SR2(i2c) & I2C_SR2_MSL) && !(I2C_SR1(i2c) & (I2C_SR1_BERR | I2C_SR1_ARLO)) && !timeout) { // wait until bus released (non master mode)
|
||||
while ((I2C_SR2(I2C(I2C_MASTER_I2C)) & I2C_SR2_MSL) && !(I2C_SR1(I2C(I2C_MASTER_I2C)) & (I2C_SR1_BERR | I2C_SR1_ARLO)) && !timeout) { // wait until bus released (non master mode)
|
||||
timeout |= systick_get_countflag(); // verify if timeout has been reached
|
||||
}
|
||||
if (I2C_SR1(i2c) & (I2C_SR1_BERR | I2C_SR1_ARLO)) {
|
||||
if (I2C_SR1(I2C(I2C_MASTER_I2C)) & (I2C_SR1_BERR | I2C_SR1_ARLO)) {
|
||||
to_return = I2C_MASTER_RC_BUS_ERROR;
|
||||
}
|
||||
while ((I2C_SR2(i2c) & I2C_SR2_BUSY) && !(I2C_SR1(i2c) & (I2C_SR1_BERR)) && !timeout) { // wait until peripheral is not busy anymore
|
||||
while ((I2C_SR2(I2C(I2C_MASTER_I2C)) & I2C_SR2_BUSY) && !(I2C_SR1(I2C(I2C_MASTER_I2C)) & (I2C_SR1_BERR)) && !timeout) { // wait until peripheral is not busy anymore
|
||||
timeout |= systick_get_countflag(); // verify if timeout has been reached
|
||||
}
|
||||
if (I2C_SR1(i2c) & (I2C_SR1_BERR | I2C_SR1_ARLO)) {
|
||||
if (I2C_SR1(I2C(I2C_MASTER_I2C)) & (I2C_SR1_BERR | I2C_SR1_ARLO)) {
|
||||
to_return = I2C_MASTER_RC_BUS_ERROR;
|
||||
}
|
||||
while ((0 == gpio_get(GPIO_PORT_SCL(i2c), GPIO_PIN_SCL(i2c)) || 0 == gpio_get(GPIO_PORT_SDA(i2c), GPIO_PIN_SDA(i2c))) && !timeout) { // wait until lines are really high again
|
||||
while ((0 == gpio_get(GPIO_PORT(I2C_MASTER_SCL), GPIO_PIN(I2C_MASTER_SCL)) || 0 == gpio_get(GPIO_PORT(I2C_MASTER_SDA), GPIO_PIN(I2C_MASTER_SDA))) && !timeout) { // wait until lines are really high again
|
||||
timeout |= systick_get_countflag(); // verify if timeout has been reached
|
||||
}
|
||||
|
||||
@ -375,55 +200,51 @@ static enum i2c_master_rc i2c_master_wait_stop(uint32_t i2c)
|
||||
if (I2C_MASTER_RC_NONE == to_return) {
|
||||
to_return = I2C_MASTER_RC_TIMEOUT; // indicate timeout only when no more specific error has occurred
|
||||
}
|
||||
I2C_CR1(i2c) |= I2C_CR1_SWRST; // assert peripheral reset
|
||||
I2C_CR1(i2c) &= ~I2C_CR1_SWRST; // release peripheral reset
|
||||
I2C_CR1(I2C(I2C_MASTER_I2C)) |= I2C_CR1_SWRST; // assert peripheral reset
|
||||
I2C_CR1(I2C(I2C_MASTER_I2C)) &= ~I2C_CR1_SWRST; // release peripheral reset
|
||||
}
|
||||
systick_counter_disable(); // we don't need to timer anymore
|
||||
return to_return;
|
||||
}
|
||||
|
||||
enum i2c_master_rc i2c_master_stop(uint32_t i2c)
|
||||
enum i2c_master_rc i2c_master_stop(void)
|
||||
{
|
||||
cm3_assert(I2C1 == i2c || I2C2 == i2c);
|
||||
|
||||
// sanity check
|
||||
if (!(I2C_SR2(i2c) & I2C_SR2_BUSY)) { // release is not busy
|
||||
if (!(I2C_SR2(I2C(I2C_MASTER_I2C)) & I2C_SR2_BUSY)) { // release is not busy
|
||||
return I2C_MASTER_RC_NONE; // bus has probably already been released
|
||||
}
|
||||
if (I2C_CR1(i2c) & (I2C_CR1_START | I2C_CR1_STOP)) { // ensure start or stop operations are not in progress
|
||||
if (I2C_CR1(I2C(I2C_MASTER_I2C)) & (I2C_CR1_START | I2C_CR1_STOP)) { // ensure start or stop operations are not in progress
|
||||
return I2C_MASTER_RC_START_STOP_IN_PROGESS;
|
||||
}
|
||||
|
||||
if (!((I2C_SR2(i2c) & I2C_SR2_TRA))) { // if we are in receiver mode
|
||||
i2c_disable_ack(i2c); // disable ACK to be able to close the communication
|
||||
if (!((I2C_SR2(I2C(I2C_MASTER_I2C)) & I2C_SR2_TRA))) { // if we are in receiver mode
|
||||
i2c_disable_ack(I2C(I2C_MASTER_I2C)); // disable ACK to be able to close the communication
|
||||
}
|
||||
|
||||
i2c_send_stop(i2c); // send stop to release bus
|
||||
return i2c_master_wait_stop(i2c);
|
||||
i2c_send_stop(I2C(I2C_MASTER_I2C)); // send stop to release bus
|
||||
return i2c_master_wait_stop(I2C(I2C_MASTER_I2C));
|
||||
}
|
||||
|
||||
enum i2c_master_rc i2c_master_select_slave(uint32_t i2c, uint16_t slave, bool address_10bit, bool write)
|
||||
enum i2c_master_rc i2c_master_select_slave(uint16_t slave, bool address_10bit, bool write)
|
||||
{
|
||||
cm3_assert(I2C1 == i2c || I2C2 == i2c);
|
||||
|
||||
enum i2c_master_rc rc = I2C_MASTER_RC_NONE; // to store I²C return codes
|
||||
uint16_t sr1, sr2; // read register once, since reading/writing other registers or other events clears some flags
|
||||
|
||||
if (!((sr1 = I2C_SR1(i2c)) & I2C_SR1_SB)) { // start condition has not been sent
|
||||
rc = i2c_master_start(i2c); // send start condition
|
||||
if (!((sr1 = I2C_SR1(I2C(I2C_MASTER_I2C))) & I2C_SR1_SB)) { // start condition has not been sent
|
||||
rc = i2c_master_start(); // send start condition
|
||||
if (I2C_MASTER_RC_NONE != rc) {
|
||||
return rc;
|
||||
}
|
||||
}
|
||||
if (!((sr2 = I2C_SR2(i2c)) & I2C_SR2_MSL)) { // I²C device is not in master mode
|
||||
if (!((sr2 = I2C_SR2(I2C(I2C_MASTER_I2C))) & I2C_SR2_MSL)) { // I²C device is not in master mode
|
||||
return I2C_MASTER_RC_NOT_MASTER;
|
||||
}
|
||||
|
||||
// select slave
|
||||
I2C_SR1(i2c) &= ~(I2C_SR1_AF); // clear acknowledgement failure
|
||||
I2C_SR1(I2C(I2C_MASTER_I2C)) &= ~(I2C_SR1_AF); // clear acknowledgement failure
|
||||
if (!address_10bit) { // 7-bit address
|
||||
i2c_send_7bit_address(i2c, slave, write ? I2C_WRITE : I2C_READ); // select slave, with read/write flag
|
||||
while (!((sr1 = I2C_SR1(i2c)) & (I2C_SR1_ADDR | I2C_SR1_AF | I2C_SR1_BERR | I2C_SR1_ARLO))); // wait until address is transmitted
|
||||
i2c_send_7bit_address(I2C(I2C_MASTER_I2C), slave, write ? I2C_WRITE : I2C_READ); // select slave, with read/write flag
|
||||
while (!((sr1 = I2C_SR1(I2C(I2C_MASTER_I2C))) & (I2C_SR1_ADDR | I2C_SR1_AF | I2C_SR1_BERR | I2C_SR1_ARLO))); // wait until address is transmitted
|
||||
if (sr1 & (I2C_SR1_BERR | I2C_SR1_ARLO)) {
|
||||
return I2C_MASTER_RC_BUS_ERROR;
|
||||
}
|
||||
@ -432,8 +253,8 @@ enum i2c_master_rc i2c_master_select_slave(uint32_t i2c, uint16_t slave, bool ad
|
||||
}
|
||||
} else { // 10-bit address
|
||||
// send first part of address
|
||||
I2C_DR(i2c) = 11110000 | (((slave >> 8 ) & 0x3) << 1); // send first header (11110xx0, where xx are 2 MSb of slave address)
|
||||
while (!((sr1 = I2C_SR1(i2c)) & (I2C_SR1_ADD10 | I2C_SR1_AF | I2C_SR1_BERR | I2C_SR1_ARLO))); // wait until first part of address is transmitted
|
||||
I2C_DR(I2C(I2C_MASTER_I2C)) = 11110000 | (((slave >> 8 ) & 0x3) << 1); // send first header (11110xx0, where xx are 2 MSb of slave address)
|
||||
while (!((sr1 = I2C_SR1(I2C(I2C_MASTER_I2C))) & (I2C_SR1_ADD10 | I2C_SR1_AF | I2C_SR1_BERR | I2C_SR1_ARLO))); // wait until first part of address is transmitted
|
||||
if (sr1 & (I2C_SR1_BERR | I2C_SR1_ARLO)) {
|
||||
return I2C_MASTER_RC_BUS_ERROR;
|
||||
}
|
||||
@ -441,9 +262,9 @@ enum i2c_master_rc i2c_master_select_slave(uint32_t i2c, uint16_t slave, bool ad
|
||||
return I2C_MASTER_RC_NAK;
|
||||
}
|
||||
// send second part of address
|
||||
I2C_SR1(i2c) &= ~(I2C_SR1_AF); // clear acknowledgement failure
|
||||
I2C_DR(i2c) = (slave & 0xff); // send remaining of address
|
||||
while (!((sr1 = I2C_SR1(i2c)) & (I2C_SR1_ADDR | I2C_SR1_AF | I2C_SR1_BERR | I2C_SR1_ARLO))); // wait until remaining part of address is transmitted
|
||||
I2C_SR1(I2C(I2C_MASTER_I2C)) &= ~(I2C_SR1_AF); // clear acknowledgement failure
|
||||
I2C_DR(I2C(I2C_MASTER_I2C)) = (slave & 0xff); // send remaining of address
|
||||
while (!((sr1 = I2C_SR1(I2C(I2C_MASTER_I2C))) & (I2C_SR1_ADDR | I2C_SR1_AF | I2C_SR1_BERR | I2C_SR1_ARLO))); // wait until remaining part of address is transmitted
|
||||
if (sr1 & (I2C_SR1_BERR | I2C_SR1_ARLO)) {
|
||||
return I2C_MASTER_RC_BUS_ERROR;
|
||||
}
|
||||
@ -452,14 +273,14 @@ enum i2c_master_rc i2c_master_select_slave(uint32_t i2c, uint16_t slave, bool ad
|
||||
}
|
||||
// go into receive mode if necessary
|
||||
if (!write) {
|
||||
rc = i2c_master_start(i2c); // send start condition
|
||||
rc = i2c_master_start(); // send start condition
|
||||
if (I2C_MASTER_RC_NONE != rc) {
|
||||
return rc;
|
||||
}
|
||||
// send first part of address with receive flag
|
||||
I2C_SR1(i2c) &= ~(I2C_SR1_AF); // clear acknowledgement failure
|
||||
I2C_DR(i2c) = 11110001 | (((slave >> 8) & 0x3) << 1); // send header (11110xx1, where xx are 2 MSb of slave address)
|
||||
while (!((sr1 = I2C_SR1(i2c)) & (I2C_SR1_ADDR | I2C_SR1_AF | I2C_SR1_BERR | I2C_SR1_ARLO))); // wait until remaining part of address is transmitted
|
||||
I2C_SR1(I2C(I2C_MASTER_I2C)) &= ~(I2C_SR1_AF); // clear acknowledgement failure
|
||||
I2C_DR(I2C(I2C_MASTER_I2C)) = 11110001 | (((slave >> 8) & 0x3) << 1); // send header (11110xx1, where xx are 2 MSb of slave address)
|
||||
while (!((sr1 = I2C_SR1(I2C(I2C_MASTER_I2C))) & (I2C_SR1_ADDR | I2C_SR1_AF | I2C_SR1_BERR | I2C_SR1_ARLO))); // wait until remaining part of address is transmitted
|
||||
if (sr1 & (I2C_SR1_BERR | I2C_SR1_ARLO)) {
|
||||
return I2C_MASTER_RC_BUS_ERROR;
|
||||
}
|
||||
@ -472,17 +293,15 @@ enum i2c_master_rc i2c_master_select_slave(uint32_t i2c, uint16_t slave, bool ad
|
||||
return I2C_MASTER_RC_NONE;
|
||||
}
|
||||
|
||||
enum i2c_master_rc i2c_master_read(uint32_t i2c, uint8_t* data, size_t data_size)
|
||||
enum i2c_master_rc i2c_master_read(uint8_t* data, size_t data_size)
|
||||
{
|
||||
cm3_assert(I2C1 == i2c || I2C2 == i2c);
|
||||
|
||||
// sanity check
|
||||
if (NULL == data || 0 == data_size) { // no data to read
|
||||
return I2C_MASTER_RC_NONE;
|
||||
}
|
||||
|
||||
// I²C start condition check
|
||||
uint16_t sr1 = I2C_SR1(i2c); // read once
|
||||
uint16_t sr1 = I2C_SR1(I2C(I2C_MASTER_I2C)); // read once
|
||||
if (!(sr1 & I2C_SR1_ADDR)) { // no slave have been selected
|
||||
return I2C_MASTER_RC_NOT_READY;
|
||||
}
|
||||
@ -492,11 +311,11 @@ enum i2c_master_rc i2c_master_read(uint32_t i2c, uint8_t* data, size_t data_size
|
||||
|
||||
// prepare (N)ACK (EV6_3 in RM0008)
|
||||
if (1 == data_size) {
|
||||
i2c_disable_ack(i2c); // NACK after first byte
|
||||
i2c_disable_ack(I2C(I2C_MASTER_I2C)); // NACK after first byte
|
||||
} else {
|
||||
i2c_enable_ack(i2c); // NAK after next byte
|
||||
i2c_enable_ack(I2C(I2C_MASTER_I2C)); // NAK after next byte
|
||||
}
|
||||
uint16_t sr2 = I2C_SR2(i2c); // reading SR2 will also also clear ADDR in SR1 and start the transaction
|
||||
uint16_t sr2 = I2C_SR2(I2C(I2C_MASTER_I2C)); // reading SR2 will also also clear ADDR in SR1 and start the transaction
|
||||
if (!(sr2 & I2C_SR2_MSL)) { // I²C device is not master
|
||||
return I2C_MASTER_RC_NOT_MASTER;
|
||||
}
|
||||
@ -508,36 +327,34 @@ enum i2c_master_rc i2c_master_read(uint32_t i2c, uint8_t* data, size_t data_size
|
||||
for (size_t i = 0; i < data_size; i++) { // read bytes
|
||||
// set (N)ACK (EV6_3, EV6_1)
|
||||
if (1 == data_size - i) { // prepare to sent NACK for last byte
|
||||
i2c_send_stop(i2c); // already indicate we will send a stop (required to not send an ACK, and this must happen before the byte is transferred, see errata)
|
||||
i2c_nack_current(i2c); // (N)ACK current byte
|
||||
i2c_disable_ack(i2c); // NACK received to stop slave transmission
|
||||
i2c_send_stop(I2C(I2C_MASTER_I2C)); // already indicate we will send a stop (required to not send an ACK, and this must happen before the byte is transferred, see errata)
|
||||
i2c_nack_current(I2C(I2C_MASTER_I2C)); // (N)ACK current byte
|
||||
i2c_disable_ack(I2C(I2C_MASTER_I2C)); // NACK received to stop slave transmission
|
||||
} else if (2 == data_size - i) { // prepare to sent NACK for second last byte
|
||||
i2c_nack_next(i2c); // NACK next byte
|
||||
i2c_disable_ack(i2c); // NACK received to stop slave transmission
|
||||
i2c_nack_next(I2C(I2C_MASTER_I2C)); // NACK next byte
|
||||
i2c_disable_ack(I2C(I2C_MASTER_I2C)); // NACK received to stop slave transmission
|
||||
} else {
|
||||
i2c_enable_ack(i2c); // ACK received byte to continue slave transmission
|
||||
i2c_enable_ack(I2C(I2C_MASTER_I2C)); // ACK received byte to continue slave transmission
|
||||
}
|
||||
while (!((sr1 = I2C_SR1(i2c)) & (I2C_SR1_RxNE | I2C_SR1_BERR | I2C_SR1_ARLO))); // wait until byte has been received
|
||||
while (!((sr1 = I2C_SR1(I2C(I2C_MASTER_I2C))) & (I2C_SR1_RxNE | I2C_SR1_BERR | I2C_SR1_ARLO))); // wait until byte has been received
|
||||
if (sr1 & (I2C_SR1_BERR|I2C_SR1_ARLO)) {
|
||||
return I2C_MASTER_RC_BUS_ERROR;
|
||||
}
|
||||
data[i] = i2c_get_data(i2c); // read received byte
|
||||
data[i] = i2c_get_data(I2C(I2C_MASTER_I2C)); // read received byte
|
||||
}
|
||||
|
||||
return i2c_master_wait_stop(i2c);
|
||||
return i2c_master_wait_stop(I2C(I2C_MASTER_I2C));
|
||||
}
|
||||
|
||||
enum i2c_master_rc i2c_master_write(uint32_t i2c, const uint8_t* data, size_t data_size)
|
||||
enum i2c_master_rc i2c_master_write(const uint8_t* data, size_t data_size)
|
||||
{
|
||||
cm3_assert(I2C1 == i2c || I2C2 == i2c);
|
||||
|
||||
// sanity check
|
||||
if (NULL == data || 0 == data_size) { // no data to write
|
||||
return I2C_MASTER_RC_NONE;
|
||||
}
|
||||
|
||||
// I²C start condition check
|
||||
uint16_t sr1 = I2C_SR1(i2c); // read once
|
||||
uint16_t sr1 = I2C_SR1(I2C(I2C_MASTER_I2C)); // read once
|
||||
if (!(sr1 & I2C_SR1_ADDR)) { // no slave have been selected
|
||||
return I2C_MASTER_RC_NOT_READY;
|
||||
}
|
||||
@ -546,7 +363,7 @@ enum i2c_master_rc i2c_master_write(uint32_t i2c, const uint8_t* data, size_t da
|
||||
}
|
||||
|
||||
// master check
|
||||
uint16_t sr2 = I2C_SR2(i2c); // reading SR2 will also also clear ADDR in SR1 and start the transaction
|
||||
uint16_t sr2 = I2C_SR2(I2C(I2C_MASTER_I2C)); // reading SR2 will also also clear ADDR in SR1 and start the transaction
|
||||
if (!(sr2 & I2C_SR2_MSL)) { // I²C device is not master
|
||||
return I2C_MASTER_RC_NOT_MASTER;
|
||||
}
|
||||
@ -556,13 +373,13 @@ enum i2c_master_rc i2c_master_write(uint32_t i2c, const uint8_t* data, size_t da
|
||||
|
||||
// write data
|
||||
for (size_t i = 0; i < data_size; i++) { // write bytes
|
||||
I2C_SR1(i2c) &= ~(I2C_SR1_AF); // clear acknowledgement failure
|
||||
i2c_send_data(i2c, data[i]); // send byte to be written in memory
|
||||
while (!(I2C_SR1(i2c) & (I2C_SR1_TxE | I2C_SR1_AF)) && !(I2C_SR1(i2c) & (I2C_SR1_BERR | I2C_SR1_ARLO))); // wait until byte has been transmitted
|
||||
if (I2C_SR1(i2c) & (I2C_SR1_BERR | I2C_SR1_ARLO)) {
|
||||
I2C_SR1(I2C(I2C_MASTER_I2C)) &= ~(I2C_SR1_AF); // clear acknowledgement failure
|
||||
i2c_send_data(I2C(I2C_MASTER_I2C), data[i]); // send byte to be written in memory
|
||||
while (!(I2C_SR1(I2C(I2C_MASTER_I2C)) & (I2C_SR1_TxE | I2C_SR1_AF)) && !(I2C_SR1(I2C(I2C_MASTER_I2C)) & (I2C_SR1_BERR | I2C_SR1_ARLO))); // wait until byte has been transmitted
|
||||
if (I2C_SR1(I2C(I2C_MASTER_I2C)) & (I2C_SR1_BERR | I2C_SR1_ARLO)) {
|
||||
return I2C_MASTER_RC_BUS_ERROR;
|
||||
}
|
||||
if (I2C_SR1(i2c) & I2C_SR1_AF) { // data has not been acknowledged
|
||||
if (I2C_SR1(I2C(I2C_MASTER_I2C)) & I2C_SR1_AF) { // data has not been acknowledged
|
||||
return I2C_MASTER_RC_NAK;
|
||||
}
|
||||
}
|
||||
@ -570,51 +387,47 @@ enum i2c_master_rc i2c_master_write(uint32_t i2c, const uint8_t* data, size_t da
|
||||
return I2C_MASTER_RC_NONE;
|
||||
}
|
||||
|
||||
enum i2c_master_rc i2c_master_slave_read(uint32_t i2c, uint16_t slave, bool address_10bit, uint8_t* data, size_t data_size)
|
||||
enum i2c_master_rc i2c_master_slave_read(uint16_t slave, bool address_10bit, uint8_t* data, size_t data_size)
|
||||
{
|
||||
cm3_assert(I2C1 == i2c || I2C2 == i2c);
|
||||
|
||||
enum i2c_master_rc rc = I2C_MASTER_RC_NONE; // to store I²C return codes
|
||||
rc = i2c_master_start(i2c); // send (re-)start condition
|
||||
rc = i2c_master_start(); // send (re-)start condition
|
||||
if (I2C_MASTER_RC_NONE != rc) {
|
||||
return rc;
|
||||
}
|
||||
rc = i2c_master_select_slave(i2c, slave, address_10bit, false); // select slave to read
|
||||
rc = i2c_master_select_slave(slave, address_10bit, false); // select slave to read
|
||||
if (I2C_MASTER_RC_NONE != rc) {
|
||||
goto error;
|
||||
}
|
||||
if (NULL != data && data_size > 0) { // only read data if needed
|
||||
rc = i2c_master_read(i2c, data, data_size); // read data (includes stop)
|
||||
rc = i2c_master_read(data, data_size); // read data (includes stop)
|
||||
if (I2C_MASTER_RC_NONE != rc) {
|
||||
goto error;
|
||||
}
|
||||
} else {
|
||||
i2c_master_stop(i2c); // sent stop condition
|
||||
i2c_master_stop(); // sent stop condition
|
||||
}
|
||||
|
||||
rc = I2C_MASTER_RC_NONE; // all went well
|
||||
error:
|
||||
if (I2C_MASTER_RC_NONE != rc) {
|
||||
i2c_master_stop(i2c); // sent stop condition
|
||||
i2c_master_stop(); // sent stop condition
|
||||
}
|
||||
return rc;
|
||||
}
|
||||
|
||||
enum i2c_master_rc i2c_master_slave_write(uint32_t i2c, uint16_t slave, bool address_10bit, const uint8_t* data, size_t data_size)
|
||||
enum i2c_master_rc i2c_master_slave_write(uint16_t slave, bool address_10bit, const uint8_t* data, size_t data_size)
|
||||
{
|
||||
cm3_assert(I2C1 == i2c || I2C2 == i2c);
|
||||
|
||||
enum i2c_master_rc rc = I2C_MASTER_RC_NONE; // to store I²C return codes
|
||||
rc = i2c_master_start(i2c); // send (re-)start condition
|
||||
rc = i2c_master_start(); // send (re-)start condition
|
||||
if (I2C_MASTER_RC_NONE != rc) {
|
||||
return rc;
|
||||
}
|
||||
rc = i2c_master_select_slave(i2c, slave, address_10bit, true); // select slave to write
|
||||
rc = i2c_master_select_slave(slave, address_10bit, true); // select slave to write
|
||||
if (I2C_MASTER_RC_NONE != rc) {
|
||||
goto error;
|
||||
}
|
||||
if (NULL != data && data_size > 0) { // write data only is some is available
|
||||
rc = i2c_master_write(i2c, data, data_size); // write data
|
||||
rc = i2c_master_write(data, data_size); // write data
|
||||
if (I2C_MASTER_RC_NONE != rc) {
|
||||
goto error;
|
||||
}
|
||||
@ -622,60 +435,57 @@ enum i2c_master_rc i2c_master_slave_write(uint32_t i2c, uint16_t slave, bool add
|
||||
|
||||
rc = I2C_MASTER_RC_NONE; // all went well
|
||||
error:
|
||||
i2c_master_stop(i2c); // sent stop condition
|
||||
i2c_master_stop(); // sent stop condition
|
||||
return rc;
|
||||
}
|
||||
|
||||
enum i2c_master_rc i2c_master_address_read(uint32_t i2c, uint16_t slave, bool address_10bit, const uint8_t* address, size_t address_size, uint8_t* data, size_t data_size)
|
||||
enum i2c_master_rc i2c_master_address_read(uint16_t slave, bool address_10bit, const uint8_t* address, size_t address_size, uint8_t* data, size_t data_size)
|
||||
{
|
||||
cm3_assert(I2C1 == i2c || I2C2 == i2c);
|
||||
|
||||
enum i2c_master_rc rc = I2C_MASTER_RC_NONE; // to store I²C return codes
|
||||
rc = i2c_master_start(i2c); // send (re-)start condition
|
||||
rc = i2c_master_start(); // send (re-)start condition
|
||||
if (I2C_MASTER_RC_NONE != rc) {
|
||||
return rc;
|
||||
}
|
||||
rc = i2c_master_select_slave(i2c, slave, address_10bit, true); // select slave to write
|
||||
rc = i2c_master_select_slave(slave, address_10bit, true); // select slave to write
|
||||
if (I2C_MASTER_RC_NONE != rc) {
|
||||
goto error;
|
||||
}
|
||||
|
||||
// write address
|
||||
if (NULL != address && address_size > 0) {
|
||||
rc = i2c_master_write(i2c, address, address_size); // send memory address
|
||||
rc = i2c_master_write(address, address_size); // send memory address
|
||||
if (I2C_MASTER_RC_NONE != rc) {
|
||||
goto error;
|
||||
}
|
||||
}
|
||||
// read data
|
||||
if (NULL != data && data_size > 0) {
|
||||
rc = i2c_master_start(i2c); // send re-start condition
|
||||
rc = i2c_master_start(); // send re-start condition
|
||||
if (I2C_MASTER_RC_NONE != rc) {
|
||||
return rc;
|
||||
}
|
||||
rc = i2c_master_select_slave(i2c, slave, address_10bit, false); // select slave to read
|
||||
rc = i2c_master_select_slave(slave, address_10bit, false); // select slave to read
|
||||
if (I2C_MASTER_RC_NONE != rc) {
|
||||
goto error;
|
||||
}
|
||||
rc = i2c_master_read(i2c, data, data_size); // read memory (includes stop)
|
||||
rc = i2c_master_read(data, data_size); // read memory (includes stop)
|
||||
if (I2C_MASTER_RC_NONE != rc) {
|
||||
goto error;
|
||||
}
|
||||
} else {
|
||||
i2c_master_stop(i2c); // sent stop condition
|
||||
i2c_master_stop(); // sent stop condition
|
||||
}
|
||||
|
||||
rc = I2C_MASTER_RC_NONE;
|
||||
error:
|
||||
if (I2C_MASTER_RC_NONE != rc) { // only send stop on error
|
||||
i2c_master_stop(i2c); // sent stop condition
|
||||
i2c_master_stop(); // sent stop condition
|
||||
}
|
||||
return rc;
|
||||
}
|
||||
|
||||
enum i2c_master_rc i2c_master_address_write(uint32_t i2c, uint16_t slave, bool address_10bit, const uint8_t* address, size_t address_size, const uint8_t* data, size_t data_size)
|
||||
enum i2c_master_rc i2c_master_address_write(uint16_t slave, bool address_10bit, const uint8_t* address, size_t address_size, const uint8_t* data, size_t data_size)
|
||||
{
|
||||
cm3_assert(I2C1 == i2c || I2C2 == i2c);
|
||||
if (SIZE_MAX - address_size < data_size) { // prevent integer overflow
|
||||
return I2C_MASTER_RC_OTHER;
|
||||
}
|
||||
@ -691,11 +501,11 @@ enum i2c_master_rc i2c_master_address_write(uint32_t i2c, uint16_t slave, bool a
|
||||
|
||||
uint8_t buffer[address_size + data_size];
|
||||
enum i2c_master_rc rc = I2C_MASTER_RC_NONE; // to store I²C return codes
|
||||
rc = i2c_master_start(i2c); // send (re-)start condition
|
||||
rc = i2c_master_start(); // send (re-)start condition
|
||||
if (I2C_MASTER_RC_NONE != rc) {
|
||||
return rc;
|
||||
}
|
||||
rc = i2c_master_select_slave(i2c, slave, address_10bit, true); // select slave to write
|
||||
rc = i2c_master_select_slave(slave, address_10bit, true); // select slave to write
|
||||
if (I2C_MASTER_RC_NONE != rc) {
|
||||
goto error;
|
||||
}
|
||||
@ -711,12 +521,12 @@ enum i2c_master_rc i2c_master_address_write(uint32_t i2c, uint16_t slave, bool a
|
||||
buffer[address_size + i] = data[i];
|
||||
}
|
||||
}
|
||||
rc = i2c_master_write(i2c, buffer, address_size + data_size); // send memory address
|
||||
rc = i2c_master_write(buffer, address_size + data_size); // send memory address
|
||||
if (I2C_MASTER_RC_NONE != rc) {
|
||||
goto error;
|
||||
}
|
||||
|
||||
error:
|
||||
rc = i2c_master_stop(i2c); // sent stop condition
|
||||
rc = i2c_master_stop(); // sent stop condition
|
||||
return rc;
|
||||
}
|
||||
|
||||
@ -3,10 +3,9 @@
|
||||
* @author King Kévin <kingkevin@cuvoodoo.info>
|
||||
* @copyright SPDX-License-Identifier: GPL-3.0-or-later
|
||||
* @date 2017-2020
|
||||
* @note peripherals used: I2C
|
||||
* @note peripherals used: I²C @ref i2c_master_i2c
|
||||
*/
|
||||
#pragma once
|
||||
#error not converted for STM32F4
|
||||
|
||||
/** I²C return codes */
|
||||
enum i2c_master_rc {
|
||||
@ -23,66 +22,55 @@ enum i2c_master_rc {
|
||||
};
|
||||
|
||||
/** setup I²C peripheral
|
||||
* @param[in] i2c I²C base address
|
||||
* @param[in] frequency frequency to use in kHz (1-400)
|
||||
* @note Standard mode (Sm) is used for frequencies up to 100 kHz, and Fast mode (Fm) is used for frequencies up to 400 kHz
|
||||
*/
|
||||
void i2c_master_setup(uint32_t i2c, uint16_t frequency);
|
||||
void i2c_master_setup(uint16_t frequency);
|
||||
/** release I²C peripheral
|
||||
* @param[in] i2c I²C base address
|
||||
*/
|
||||
void i2c_master_release(uint32_t i2c);
|
||||
void i2c_master_release(void);
|
||||
/** reset I2C peripheral, fixing any locked state
|
||||
* @warning the I2C peripheral needs to be re-setup
|
||||
* @note to be used after failed start or stop, and bus error
|
||||
* @param[in] i2c I2C base address
|
||||
* @return true if complete reset is successful, false if the lines could not be set
|
||||
*/
|
||||
bool i2c_master_reset(uint32_t i2c);
|
||||
/** check if SDA and SCL signals are high
|
||||
* @param[in] i2c I²C base address
|
||||
* @return SDA and SCL signals are high
|
||||
void i2c_master_reset(void);
|
||||
/** check if SDA and SCL signals are pulled up externally
|
||||
* @return SDA and SCL signals are pulled up externally
|
||||
*/
|
||||
bool i2c_master_check_signals(uint32_t i2c);
|
||||
bool i2c_master_check_signals(void);
|
||||
/** send start condition
|
||||
* @param[in] i2c I²C base address
|
||||
* @return I2C return code
|
||||
*/
|
||||
enum i2c_master_rc i2c_master_start(uint32_t i2c);
|
||||
enum i2c_master_rc i2c_master_start(void);
|
||||
/** select I²C slave device
|
||||
* @warning a start condition should be sent before this operation
|
||||
* @param[in] i2c I²C base address
|
||||
* @param[in] slave I²C address of slave device to select
|
||||
* @param[in] address_10bit if the I²C slave address is 10 bits wide
|
||||
* @param[in] write this transaction will be followed by a read (false) or write (true) operation
|
||||
* @return I²C return code
|
||||
*/
|
||||
enum i2c_master_rc i2c_master_select_slave(uint32_t i2c, uint16_t slave, bool address_10bit, bool write);
|
||||
enum i2c_master_rc i2c_master_select_slave(uint16_t slave, bool address_10bit, bool write);
|
||||
/** read data over I²C
|
||||
* @param[in] i2c I²C base address
|
||||
* @param[out] data array to store bytes read
|
||||
* @param[in] data_size number of bytes to read
|
||||
* @return I²C return code
|
||||
* @warning the slave device must be selected before this operation
|
||||
* @note a stop condition will be sent at the end (I²C does not permit multiple reads, and this is necessary for 1-byte transfer)
|
||||
*/
|
||||
enum i2c_master_rc i2c_master_read(uint32_t i2c, uint8_t* data, size_t data_size);
|
||||
enum i2c_master_rc i2c_master_read(uint8_t* data, size_t data_size);
|
||||
/** write data over I²C
|
||||
* @param[in] i2c I²C base address
|
||||
* @param[in] data array of byte to write to slave
|
||||
* @param[in] data_size number of bytes to write
|
||||
* @return I²C return code
|
||||
* @warning the slave device must be selected before this operation
|
||||
* @note no stop condition is sent at the end, allowing multiple writes
|
||||
*/
|
||||
enum i2c_master_rc i2c_master_write(uint32_t i2c, const uint8_t* data, size_t data_size);
|
||||
enum i2c_master_rc i2c_master_write(const uint8_t* data, size_t data_size);
|
||||
/** sent stop condition
|
||||
* @param[in] i2c I²C base address
|
||||
* @return I²C return code
|
||||
*/
|
||||
enum i2c_master_rc i2c_master_stop(uint32_t i2c);
|
||||
enum i2c_master_rc i2c_master_stop(void);
|
||||
/** read data from slave device
|
||||
* @param[in] i2c I²C base address
|
||||
* @param[in] slave I²C address of slave device to select
|
||||
* @param[in] address_10bit if the I²C slave address is 10 bits wide
|
||||
* @param[out] data array to store bytes read
|
||||
@ -90,9 +78,8 @@ enum i2c_master_rc i2c_master_stop(uint32_t i2c);
|
||||
* @return I²C return code
|
||||
* @note start and stop conditions are included
|
||||
*/
|
||||
enum i2c_master_rc i2c_master_slave_read(uint32_t i2c, uint16_t slave, bool address_10bit, uint8_t* data, size_t data_size);
|
||||
enum i2c_master_rc i2c_master_slave_read(uint16_t slave, bool address_10bit, uint8_t* data, size_t data_size);
|
||||
/** write data to slave device
|
||||
* @param[in] i2c I²C base address
|
||||
* @param[in] slave I²C address of slave device to select
|
||||
* @param[in] address_10bit if the I²C slave address is 10 bits wide
|
||||
* @param[in] data array of byte to write to slave
|
||||
@ -100,9 +87,8 @@ enum i2c_master_rc i2c_master_slave_read(uint32_t i2c, uint16_t slave, bool addr
|
||||
* @return I²C return code
|
||||
* @note start and stop conditions are included
|
||||
*/
|
||||
enum i2c_master_rc i2c_master_slave_write(uint32_t i2c, uint16_t slave, bool address_10bit, const uint8_t* data, size_t data_size);
|
||||
enum i2c_master_rc i2c_master_slave_write(uint16_t slave, bool address_10bit, const uint8_t* data, size_t data_size);
|
||||
/** read data at specific address from an I²C memory slave
|
||||
* @param[in] i2c I²C base address
|
||||
* @param[in] slave I²C address of slave device to select
|
||||
* @param[in] address_10bit if the I²C slave address is 10 bits wide
|
||||
* @param[in] address memory address of slave to read from
|
||||
@ -112,9 +98,8 @@ enum i2c_master_rc i2c_master_slave_write(uint32_t i2c, uint16_t slave, bool add
|
||||
* @return I²C return code
|
||||
* @note start and stop conditions are included
|
||||
*/
|
||||
enum i2c_master_rc i2c_master_address_read(uint32_t i2c, uint16_t slave, bool address_10bit, const uint8_t* address, size_t address_size, uint8_t* data, size_t data_size);
|
||||
enum i2c_master_rc i2c_master_address_read(uint16_t slave, bool address_10bit, const uint8_t* address, size_t address_size, uint8_t* data, size_t data_size);
|
||||
/** write data at specific address on an I²C memory slave
|
||||
* @param[in] i2c I²C base address
|
||||
* @param[in] slave I²C address of slave device to select
|
||||
* @param[in] address_10bit if the I²C slave address is 10 bits wide
|
||||
* @param[in] address memory address of slave to write to
|
||||
@ -124,4 +109,4 @@ enum i2c_master_rc i2c_master_address_read(uint32_t i2c, uint16_t slave, bool ad
|
||||
* @return I²C return code
|
||||
* @note start and stop conditions are included
|
||||
*/
|
||||
enum i2c_master_rc i2c_master_address_write(uint32_t i2c, uint16_t slave, bool address_10bit, const uint8_t* address, size_t address_size, const uint8_t* data, size_t data_size);
|
||||
enum i2c_master_rc i2c_master_address_write(uint16_t slave, bool address_10bit, const uint8_t* address, size_t address_size, const uint8_t* data, size_t data_size);
|
||||
|
||||
Loading…
Reference in New Issue
Block a user