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application: add MCU verification to version action

This commit is contained in:
King Kévin 2020-03-15 18:25:51 +01:00
parent b1c13e7c15
commit 8b4f98d79a
1 changed files with 72 additions and 1 deletions
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73
application.c
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@ -321,10 +321,81 @@ static void command_version(void* argument)
}
// display device identity
printf("device id: %08x%08x%04x%04x\n", DESIG_UNIQUE_ID2, DESIG_UNIQUE_ID1, DESIG_UNIQUE_ID0 & 0xffff, DESIG_UNIQUE_ID0 >> 16);
// from RM0091 STM32F0x8 reference manual
// from RM0091 STM32F0x8 reference manual (not sure if it applies to F1)
printf("- X,Y wafer coordinate: %08x\n", DESIG_UNIQUE_ID0);
printf("- lot number: %c%c%c%c%c%c%c\n", DESIG_UNIQUE_ID2 >> 24, DESIG_UNIQUE_ID2 >> 16, DESIG_UNIQUE_ID2 >> 8, DESIG_UNIQUE_ID2 >> 0, DESIG_UNIQUE_ID1 >> 24, DESIG_UNIQUE_ID1 >> 16, DESIG_UNIQUE_ID1 >> 8);
printf("- wafer number: %u\n", DESIG_UNIQUE_ID1 & 0xff);
// from ARMv7-M and Cortex-M3 TRM
// ARMv7-M B3.2.3
printf("CPUID: 0x%08x\n", SCB_CPUID);
const uint8_t cpuid_implementer = (SCB_CPUID & SCB_CPUID_IMPLEMENTER) >> SCB_CPUID_IMPLEMENTER_LSB;
printf("- implementer: %s (0x%02x)\n", 0x41 == cpuid_implementer ? "ARM" : "unknown", cpuid_implementer);
const uint8_t cpuid_architecture = (SCB_CPUID & SCB_CPUID_CONSTANT) >> SCB_CPUID_CONSTANT_LSB;
puts("- architecture: ");
switch (cpuid_architecture) {
case 0xc:
puts("ARMv6-M");
break;
case 0xf:
puts("ARMv7-M");
break;
default:
puts("unknown");
}
printf(" (0x%x)\n", cpuid_architecture);
const uint16_t cpuid_partno = (SCB_CPUID & SCB_CPUID_PARTNO) >> SCB_CPUID_PARTNO_LSB;
puts("- part number: ");
switch (cpuid_partno) {
case 0xC60:
puts("Cortex-M0+");
break;
case 0xC20:
puts("Cortex‑M0");
break;
case 0xC23: // the ARM spec actually mentions 0xC24
puts("Cortex‑M3");
break;
case 0xC24:
puts("Cortex‑M4");
break;
case 0xC27:
puts("Cortex‑M7");
break;
default:
puts("unknown");
}
printf(" (0x%03x)\n", cpuid_partno);
const uint8_t cpuid_variant = (SCB_CPUID & SCB_CPUID_VARIANT) >> SCB_CPUID_VARIANT_LSB;
printf("- variant: %u\n", cpuid_variant);
const uint8_t cpuid_revision = (SCB_CPUID & SCB_CPUID_REVISION) >> SCB_CPUID_REVISION_LSB;
printf("- revision: %u\n", cpuid_revision);
// ARM CoreSight B2.2.2
const uint8_t jep106_continuation = *(uint32_t*)0xE00FFFD0 & 0x0f; // DES_2, PIDR4 bits[3:0]
const uint8_t jep106_identification = ((*(uint32_t*)0xE00FFFE8 & 0x7) << 4) + ((*(uint32_t*)0xE00FFFE4 >> 4) & 0xf); // DES_0, PIDR1 bits[7:4] JEP106 identification code bits[3:0], DES_1, PIDR2 bits[2:0] JEP106 identification code bits[6:4]
const uint16_t pidr_partno = ((*(uint32_t*)0xE00FFFE4 & 0xf) << 8) + (*(uint32_t*)0xE00FFFE0 & 0xff); // PART_0, PIDR0 bits[7:0] Part number bits[7:0], PART_1, PIDR1 bits[3:0] Part number bits[11:8]
puts("JEP106 ID: ");
if (0 == jep106_continuation && 0x20 == jep106_identification) {
puts("STM");
} else if (7 == jep106_continuation && 0x51 == jep106_identification) {
puts("GigaDevice");
} else if (4 == jep106_continuation && 0x3b == jep106_identification) {
puts("ARM");
} else {
puts("unknown");
}
printf(" (cont.=%u, ID=0x%02x), part=0x%03x\n", jep106_continuation, jep106_identification, pidr_partno);
// guess the micro-controller
puts("MCU: ");
if (1 == cpuid_variant && 1 == cpuid_revision && 0 == jep106_continuation && 0x20 == jep106_identification) { // STM32 uses Cortex-M3 r1p1 and the right JEP106 ID
puts("STM32");
} else if (2 == cpuid_variant && 1 == cpuid_revision && 7 == jep106_continuation && 0x51 == jep106_identification) { // GD32 uses Cortex-M3 r2p1 and the right JEP106 ID
puts("GD32");
} else if (2 == cpuid_variant && 1 == cpuid_revision && 4 == jep106_continuation && 0x3b == jep106_identification) { // GD32 uses Cortex-M3 r2p1 and ARM JEP106 ID
puts("CS32");
} else {
puts("unknown");
}
putc('\n');
}
static void command_uptime(void* argument)