1-wire: add option to use interrupt redirection
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62cc65d954
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@ -12,8 +12,8 @@
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*
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*/
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/** library for 1-wire protocol as master (code)
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* @file onewire_master.c
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/** library for 1-wire protocol as master
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* @file
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* @author King Kévin <kingkevin@cuvoodoo.info>
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* @date 2017-2018
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* @note peripherals used: timer @ref onewire_master_timer, GPIO @ref onewire_master_gpio
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@ -35,14 +35,20 @@
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/* own libraries */
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#include "global.h" // help macros
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#include "interrupt.h" // runtime interrupt table
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#include "onewire_master.h" // own definitions
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/** @defgroup onewire_master_timer timer used to measure 1-wire signal timing
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* @{
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*/
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#define ONEWIRE_MASTER_TIMER 2 /**< timer ID */
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#define ONEWIRE_MASTER_TIMER 5 /**< timer ID */
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/** @} */
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/** set if the timer ISR should be set in the interrupt table instead of the vector table
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* @note the vector table is faster, but doesn't allow to change the ISR
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*/
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#define ONEWIRE_MASTER_TIMER_USE_INTERRUPT_TABLE false
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/** state of 1-Wire communication */
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volatile enum {
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ONEWIRE_STATE_IDLE, /**< no current communication */
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@ -59,6 +65,106 @@ static volatile bool slave_presence = false; /**< if slaves have been detected *
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static uint8_t* buffer = NULL; /**< input/output buffer for read/write commands/functions */
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static uint32_t buffer_size = 0; /**< size of buffer in bits */
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static volatile uint32_t buffer_bit = 0; /**< number of bits read/written */
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#if defined(ONEWIRE_MASTER_TIMER_USE_INTERRUPT_TABLE) && ONEWIRE_MASTER_TIMER_USE_INTERRUPT_TABLE
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static void (*isr_backup)(void) = NULL; /**< backup for the existing timer ISR */
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static bool irq_backup = false; /**< backup for the existing timer IRQ */
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#endif
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/** interrupt service routine called for timer */
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#if defined(ONEWIRE_MASTER_TIMER_USE_INTERRUPT_TABLE) && ONEWIRE_MASTER_TIMER_USE_INTERRUPT_TABLE
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static void onewire_master_timer_isr(void)
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#else
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void TIM_ISR(ONEWIRE_MASTER_TIMER)(void)
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#endif
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{
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if (timer_get_flag(TIM(ONEWIRE_MASTER_TIMER), TIM_SR_UIF)) { // overflow update event happened
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timer_clear_flag(TIM(ONEWIRE_MASTER_TIMER), TIM_SR_UIF); // clear flag
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switch (onewire_master_state) {
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case ONEWIRE_STATE_MASTER_RESET: // reset pulse has been started
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timer_clear_flag(TIM(ONEWIRE_MASTER_TIMER), TIM_SR_CC4IF); // clear output compare flag
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timer_enable_irq(TIM(ONEWIRE_MASTER_TIMER), TIM_DIER_CC4IE); // enable compare interrupt for presence detection
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gpio_set(GPIO(ONEWIRE_MASTER_PORT),GPIO(ONEWIRE_MASTER_PIN)); // set signal high again for slaves to respond
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onewire_master_state = ONEWIRE_STATE_SLAVE_PRESENCE; // set new state
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break;
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case ONEWIRE_STATE_SLAVE_PRESENCE: // waiting for slave presence but none received
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timer_disable_counter(TIM(ONEWIRE_MASTER_TIMER)); // disable timer
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timer_disable_irq(TIM(ONEWIRE_MASTER_TIMER), TIM_DIER_CC4IE); // disable compare interrupt for presence detection
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onewire_master_state = ONEWIRE_STATE_DONE; // go to next state
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break;
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case ONEWIRE_STATE_MASTER_READ: // end of time slot and recovery time for reading bit
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case ONEWIRE_STATE_MASTER_WRITE: // end of time slot and recovery time for writing bit
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if (buffer_bit<buffer_size) { // check if byte to read/write are remaining
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gpio_clear(GPIO(ONEWIRE_MASTER_PORT),GPIO(ONEWIRE_MASTER_PIN)); // pull signal low to start next slot
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} else { // all bytes read/written
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timer_disable_counter(TIM(ONEWIRE_MASTER_TIMER)); // disable timer
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timer_disable_irq(TIM(ONEWIRE_MASTER_TIMER), TIM_DIER_CC1IE); // disable compare interrupt for master pull low
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timer_disable_irq(TIM(ONEWIRE_MASTER_TIMER), TIM_DIER_CC2IE); // disable compare interrupt for read/write bit
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timer_disable_irq(TIM(ONEWIRE_MASTER_TIMER), TIM_DIER_CC3IE); // disable compare interrupt for end of slot
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onewire_master_state = ONEWIRE_STATE_DONE; // set end state
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}
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break;
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default: // unknown state for this stage
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timer_disable_counter(TIM(ONEWIRE_MASTER_TIMER)); // disable timer
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timer_disable_irq(TIM(ONEWIRE_MASTER_TIMER), TIM_DIER_CC1IE); // disable all compare interrupt
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timer_disable_irq(TIM(ONEWIRE_MASTER_TIMER), TIM_DIER_CC2IE); // disable all compare interrupt
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timer_disable_irq(TIM(ONEWIRE_MASTER_TIMER), TIM_DIER_CC3IE); // disable all compare interrupt
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timer_disable_irq(TIM(ONEWIRE_MASTER_TIMER), TIM_DIER_CC4IE); // disable all compare interrupt
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gpio_set(GPIO(ONEWIRE_MASTER_PORT),GPIO(ONEWIRE_MASTER_PIN)); // pull signal high (idle state)
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onewire_master_state = ONEWIRE_STATE_ERROR; // indicate error
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}
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} else if (timer_get_flag(TIM(ONEWIRE_MASTER_TIMER), TIM_SR_CC1IF)) { // compare event happened for master pull low end for read
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timer_clear_flag(TIM(ONEWIRE_MASTER_TIMER), TIM_SR_CC1IF); // clear flag
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switch (onewire_master_state) {
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case ONEWIRE_STATE_MASTER_READ: // master has to read a bit
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gpio_set(GPIO(ONEWIRE_MASTER_PORT),GPIO(ONEWIRE_MASTER_PIN)); // pull signal high to end time slot
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break;
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default: // unknown state for this stage
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break; // let the overflow handle the error if any
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}
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} else if (timer_get_flag(TIM(ONEWIRE_MASTER_TIMER), TIM_SR_CC2IF)) { // compare event happened for bit sampling/setting
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timer_clear_flag(TIM(ONEWIRE_MASTER_TIMER), TIM_SR_CC2IF); // clear flag
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switch (onewire_master_state) {
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case ONEWIRE_STATE_MASTER_WRITE: // master has to write a bit
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if (buffer_bit<buffer_size) { // check if byte to send are remaining
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if (buffer[buffer_bit/8]&(1<<(buffer_bit%8))) { // check bit (LSb first)
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gpio_set(GPIO(ONEWIRE_MASTER_PORT),GPIO(ONEWIRE_MASTER_PIN)); // set signal high again to write "1"
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}
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buffer_bit++; // got to next bit
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} else {
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timer_disable_irq(TIM(ONEWIRE_MASTER_TIMER), TIM_DIER_CC2IE); // disable compare interrupt
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onewire_master_state = ONEWIRE_STATE_ERROR; // indicate error
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}
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break;
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case ONEWIRE_STATE_MASTER_READ: // master has to read a bit set by slave
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if (buffer_bit<buffer_size) { // check if byte to send are remaining
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if (gpio_get(GPIO(ONEWIRE_MASTER_PORT),GPIO(ONEWIRE_MASTER_PIN))) { // check if the slave kept it low
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buffer[buffer_bit/8] |= (1<<(buffer_bit%8)); // save bit "1"
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} else {
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buffer[buffer_bit/8] &= ~(1<<(buffer_bit%8)); // save bit "0"
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}
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buffer_bit++; // got to next bit
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} else {
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timer_disable_irq(TIM(ONEWIRE_MASTER_TIMER), TIM_DIER_CC2IE); // disable compare interrupt
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onewire_master_state = ONEWIRE_STATE_ERROR; // indicate error
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}
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break;
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default: // unknown state for this stage
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break; // let the overflow handle the error if any
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}
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} else if (timer_get_flag(TIM(ONEWIRE_MASTER_TIMER), TIM_SR_CC3IF)) { // compare event happened for end to time slot
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timer_clear_flag(TIM(ONEWIRE_MASTER_TIMER), TIM_SR_CC3IF); // clear flag
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gpio_set(GPIO(ONEWIRE_MASTER_PORT),GPIO(ONEWIRE_MASTER_PIN)); // pull signal high to end time slot
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} else if (timer_get_flag(TIM(ONEWIRE_MASTER_TIMER), TIM_SR_CC4IF)) { // compare event happened for slave presence detection
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timer_clear_flag(TIM(ONEWIRE_MASTER_TIMER), TIM_SR_CC4IF); // clear flag
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if (gpio_get(GPIO(ONEWIRE_MASTER_PORT),GPIO(ONEWIRE_MASTER_PIN))) { // check is a slave let its presence know by pulling low
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slave_presence = false; // remember no slave(s) responded
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} else {
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slave_presence = true; // remember slave(s) responded
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}
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} else { // no other interrupt should occur
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while (true); // unhandled exception: wait for the watchdog to bite
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}
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}
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void onewire_master_setup(void)
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{
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@ -86,6 +192,11 @@ void onewire_master_setup(void)
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timer_clear_flag(TIM(ONEWIRE_MASTER_TIMER), TIM_SR_UIF); // clear update (overflow) flag
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timer_update_on_overflow(TIM(ONEWIRE_MASTER_TIMER)); // only use counter overflow as UEV source (use overflow as start time or timeout)
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timer_enable_irq(TIM(ONEWIRE_MASTER_TIMER), TIM_DIER_UIE); // enable update interrupt for overflow
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#if defined(ONEWIRE_MASTER_TIMER_USE_INTERRUPT_TABLE) && ONEWIRE_MASTER_TIMER_USE_INTERRUPT_TABLE
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isr_backup = interrupt_table[NVIC_TIM_IRQ(ONEWIRE_MASTER_TIMER)]; // backup timer ISR
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interrupt_table[NVIC_TIM_IRQ(ONEWIRE_MASTER_TIMER)] = &onewire_master_timer_isr; // set the 1-wire timer ISR
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irq_backup = nvic_get_irq_enabled(NVIC_TIM_IRQ(ONEWIRE_MASTER_TIMER)); // backup timer IRQ setting
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#endif
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nvic_enable_irq(NVIC_TIM_IRQ(ONEWIRE_MASTER_TIMER)); // catch interrupt in service routine
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slave_presence = false; // reset state
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@ -101,6 +212,16 @@ void onewire_master_release(void)
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// release GPIO
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gpio_set_mode(GPIO(ONEWIRE_MASTER_PORT), GPIO_MODE_INPUT, GPIO_CNF_INPUT_FLOAT, GPIO(ONEWIRE_MASTER_PIN)); // put back to input floating
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// disable timer ISR
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#if defined(ONEWIRE_MASTER_TIMER_USE_INTERRUPT_TABLE) && ONEWIRE_MASTER_TIMER_USE_INTERRUPT_TABLE
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if (!irq_backup) { // don't disable the IRQ if there was already enabled
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nvic_disable_irq(NVIC_TIM_IRQ(ONEWIRE_MASTER_TIMER)); // stop timer IRQ
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}
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interrupt_table[NVIC_TIM_IRQ(ONEWIRE_MASTER_TIMER)] = isr_backup; // set back original timer ISR
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#else
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nvic_disable_irq(NVIC_TIM_IRQ(ONEWIRE_MASTER_TIMER)); // stop timer IRQ
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#endif
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}
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bool onewire_master_reset(void)
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@ -390,94 +511,3 @@ bool onewire_master_rom_match(uint64_t code)
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return true;
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}
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/** interrupt service routine called for timer */
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void TIM_ISR(ONEWIRE_MASTER_TIMER)(void)
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{
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if (timer_get_flag(TIM(ONEWIRE_MASTER_TIMER), TIM_SR_UIF)) { // overflow update event happened
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timer_clear_flag(TIM(ONEWIRE_MASTER_TIMER), TIM_SR_UIF); // clear flag
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switch (onewire_master_state) {
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case ONEWIRE_STATE_MASTER_RESET: // reset pulse has been started
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timer_clear_flag(TIM(ONEWIRE_MASTER_TIMER), TIM_SR_CC4IF); // clear output compare flag
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timer_enable_irq(TIM(ONEWIRE_MASTER_TIMER), TIM_DIER_CC4IE); // enable compare interrupt for presence detection
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gpio_set(GPIO(ONEWIRE_MASTER_PORT),GPIO(ONEWIRE_MASTER_PIN)); // set signal high again for slaves to respond
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onewire_master_state = ONEWIRE_STATE_SLAVE_PRESENCE; // set new state
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break;
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case ONEWIRE_STATE_SLAVE_PRESENCE: // waiting for slave presence but none received
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timer_disable_counter(TIM(ONEWIRE_MASTER_TIMER)); // disable timer
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timer_disable_irq(TIM(ONEWIRE_MASTER_TIMER), TIM_DIER_CC4IE); // disable compare interrupt for presence detection
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onewire_master_state = ONEWIRE_STATE_DONE; // go to next state
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break;
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case ONEWIRE_STATE_MASTER_READ: // end of time slot and recovery time for reading bit
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case ONEWIRE_STATE_MASTER_WRITE: // end of time slot and recovery time for writing bit
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if (buffer_bit<buffer_size) { // check if byte to read/write are remaining
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gpio_clear(GPIO(ONEWIRE_MASTER_PORT),GPIO(ONEWIRE_MASTER_PIN)); // pull signal low to start next slot
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} else { // all bytes read/written
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timer_disable_counter(TIM(ONEWIRE_MASTER_TIMER)); // disable timer
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timer_disable_irq(TIM(ONEWIRE_MASTER_TIMER), TIM_DIER_CC1IE); // disable compare interrupt for master pull low
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timer_disable_irq(TIM(ONEWIRE_MASTER_TIMER), TIM_DIER_CC2IE); // disable compare interrupt for read/write bit
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timer_disable_irq(TIM(ONEWIRE_MASTER_TIMER), TIM_DIER_CC3IE); // disable compare interrupt for end of slot
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onewire_master_state = ONEWIRE_STATE_DONE; // set end state
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}
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break;
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default: // unknown state for this stage
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timer_disable_counter(TIM(ONEWIRE_MASTER_TIMER)); // disable timer
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timer_disable_irq(TIM(ONEWIRE_MASTER_TIMER), TIM_DIER_CC1IE); // disable all compare interrupt
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timer_disable_irq(TIM(ONEWIRE_MASTER_TIMER), TIM_DIER_CC2IE); // disable all compare interrupt
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timer_disable_irq(TIM(ONEWIRE_MASTER_TIMER), TIM_DIER_CC3IE); // disable all compare interrupt
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timer_disable_irq(TIM(ONEWIRE_MASTER_TIMER), TIM_DIER_CC4IE); // disable all compare interrupt
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gpio_set(GPIO(ONEWIRE_MASTER_PORT),GPIO(ONEWIRE_MASTER_PIN)); // pull signal high (idle state)
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onewire_master_state = ONEWIRE_STATE_ERROR; // indicate error
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}
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} else if (timer_get_flag(TIM(ONEWIRE_MASTER_TIMER), TIM_SR_CC1IF)) { // compare event happened for master pull low end for read
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timer_clear_flag(TIM(ONEWIRE_MASTER_TIMER), TIM_SR_CC1IF); // clear flag
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switch (onewire_master_state) {
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case ONEWIRE_STATE_MASTER_READ: // master has to read a bit
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gpio_set(GPIO(ONEWIRE_MASTER_PORT),GPIO(ONEWIRE_MASTER_PIN)); // pull signal high to end time slot
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break;
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default: // unknown state for this stage
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break; // let the overflow handle the error if any
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}
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} else if (timer_get_flag(TIM(ONEWIRE_MASTER_TIMER), TIM_SR_CC2IF)) { // compare event happened for bit sampling/setting
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timer_clear_flag(TIM(ONEWIRE_MASTER_TIMER), TIM_SR_CC2IF); // clear flag
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switch (onewire_master_state) {
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case ONEWIRE_STATE_MASTER_WRITE: // master has to write a bit
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if (buffer_bit<buffer_size) { // check if byte to send are remaining
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if (buffer[buffer_bit/8]&(1<<(buffer_bit%8))) { // check bit (LSb first)
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gpio_set(GPIO(ONEWIRE_MASTER_PORT),GPIO(ONEWIRE_MASTER_PIN)); // set signal high again to write "1"
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}
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buffer_bit++; // got to next bit
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} else {
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timer_disable_irq(TIM(ONEWIRE_MASTER_TIMER), TIM_DIER_CC2IE); // disable compare interrupt
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onewire_master_state = ONEWIRE_STATE_ERROR; // indicate error
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}
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break;
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case ONEWIRE_STATE_MASTER_READ: // master has to read a bit set by slave
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if (buffer_bit<buffer_size) { // check if byte to send are remaining
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if (gpio_get(GPIO(ONEWIRE_MASTER_PORT),GPIO(ONEWIRE_MASTER_PIN))) { // check if the slave kept it low
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buffer[buffer_bit/8] |= (1<<(buffer_bit%8)); // save bit "1"
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} else {
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buffer[buffer_bit/8] &= ~(1<<(buffer_bit%8)); // save bit "0"
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}
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buffer_bit++; // got to next bit
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} else {
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timer_disable_irq(TIM(ONEWIRE_MASTER_TIMER), TIM_DIER_CC2IE); // disable compare interrupt
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onewire_master_state = ONEWIRE_STATE_ERROR; // indicate error
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}
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break;
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default: // unknown state for this stage
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break; // let the overflow handle the error if any
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}
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} else if (timer_get_flag(TIM(ONEWIRE_MASTER_TIMER), TIM_SR_CC3IF)) { // compare event happened for end to time slot
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timer_clear_flag(TIM(ONEWIRE_MASTER_TIMER), TIM_SR_CC3IF); // clear flag
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gpio_set(GPIO(ONEWIRE_MASTER_PORT),GPIO(ONEWIRE_MASTER_PIN)); // pull signal high to end time slot
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} else if (timer_get_flag(TIM(ONEWIRE_MASTER_TIMER), TIM_SR_CC4IF)) { // compare event happened for slave presence detection
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timer_clear_flag(TIM(ONEWIRE_MASTER_TIMER), TIM_SR_CC4IF); // clear flag
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if (gpio_get(GPIO(ONEWIRE_MASTER_PORT),GPIO(ONEWIRE_MASTER_PIN))) { // check is a slave let its presence know by pulling low
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slave_presence = false; // remember no slave(s) responded
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} else {
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slave_presence = true; // remember slave(s) responded
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}
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} else { // no other interrupt should occur
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while (true); // unhandled exception: wait for the watchdog to bite
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}
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}
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@ -12,8 +12,8 @@
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*
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*/
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/** library for 1-wire protocol as master (API)
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* @file onewire_master.h
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/** library for 1-wire protocol as master
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* @file
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* @author King Kévin <kingkevin@cuvoodoo.info>
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* @date 2017-2018
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* @note peripherals used: timer @ref onewire_master_timer, GPIO @ref onewire_master_gpio
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