I2C: add return codes
This commit is contained in:
parent
708e3d195b
commit
2fec5cf247
168
lib/i2c_master.c
168
lib/i2c_master.c
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@ -262,7 +262,7 @@ void i2c_master_reset(uint32_t i2c)
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i2c_peripheral_enable(i2c); // re-enable device
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}
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bool i2c_master_start(uint32_t i2c)
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enum i2c_master_rc i2c_master_start(uint32_t i2c)
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{
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// check I2C peripheral
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if (I2C1!=i2c && I2C2!=i2c) {
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@ -271,33 +271,35 @@ bool i2c_master_start(uint32_t i2c)
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// send (re-)start condition
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if (I2C_CR1(i2c) & (I2C_CR1_START|I2C_CR1_STOP)) { // ensure start or stop operations are not in progress
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return false;
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return I2C_MASTER_RC_START_STOP_IN_PROGESS;
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}
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i2c_send_start(i2c); // send start condition to start transaction
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while (I2C_CR1(i2c) & I2C_CR1_START); // wait until start condition has been accepted and cleared
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while ((I2C_CR1(i2c) & I2C_CR1_START)); // wait until start condition is accepted and cleared
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while (!(I2C_SR1(i2c) & I2C_SR1_SB)); // wait until start condition is transmitted
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if (!(I2C_SR2(i2c) & I2C_SR2_MSL)) { // verify if in master mode
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return false;
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return I2C_MASTER_RC_NOT_MASTER;
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}
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return true;
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return I2C_MASTER_RC_NONE;
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}
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bool i2c_master_select_slave(uint32_t i2c, uint16_t slave, bool address_10bit, bool write)
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enum i2c_master_rc i2c_master_select_slave(uint32_t i2c, uint16_t slave, bool address_10bit, bool write)
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{
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// check I2C peripheral
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if (I2C1!=i2c && I2C2!=i2c) {
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while (true);
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}
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enum i2c_master_rc rc = I2C_MASTER_RC_NONE; // to store I2C return codes
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if (!(I2C_SR1(i2c) & I2C_SR1_SB)) { // start condition has not been sent
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if (!i2c_master_start(i2c)) { // send start condition
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return false;
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rc = i2c_master_start(i2c); // send start condition
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if (I2C_MASTER_RC_NONE!=rc) {
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return rc;
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}
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}
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if (!(I2C_SR2(i2c) & I2C_SR2_MSL)) { // I2C device is not in master mode
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return false;
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return I2C_MASTER_RC_NOT_MASTER;
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}
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// select slave
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@ -306,7 +308,7 @@ bool i2c_master_select_slave(uint32_t i2c, uint16_t slave, bool address_10bit, b
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i2c_send_7bit_address(i2c, slave, write ? I2C_WRITE : I2C_READ); // select slave, with read/write flag
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while (!(I2C_SR1(i2c) & (I2C_SR1_ADDR|I2C_SR1_AF))); // wait until address is transmitted
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if (I2C_SR1(i2c) & I2C_SR1_AF) { // address has not been acknowledged
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return false;
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return I2C_MASTER_RC_NAK;
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}
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} else { // 10-bit address
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// send first part of address
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@ -314,43 +316,44 @@ bool i2c_master_select_slave(uint32_t i2c, uint16_t slave, bool address_10bit, b
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I2C_DR(i2c) = 11110000 | (((slave>>8)&0x3)<<1); // send first header (11110xx0, where xx are 2 MSb of slave address)
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while (!(I2C_SR1(i2c) & (I2C_SR1_ADD10|I2C_SR1_AF))); // wait until first part of address is transmitted
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if (I2C_SR1(i2c) & I2C_SR1_AF) { // address has not been acknowledged
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return false;
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return I2C_MASTER_RC_NAK;
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}
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// send second part of address
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I2C_SR1(i2c) &= ~(I2C_SR1_AF); // clear acknowledgement failure
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I2C_DR(i2c) = (slave&0xff); // send remaining of address
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while (!(I2C_SR1(i2c) & (I2C_SR1_ADDR|I2C_SR1_AF))); // wait until remaining part of address is transmitted
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if (I2C_SR1(i2c) & I2C_SR1_AF) { // address has not been acknowledged
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return false;
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return I2C_MASTER_RC_NAK;
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}
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// go into receive mode if necessary
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if (!write) {
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if (!i2c_master_start(i2c)) { // send re-start condition
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return false; // could not send start condition
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rc = i2c_master_start(i2c); // send start condition
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if (I2C_MASTER_RC_NONE!=rc) {
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return rc;
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}
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// send first part of address with receive flag
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I2C_SR1(i2c) &= ~(I2C_SR1_AF); // clear acknowledgement failure
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I2C_DR(i2c) = 11110001 | (((slave>>8)&0x3)<<1); // send header (11110xx1, where xx are 2 MSb of slave address)
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while (!(I2C_SR1(i2c) & (I2C_SR1_ADDR|I2C_SR1_AF))); // wait until remaining part of address is transmitted
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if (I2C_SR1(i2c) & I2C_SR1_AF) { // address has not been acknowledged
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return false;
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return I2C_MASTER_RC_NAK;
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}
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}
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}
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if (write) {
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if (!((I2C_SR2(i2c) & I2C_SR2_TRA))) { // verify we are in transmit mode (and read SR2 to clear ADDR)
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return false;
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return I2C_MASTER_RC_NOT_TRANSMIT;
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}
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} else {
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if ((I2C_SR2(i2c) & I2C_SR2_TRA)) { // verify we are in read mode (and read SR2 to clear ADDR)
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return false;
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return I2C_MASTER_RC_NOT_RECEIVE;
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}
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}
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return true;
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return I2C_MASTER_RC_NONE;
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}
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bool i2c_master_read(uint32_t i2c, uint8_t* data, size_t data_size)
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enum i2c_master_rc i2c_master_read(uint32_t i2c, uint8_t* data, size_t data_size)
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{
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// check I2C peripheral
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if (I2C1!=i2c && I2C2!=i2c) {
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@ -359,13 +362,16 @@ bool i2c_master_read(uint32_t i2c, uint8_t* data, size_t data_size)
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// sanity check
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if (data==NULL || data_size==0) { // no data to read
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return true;
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return I2C_MASTER_RC_NONE;
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}
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if (!(I2C_SR2(i2c) & I2C_SR2_MSL)) { // I2C device is not master
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return false;
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return I2C_MASTER_RC_NOT_MASTER;
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}
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if ((I2C_SR2(i2c) & I2C_SR2_TRA)) { // I2C device not in receiver mode
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return false;
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return I2C_MASTER_RC_NOT_RECEIVE;
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}
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if (I2C_SR1(i2c) & I2C_SR1_AF) { // check if the previous transaction went well
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return I2C_MASTER_RC_NOT_READY;
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}
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// read data
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@ -379,10 +385,10 @@ bool i2c_master_read(uint32_t i2c, uint8_t* data, size_t data_size)
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data[i] = i2c_get_data(i2c); // read received byte
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}
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return true;
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return I2C_MASTER_RC_NONE;
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}
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bool i2c_master_write(uint32_t i2c, const uint8_t* data, size_t data_size)
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enum i2c_master_rc i2c_master_write(uint32_t i2c, const uint8_t* data, size_t data_size)
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{
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// check I2C peripheral
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if (I2C1!=i2c && I2C2!=i2c) {
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@ -391,13 +397,16 @@ bool i2c_master_write(uint32_t i2c, const uint8_t* data, size_t data_size)
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// sanity check
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if (data==NULL || data_size==0) { // no data to write
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return true;
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return I2C_MASTER_RC_NONE;
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}
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if (!(I2C_SR2(i2c) & I2C_SR2_MSL)) { // I2C device is not master
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return false;
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return I2C_MASTER_RC_NOT_MASTER;
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}
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if (!(I2C_SR2(i2c) & I2C_SR2_TRA)) { // I2C device not in transmitter mode
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return false;
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return I2C_MASTER_RC_NOT_TRANSMIT;
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}
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if (I2C_SR1(i2c) & I2C_SR1_AF) { // check if the previous transaction went well
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return I2C_MASTER_RC_NOT_READY;
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}
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// write data
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@ -406,14 +415,14 @@ bool i2c_master_write(uint32_t i2c, const uint8_t* data, size_t data_size)
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i2c_send_data(i2c, data[i]); // send byte to be written in memory
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while (!(I2C_SR1(i2c) & (I2C_SR1_TxE|I2C_SR1_AF))); // wait until byte has been transmitted
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if (I2C_SR1(i2c) & I2C_SR1_AF) { // data has not been acknowledged
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return false;
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return I2C_MASTER_RC_NAK;
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}
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}
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return true;
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return I2C_MASTER_RC_NONE;
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}
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bool i2c_master_stop(uint32_t i2c)
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enum i2c_master_rc i2c_master_stop(uint32_t i2c)
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{
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// check I2C peripheral
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if (I2C1!=i2c && I2C2!=i2c) {
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@ -422,141 +431,158 @@ bool i2c_master_stop(uint32_t i2c)
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// sanity check
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if (!(I2C_SR2(i2c) & I2C_SR2_BUSY)) { // release is not busy
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return true; // bus has probably already been released
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return I2C_MASTER_RC_NONE; // bus has probably already been released
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}
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// send stop condition
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if (I2C_CR1(i2c) & (I2C_CR1_START|I2C_CR1_STOP)) { // ensure start or stop operations are not in progress
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return false;
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return I2C_MASTER_RC_START_STOP_IN_PROGESS;
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}
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i2c_send_stop(i2c); // send stop to release bus
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while ((I2C_CR1(i2c) & I2C_CR1_STOP)); // wait until stop condition is accepted and cleared
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while ((I2C_SR2(i2c) & I2C_SR2_MSL)); // wait until bus released (non master mode)
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return true;
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return I2C_MASTER_RC_NONE;
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}
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bool i2c_master_slave_read(uint32_t i2c, uint16_t slave, bool address_10bit, uint8_t* data, size_t data_size)
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enum i2c_master_rc i2c_master_slave_read(uint32_t i2c, uint16_t slave, bool address_10bit, uint8_t* data, size_t data_size)
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{
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// check I2C peripheral
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if (I2C1!=i2c && I2C2!=i2c) {
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while (true);
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}
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bool success = false; // return if read succeeded
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if (!i2c_master_start(i2c)) { // send (re-)start condition
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return false;
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enum i2c_master_rc rc = I2C_MASTER_RC_NONE; // to store I2C return codes
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rc = i2c_master_start(i2c); // send (re-)start condition
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if (I2C_MASTER_RC_NONE!=rc) {
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return rc;
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}
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if (!i2c_master_select_slave(i2c, slave, address_10bit, false)) { // select slave to read
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rc = i2c_master_select_slave(i2c, slave, address_10bit, false); // select slave to read
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if (I2C_MASTER_RC_NONE!=rc) {
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goto error;
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}
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if (NULL!=data && data_size>0) { // only read data if needed
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if (!i2c_master_read(i2c, data, data_size)) { // read data
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rc = i2c_master_read(i2c, data, data_size);
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if (I2C_MASTER_RC_NONE!=rc) {
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goto error;
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}
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}
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success = true; // all went well
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rc = I2C_MASTER_RC_NONE; // all went well
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error:
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i2c_master_stop(i2c); // sent stop condition
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return success;
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return rc;
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}
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bool i2c_master_slave_write(uint32_t i2c, uint16_t slave, bool address_10bit, const uint8_t* data, size_t data_size)
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enum i2c_master_rc i2c_master_slave_write(uint32_t i2c, uint16_t slave, bool address_10bit, const uint8_t* data, size_t data_size)
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{
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// check I2C peripheral
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if (I2C1!=i2c && I2C2!=i2c) {
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while (true);
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}
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bool success = false; // return if write succeeded
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if (!i2c_master_start(i2c)) { // send (re-)start condition
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return false;
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enum i2c_master_rc rc = I2C_MASTER_RC_NONE; // to store I2C return codes
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rc = i2c_master_start(i2c); // send (re-)start condition
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if (I2C_MASTER_RC_NONE!=rc) {
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return rc;
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}
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if (!i2c_master_select_slave(i2c, slave, address_10bit, true)) { // select slave to write
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rc = i2c_master_select_slave(i2c, slave, address_10bit, true); // select slave to write
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if (I2C_MASTER_RC_NONE!=rc) {
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goto error;
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}
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if (NULL!=data && data_size>0) { // write data only is some is available
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if (!i2c_master_write(i2c, data, data_size)) { // write data
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rc = i2c_master_write(i2c, data, data_size); // write data
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if (I2C_MASTER_RC_NONE!=rc) {
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goto error;
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}
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}
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success = true; // all went well
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rc = I2C_MASTER_RC_NONE; // all went well
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error:
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i2c_master_stop(i2c); // sent stop condition
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return success;
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return rc;
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}
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bool i2c_master_address_read(uint32_t i2c, uint16_t slave, bool address_10bit, const uint8_t* address, size_t address_size, uint8_t* data, size_t data_size)
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enum i2c_master_rc i2c_master_address_read(uint32_t i2c, uint16_t slave, bool address_10bit, const uint8_t* address, size_t address_size, uint8_t* data, size_t data_size)
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{
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// check I2C peripheral
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if (I2C1!=i2c && I2C2!=i2c) {
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while (true);
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}
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bool success = false; // return if read succeeded
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if (!i2c_master_start(i2c)) { // send (re-)start condition
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return false;
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enum i2c_master_rc rc = I2C_MASTER_RC_NONE; // to store I2C return codes
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rc = i2c_master_start(i2c); // send (re-)start condition
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if (I2C_MASTER_RC_NONE!=rc) {
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return rc;
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}
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if (!i2c_master_select_slave(i2c, slave, address_10bit, true)) { // select slave to write
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rc = i2c_master_select_slave(i2c, slave, address_10bit, true); // select slave to write
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if (I2C_MASTER_RC_NONE!=rc) {
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goto error;
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}
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// write address
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if (NULL!=address && address_size>0) {
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if (!i2c_master_write(i2c, address, address_size)) { // send memory address
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rc = i2c_master_write(i2c, address, address_size); // send memory address
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if (I2C_MASTER_RC_NONE!=rc) {
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goto error;
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}
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}
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// read data
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if (NULL!=data && data_size>0) {
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if (!i2c_master_start(i2c)) { // send (re-)start condition
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return false;
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rc = i2c_master_start(i2c); // send re-start condition
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if (I2C_MASTER_RC_NONE!=rc) {
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return rc;
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}
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if (!i2c_master_select_slave(i2c, slave, address_10bit, false)) { // select slave to read
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rc = i2c_master_select_slave(i2c, slave, address_10bit, false); // select slave to read
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if (I2C_MASTER_RC_NONE!=rc) {
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goto error;
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}
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if (!i2c_master_read(i2c, data, data_size)) { // read memory
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rc = i2c_master_read(i2c, data, data_size); // read memory
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if (I2C_MASTER_RC_NONE!=rc) {
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goto error;
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}
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}
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success = true;
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rc = I2C_MASTER_RC_NONE; // all went well
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error:
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i2c_master_stop(i2c); // sent stop condition
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return success;
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return rc;
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}
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bool i2c_master_address_write(uint32_t i2c, uint16_t slave, bool address_10bit, const uint8_t* address, size_t address_size, const uint8_t* data, size_t data_size)
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enum i2c_master_rc i2c_master_address_write(uint32_t i2c, uint16_t slave, bool address_10bit, const uint8_t* address, size_t address_size, const uint8_t* data, size_t data_size)
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{
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// check I2C peripheral
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if (I2C1!=i2c && I2C2!=i2c) {
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while (true);
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}
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bool success = false; // return if write succeeded
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if (!i2c_master_start(i2c)) { // send (re-)start condition
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return false;
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enum i2c_master_rc rc = I2C_MASTER_RC_NONE; // to store I2C return codes
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rc = i2c_master_start(i2c); // send (re-)start condition
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if (I2C_MASTER_RC_NONE!=rc) {
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return rc;
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}
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if (!i2c_master_select_slave(i2c, slave, address_10bit, true)) { // select slave to write
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rc = i2c_master_select_slave(i2c, slave, address_10bit, true); // select slave to write
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if (I2C_MASTER_RC_NONE!=rc) {
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goto error;
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}
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// write address
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if (NULL!=address && address_size>0) {
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if (!i2c_master_write(i2c, address, address_size)) { // send memory address to write
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rc = i2c_master_write(i2c, address, address_size); // send memory address
|
||||
if (I2C_MASTER_RC_NONE!=rc) {
|
||||
goto error;
|
||||
}
|
||||
}
|
||||
// read data
|
||||
if (NULL!=data && data_size>0) {
|
||||
if (!i2c_master_write(i2c, data, data_size)) { // write data
|
||||
rc = i2c_master_write(i2c, data, data_size); // write memory
|
||||
if (I2C_MASTER_RC_NONE!=rc) {
|
||||
goto error;
|
||||
}
|
||||
}
|
||||
|
||||
success = true;
|
||||
rc = I2C_MASTER_RC_NONE; // all went well
|
||||
error:
|
||||
i2c_master_stop(i2c); // sent stop condition
|
||||
return success;
|
||||
return rc;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -20,6 +20,17 @@
|
|||
*/
|
||||
#pragma once
|
||||
|
||||
/** I2C return codes */
|
||||
enum i2c_master_rc {
|
||||
I2C_MASTER_RC_NONE = 0, /**< no error */
|
||||
I2C_MASTER_RC_START_STOP_IN_PROGESS, /**< a start or stop condition is already in progress */
|
||||
I2C_MASTER_RC_NOT_MASTER, /**< not in master mode */
|
||||
I2C_MASTER_RC_NOT_TRANSMIT, /**< not in transmit mode */
|
||||
I2C_MASTER_RC_NOT_RECEIVE, /**< not in receive mode */
|
||||
I2C_MASTER_RC_NOT_READY, /**< slave is not read (previous operations has been nacked) */
|
||||
I2C_MASTER_RC_NAK, /**< not acknowledge received */
|
||||
};
|
||||
|
||||
/** setup I2C peripheral
|
||||
* @param[in] i2c I2C base address
|
||||
* @param[in] frequency frequency to use in kHz (1-400)
|
||||
|
|
@ -42,37 +53,39 @@ void i2c_master_reset(uint32_t i2c);
|
|||
bool i2c_master_check_signals(uint32_t i2c);
|
||||
/** send start condition
|
||||
* @param[in] i2c I2C base address
|
||||
* @return if start condition was sent successfully (true) or error occurred (false)
|
||||
* @return I2C return code
|
||||
*/
|
||||
bool i2c_master_start(uint32_t i2c);
|
||||
enum i2c_master_rc i2c_master_start(uint32_t i2c);
|
||||
/** select slave device
|
||||
* @warning a start condition should be sent before this operation
|
||||
* @param[in] i2c I2C base address
|
||||
* @param[in] slave I2C address of slave device to select
|
||||
* @param[in] address_10bit if the I2C slave address is 10 bits wide
|
||||
* @param[in] write this transaction will be followed by a read (false) or write (true) operation
|
||||
* @return if slave was selected successfully (true) or error occurred (false)
|
||||
* @return I2C return code
|
||||
*/
|
||||
bool i2c_master_select_slave(uint32_t i2c, uint16_t slave, bool address_10bit, bool write);
|
||||
enum i2c_master_rc i2c_master_select_slave(uint32_t i2c, uint16_t slave, bool address_10bit, bool write);
|
||||
/** read data
|
||||
* @warning the slave device must be selected before this operation
|
||||
* @param[in] address_10bit if the I2C slave address is 10 bits wide
|
||||
* @param[out] data array to store bytes read
|
||||
* @param[in] data_size number of bytes to read
|
||||
* @return I2C return code
|
||||
*/
|
||||
bool i2c_master_read(uint32_t i2c, uint8_t* data, size_t data_size);
|
||||
enum i2c_master_rc i2c_master_read(uint32_t i2c, uint8_t* data, size_t data_size);
|
||||
/** write data
|
||||
* @warning the slave device must be selected before this operation
|
||||
* @param[in] address_10bit if the I2C slave address is 10 bits wide
|
||||
* @param[in] data array of byte to write to slave
|
||||
* @param[in] data_size number of bytes to write
|
||||
* @return I2C return code
|
||||
*/
|
||||
bool i2c_master_write(uint32_t i2c, const uint8_t* data, size_t data_size);
|
||||
enum i2c_master_rc i2c_master_write(uint32_t i2c, const uint8_t* data, size_t data_size);
|
||||
/** sent stop condition
|
||||
* @param[in] i2c I2C base address
|
||||
* @return is stop condition has been sent successfully
|
||||
* @return I2C return code
|
||||
*/
|
||||
bool i2c_master_stop(uint32_t i2c);
|
||||
enum i2c_master_rc i2c_master_stop(uint32_t i2c);
|
||||
/** read data from slave device
|
||||
* @warning the slave device must be selected before this operation
|
||||
* @param[in] i2c I2C base address
|
||||
|
|
@ -80,8 +93,9 @@ bool i2c_master_stop(uint32_t i2c);
|
|||
* @param[in] address_10bit if the I2C slave address is 10 bits wide
|
||||
* @param[out] data array to store bytes read
|
||||
* @param[in] data_size number of bytes to read
|
||||
* @return I2C return code
|
||||
*/
|
||||
bool i2c_master_slave_read(uint32_t i2c, uint16_t slave, bool address_10bit, uint8_t* data, size_t data_size);
|
||||
enum i2c_master_rc i2c_master_slave_read(uint32_t i2c, uint16_t slave, bool address_10bit, uint8_t* data, size_t data_size);
|
||||
/** write data to slave device
|
||||
* @warning the slave device must be selected before this operation
|
||||
* @param[in] i2c I2C base address
|
||||
|
|
@ -89,16 +103,9 @@ bool i2c_master_slave_read(uint32_t i2c, uint16_t slave, bool address_10bit, uin
|
|||
* @param[in] address_10bit if the I2C slave address is 10 bits wide
|
||||
* @param[in] data array of byte to write to slave
|
||||
* @param[in] data_size number of bytes to write
|
||||
* @return I2C return code
|
||||
*/
|
||||
bool i2c_master_slave_write(uint32_t i2c, uint16_t slave, bool address_10bit, const uint8_t* data, size_t data_size);
|
||||
/** read from date from an I2C slave
|
||||
* @param[in] i2c I2C base address
|
||||
* @param[in] slave I2C address of slave device to select
|
||||
* @param[in] address_10bit if the I2C slave address is 10 bits wide
|
||||
* @param[out] data array to store bytes read
|
||||
* @param[in] data_size number of bytes to read
|
||||
* @return if read succeeded
|
||||
*/
|
||||
enum i2c_master_rc i2c_master_slave_write(uint32_t i2c, uint16_t slave, bool address_10bit, const uint8_t* data, size_t data_size);
|
||||
/** read data at specific address from an I2C memory slave
|
||||
* @param[in] i2c I2C base address
|
||||
* @param[in] slave I2C address of slave device to select
|
||||
|
|
@ -107,9 +114,9 @@ bool i2c_master_slave_write(uint32_t i2c, uint16_t slave, bool address_10bit, co
|
|||
* @param[in] address_size address size in bytes
|
||||
* @param[out] data array to store bytes read
|
||||
* @param[in] data_size number of bytes to read
|
||||
* @return if read succeeded
|
||||
* @return I2C return code
|
||||
*/
|
||||
bool i2c_master_address_read(uint32_t i2c, uint16_t slave, bool address_10bit, const uint8_t* address, size_t address_size, uint8_t* data, size_t data_size);
|
||||
enum i2c_master_rc i2c_master_address_read(uint32_t i2c, uint16_t slave, bool address_10bit, const uint8_t* address, size_t address_size, uint8_t* data, size_t data_size);
|
||||
/** write data at specific address on an I2C memory slave
|
||||
* @param[in] i2c I2C base address
|
||||
* @param[in] slave I2C address of slave device to select
|
||||
|
|
@ -118,6 +125,6 @@ bool i2c_master_address_read(uint32_t i2c, uint16_t slave, bool address_10bit, c
|
|||
* @param[in] address_size address size in bytes
|
||||
* @param[in] data array of byte to write to slave
|
||||
* @param[in] data_size number of bytes to write
|
||||
* @return if write succeeded
|
||||
* @return I2C return code
|
||||
*/
|
||||
bool i2c_master_address_write(uint32_t i2c, uint16_t slave, bool address_10bit, const uint8_t* address, size_t address_size, const uint8_t* data, size_t data_size);
|
||||
enum i2c_master_rc i2c_master_address_write(uint32_t i2c, uint16_t slave, bool address_10bit, const uint8_t* address, size_t address_size, const uint8_t* data, size_t data_size);
|
||||
|
|
|
|||
Loading…
Reference in New Issue