application: remove lengthy version description
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ac9eb9bac9
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284065b62f
218
application.c
218
application.c
@ -431,132 +431,10 @@ static void command_help(void* argument)
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static void command_version(void* argument)
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{
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(void)argument; // we won't use the argument
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bool fake = false; // if details indicate it's not an STM32
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printf("firmware date: %04u-%02u-%02u\n", BUILD_YEAR, BUILD_MONTH, BUILD_DAY); // show firmware build date
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puts("chip family: ");
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const uint16_t dev_id = DBGMCU_IDCODE & DBGMCU_IDCODE_DEV_ID_MASK;
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switch (dev_id) {
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case 0: // DBGMCU_IDCODE is only accessible in debug mode (this is a known issue documented in STM32F10xxC/D/E Errata sheet, without workaround)
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puts("not readable, retry with debug attached");
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break;
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// from RM0008 STM32F101xx, STM32F102xx, STM32F103xx, STM32F105xx and STM32F107xx
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case 0x412:
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puts("STM32F10x low-density");
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break;
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case 0x410:
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puts("STM32F10x medium-density");
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break;
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case 0x414:
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puts("STM32F10x high-density");
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break;
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case 0x430:
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puts("STM32F10x XL-density");
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break;
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case 0x418:
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puts("STM32F10xconnectivity");
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break;
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// from RM0091 STM32F0x8
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case 0x444:
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puts("STM32F03x");
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break;
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case 0x445:
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puts("STM32F04x");
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break;
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case 0x440:
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puts("STM32F05x");
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break;
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case 0x448:
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puts("STM32F07x");
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break;
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case 0x442:
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puts("STM32F09x");
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break;
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// from RM0444 STM32G0x1
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case 0x460:
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puts("STM32G071xx/STM32G081xx");
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break;
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case 0x466:
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puts("STM32G031xx/STM32G041xx");
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break;
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// from RM0090 STM32F4x5/STM32F4x7
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case 0x413:
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puts("STM32F405/STM32F407/STM32F415/STM32F417");
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break;
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case 0x419:
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puts("STM32F42x/STM32F43x");
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break;
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// from RM0368
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case 0x423:
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puts("STM32F401xB/C");
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break;
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case 0x433:
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puts("STM32F401xD/E");
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break;
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// from RM0383
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case 0x431:
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puts("STM32F411xC/E");
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break;
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default:
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puts("unknown");
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fake = true;
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break;
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}
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printf(" (DEV_ID=0x%03x)\n", dev_id);
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puts("chip revision: ");
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const uint16_t rev_id = DBGMCU_IDCODE >> 16;
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switch (DBGMCU_IDCODE & DBGMCU_IDCODE_DEV_ID_MASK) {
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case 0x412:
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if (0x1000 == rev_id) {
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putc('A');
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} else {
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puts("unknown");
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}
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break;
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case 0x410:
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if (0x0000 == rev_id) {
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putc('A');
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} else if (0x2000 == rev_id) {
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putc('B');
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} else if (0x2001 == rev_id) {
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putc('Z');
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} else if (0x2003 == rev_id) {
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puts("1/2/3/X/Y");
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} else {
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puts("unknown");
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}
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break;
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case 0x414:
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if (0x1000 == rev_id) {
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puts("A/1");
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} else if (0x1001 == rev_id) {
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putc('Z');
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} else if (0x1003 == rev_id) {
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puts("1/2/3/X/Y");
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} else {
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puts("unknown");
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}
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break;
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case 0x430:
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if (0x1003 == rev_id) {
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puts("A/1");
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} else {
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puts("unknown");
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}
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break;
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case 0x418:
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if (0x1000 == rev_id) {
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putc('A');
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} else if (0x1001 == rev_id) {
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putc('Z');
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} else {
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puts("unknown");
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}
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break;
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default:
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printf("unknown");
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break;
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}
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printf(" (REV_ID=0x%04x)\n", rev_id);
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printf("chip: ID=0x%03x, rev=0x%04x\n", dev_id, rev_id);
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// show flash size
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puts("flash size: ");
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if (0xffff == DESIG_FLASH_SIZE) {
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@ -566,100 +444,6 @@ static void command_version(void* argument)
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}
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// display device identity
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printf("device id: %08x%08x%04x%04x\n", DESIG_UNIQUE_ID2, DESIG_UNIQUE_ID1, DESIG_UNIQUE_ID0 & 0xffff, DESIG_UNIQUE_ID0 >> 16);
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// from RM0091 STM32F0x8 reference manual (not sure if it applies to F1)
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printf("- X,Y wafer coordinate: %08x\n", DESIG_UNIQUE_ID0);
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printf("- lot number: %c%c%c%c%c%c%c\n", DESIG_UNIQUE_ID2 >> 24, DESIG_UNIQUE_ID2 >> 16, DESIG_UNIQUE_ID2 >> 8, DESIG_UNIQUE_ID2 >> 0, DESIG_UNIQUE_ID1 >> 24, DESIG_UNIQUE_ID1 >> 16, DESIG_UNIQUE_ID1 >> 8);
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printf("- wafer number: %u\n", DESIG_UNIQUE_ID1 & 0xff);
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// from ARMv7-M and Cortex-M3 TRM
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// ARMv7-M B3.2.3
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printf("CPUID: 0x%08x\n", SCB_CPUID);
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const uint8_t cpuid_implementer = (SCB_CPUID & SCB_CPUID_IMPLEMENTER) >> SCB_CPUID_IMPLEMENTER_LSB;
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printf("- implementer: %s (0x%02x)\n", 0x41 == cpuid_implementer ? "ARM" : "unknown", cpuid_implementer);
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const uint8_t cpuid_architecture = (SCB_CPUID & SCB_CPUID_CONSTANT) >> SCB_CPUID_CONSTANT_LSB;
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puts("- architecture: ");
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switch (cpuid_architecture) {
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case 0xc:
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puts("ARMv6-M");
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break;
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case 0xf:
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puts("ARMv7-M");
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break;
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default:
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fake = true;
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puts("unknown");
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}
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printf(" (0x%x)\n", cpuid_architecture);
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const uint16_t cpuid_partno = (SCB_CPUID & SCB_CPUID_PARTNO) >> SCB_CPUID_PARTNO_LSB;
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puts("- part number: ");
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switch (cpuid_partno) {
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case 0xC60:
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puts("Cortex-M0+");
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break;
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case 0xC20:
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puts("Cortex‑M0");
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break;
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case 0xC23: // the ARM spec actually mentions 0xC24
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puts("Cortex‑M3");
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break;
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case 0xC24:
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puts("Cortex‑M4");
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break;
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case 0xC27:
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puts("Cortex‑M7");
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break;
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default:
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fake = true;
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puts("unknown");
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}
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printf(" (0x%03x)\n", cpuid_partno);
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const uint8_t cpuid_variant = (SCB_CPUID & SCB_CPUID_VARIANT) >> SCB_CPUID_VARIANT_LSB;
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printf("- variant: %u\n", cpuid_variant);
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const uint8_t cpuid_revision = (SCB_CPUID & SCB_CPUID_REVISION) >> SCB_CPUID_REVISION_LSB;
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printf("- revision: %u\n", cpuid_revision);
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// ARM CoreSight B2.2.2
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const uint8_t jep106_continuation = *(uint32_t*)0xE00FFFD0 & 0x0f; // DES_2, PIDR4 bits[3:0]
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const uint8_t jep106_identification = ((*(uint32_t*)0xE00FFFE8 & 0x7) << 4) + ((*(uint32_t*)0xE00FFFE4 >> 4) & 0xf); // DES_0, PIDR1 bits[7:4] JEP106 identification code bits[3:0], DES_1, PIDR2 bits[2:0] JEP106 identification code bits[6:4]
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const uint16_t pidr_partno = ((*(uint32_t*)0xE00FFFE4 & 0xf) << 8) + (*(uint32_t*)0xE00FFFE0 & 0xff); // PART_0, PIDR0 bits[7:0] Part number bits[7:0], PART_1, PIDR1 bits[3:0] Part number bits[11:8]
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puts("JEP106 ID: ");
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if (0 == jep106_continuation && 0x20 == jep106_identification) {
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puts("STM");
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} else if (7 == jep106_continuation && 0x51 == jep106_identification) {
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puts("GigaDevice");
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} else if (4 == jep106_continuation && 0x3b == jep106_identification) {
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puts("ARM");
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} else {
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puts("unknown");
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}
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printf(" (cont.=%u, ID=0x%02x), part=0x%03x\n", jep106_continuation, jep106_identification, pidr_partno);
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// guess the micro-controller
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puts("MCU: ");
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if (1 == cpuid_variant && 1 == cpuid_revision && 0 == jep106_continuation && 0x20 == jep106_identification) { // STM32 uses Cortex-M3 r1p1 and the right JEP106 ID
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puts("STM32");
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} else if (2 == cpuid_variant && 1 == cpuid_revision && 7 == jep106_continuation && 0x51 == jep106_identification) { // GD32 uses Cortex-M3 r2p1 and the right JEP106 ID
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puts("GD32");
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fake = true;
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} else if (2 == cpuid_variant && 1 == cpuid_revision && 4 == jep106_continuation && 0x3b == jep106_identification) { // GD32 uses Cortex-M3 r2p1 and ARM JEP106 ID
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puts("CS32");
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fake = true;
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} else {
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puts("unknown");
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fake = true;
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}
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putc('\n');
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// detect fake STM32
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if (0x412 == dev_id || 0x410 == dev_id || 0x414 == dev_id || 0x430 == dev_id || 0x418 == dev_id) { // STM32F10x
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// the original STM32F10x uses a Cortex-M3 r1p1
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if (0xC23 != cpuid_partno) { // Cortex-M3
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fake = true;
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}
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if (1 != cpuid_variant) { // r1
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fake = true;
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}
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if (1 != cpuid_revision) { // p1
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fake = true;
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}
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}
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printf("this %s to be a genuine STM32\n", fake ? "does not seem" : "seems");
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}
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static void command_uptime(void* argument)
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