i2c_master: minor, improve register read consistency
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@ -15,7 +15,7 @@
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/** library to communicate using I²C as master (code)
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* @file
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* @author King Kévin <kingkevin@cuvoodoo.info>
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* @date 2017-2019
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* @date 2017-2020
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* @note peripherals used: I2C
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*/
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@ -298,6 +298,7 @@ enum i2c_master_rc i2c_master_start(uint32_t i2c)
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bool retry = true; // retry after reset if first try failed
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enum i2c_master_rc to_return; // return code
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uint16_t sr1; // read register once, since reading/writing other registers or other events clears some flags
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try:
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to_return = I2C_MASTER_RC_NONE; // return code
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// send (re-)start condition
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@ -313,20 +314,22 @@ try:
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i2c_send_start(i2c); // send start condition to start transaction
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bool timeout = false; // remember if the timeout has been reached
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systick_counter_enable(); // start timer
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while ((I2C_CR1(i2c) & I2C_CR1_START) && !(I2C_SR1(i2c) & (I2C_SR1_BERR | I2C_SR1_ARLO)) && !timeout) { // wait until start condition has been accepted and cleared
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while ((I2C_CR1(i2c) & I2C_CR1_START) && !((sr1 = I2C_SR1(i2c)) & (I2C_SR1_BERR | I2C_SR1_ARLO)) && !timeout) { // wait until start condition has been accepted and cleared
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timeout |= systick_get_countflag(); // verify if timeout has been reached
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}
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if (I2C_SR1(i2c) & (I2C_SR1_BERR | I2C_SR1_ARLO)) {
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sr1 = I2C_SR1(i2c); // be sure to get the current value
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if (sr1 & (I2C_SR1_BERR | I2C_SR1_ARLO)) {
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to_return = I2C_MASTER_RC_BUS_ERROR;
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}
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while (!(I2C_SR1(i2c) & I2C_SR1_SB) && !(I2C_SR1(i2c) & (I2C_SR1_BERR | I2C_SR1_ARLO)) && !timeout && I2C_MASTER_RC_NONE == to_return) { // wait until start condition is transmitted
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while (!((sr1 = I2C_SR1(i2c)) & (I2C_SR1_SB | I2C_SR1_BERR | I2C_SR1_ARLO)) && !timeout && I2C_MASTER_RC_NONE == to_return) { // wait until start condition is transmitted
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timeout |= systick_get_countflag(); // verify if timeout has been reached
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}
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if (I2C_SR1(i2c) & (I2C_SR1_BERR|I2C_SR1_ARLO)) {
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sr1 = I2C_SR1(i2c); // be sure to get the current value
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if (sr1 & (I2C_SR1_BERR|I2C_SR1_ARLO)) {
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to_return = I2C_MASTER_RC_BUS_ERROR;
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} else if (!(I2C_SR1(i2c) & I2C_SR1_SB)) { // the start bit has not been set although we the peripheral is not busy anymore
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} else if (!(sr1 & I2C_SR1_SB)) { // the start bit has not been set although we the peripheral is not busy anymore
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to_return = I2C_MASTER_RC_BUS_ERROR;
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} else if (!(I2C_SR2(i2c) & I2C_SR2_MSL)) { // verify if in master mode
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} else if (!(sr1 & I2C_SR2_MSL)) { // verify if in master mode
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to_return = I2C_MASTER_RC_NOT_MASTER;
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} else if (timeout) { // timeout has been reached, i.e. the peripheral hangs
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to_return = I2C_MASTER_RC_NOT_MASTER;
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@ -347,43 +350,47 @@ enum i2c_master_rc i2c_master_select_slave(uint32_t i2c, uint16_t slave, bool ad
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cm3_assert(I2C1 == i2c || I2C2 == i2c);
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enum i2c_master_rc rc = I2C_MASTER_RC_NONE; // to store I²C return codes
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if (!(I2C_SR1(i2c) & I2C_SR1_SB)) { // start condition has not been sent
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uint16_t sr1, sr2; // read register once, since reading/writing other registers or other events clears some flags
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if (!((sr1 = I2C_SR1(i2c)) & I2C_SR1_SB)) { // start condition has not been sent
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rc = i2c_master_start(i2c); // send start condition
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if (I2C_MASTER_RC_NONE != rc) {
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return rc;
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}
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}
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if (!(I2C_SR2(i2c) & I2C_SR2_MSL)) { // I²C device is not in master mode
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if (!((sr2 = I2C_SR2(i2c)) & I2C_SR2_MSL)) { // I²C device is not in master mode
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return I2C_MASTER_RC_NOT_MASTER;
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}
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// select slave
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I2C_SR1(i2c) &= ~(I2C_SR1_AF); // clear acknowledgement failure
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if (!address_10bit) { // 7-bit address
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I2C_SR1(i2c) &= ~(I2C_SR1_AF); // clear acknowledgement failure
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i2c_send_7bit_address(i2c, slave, write ? I2C_WRITE : I2C_READ); // select slave, with read/write flag
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while (!(I2C_SR1(i2c) & (I2C_SR1_ADDR | I2C_SR1_AF)) && !(I2C_SR1(i2c) & (I2C_SR1_BERR | I2C_SR1_ARLO))); // wait until address is transmitted
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if (I2C_SR1(i2c) & (I2C_SR1_BERR | I2C_SR1_ARLO)) {
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while (!((sr1 = I2C_SR1(i2c)) & (I2C_SR1_ADDR | I2C_SR1_AF | I2C_SR1_BERR | I2C_SR1_ARLO))); // wait until address is transmitted
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if (sr1 & (I2C_SR1_BERR | I2C_SR1_ARLO)) {
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return I2C_MASTER_RC_BUS_ERROR;
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}
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if (I2C_SR1(i2c) & I2C_SR1_AF) { // address has not been acknowledged
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if (sr1 & I2C_SR1_AF) { // address has not been acknowledged
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return I2C_MASTER_RC_NAK;
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}
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} else { // 10-bit address
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// send first part of address
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I2C_SR1(i2c) &= ~(I2C_SR1_AF); // clear acknowledgement failure
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I2C_DR(i2c) = 11110000 | (((slave >> 8 ) & 0x3) << 1); // send first header (11110xx0, where xx are 2 MSb of slave address)
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while (!(I2C_SR1(i2c) & (I2C_SR1_ADD10 | I2C_SR1_AF)) && !(I2C_SR1(i2c) & (I2C_SR1_BERR | I2C_SR1_ARLO))); // wait until first part of address is transmitted
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if (I2C_SR1(i2c) & I2C_SR1_AF) { // address has not been acknowledged
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while (!((sr1 = I2C_SR1(i2c)) & (I2C_SR1_ADD10 | I2C_SR1_AF | I2C_SR1_BERR | I2C_SR1_ARLO))); // wait until first part of address is transmitted
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if (sr1 & (I2C_SR1_BERR | I2C_SR1_ARLO)) {
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return I2C_MASTER_RC_BUS_ERROR;
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}
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if (sr1 & I2C_SR1_AF) { // address has not been acknowledged
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return I2C_MASTER_RC_NAK;
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}
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// send second part of address
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I2C_SR1(i2c) &= ~(I2C_SR1_AF); // clear acknowledgement failure
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I2C_DR(i2c) = (slave & 0xff); // send remaining of address
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while (!(I2C_SR1(i2c) & (I2C_SR1_ADDR|I2C_SR1_AF)) && !(I2C_SR1(i2c) & (I2C_SR1_BERR | I2C_SR1_ARLO))); // wait until remaining part of address is transmitted
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if (I2C_SR1(i2c) & (I2C_SR1_BERR | I2C_SR1_ARLO)) {
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while (!((sr1 = I2C_SR1(i2c)) & (I2C_SR1_ADDR | I2C_SR1_AF | I2C_SR1_BERR | I2C_SR1_ARLO))); // wait until remaining part of address is transmitted
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if (sr1 & (I2C_SR1_BERR | I2C_SR1_ARLO)) {
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return I2C_MASTER_RC_BUS_ERROR;
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}
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if (I2C_SR1(i2c) & I2C_SR1_AF) { // address has not been acknowledged
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if (sr1 & I2C_SR1_AF) { // address has not been acknowledged
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return I2C_MASTER_RC_NAK;
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}
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// go into receive mode if necessary
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@ -395,11 +402,11 @@ enum i2c_master_rc i2c_master_select_slave(uint32_t i2c, uint16_t slave, bool ad
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// send first part of address with receive flag
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I2C_SR1(i2c) &= ~(I2C_SR1_AF); // clear acknowledgement failure
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I2C_DR(i2c) = 11110001 | (((slave >> 8) & 0x3) << 1); // send header (11110xx1, where xx are 2 MSb of slave address)
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while (!(I2C_SR1(i2c) & (I2C_SR1_ADDR | I2C_SR1_AF)) && !(I2C_SR1(i2c) & (I2C_SR1_BERR | I2C_SR1_ARLO))); // wait until remaining part of address is transmitted
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if (I2C_SR1(i2c) & (I2C_SR1_BERR | I2C_SR1_ARLO)) {
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while (!((sr1 = I2C_SR1(i2c)) & (I2C_SR1_ADDR | I2C_SR1_AF | I2C_SR1_BERR | I2C_SR1_ARLO))); // wait until remaining part of address is transmitted
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if (sr1 & (I2C_SR1_BERR | I2C_SR1_ARLO)) {
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return I2C_MASTER_RC_BUS_ERROR;
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}
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if (I2C_SR1(i2c) & I2C_SR1_AF) { // address has not been acknowledged
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if (sr1 & I2C_SR1_AF) { // address has not been acknowledged
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return I2C_MASTER_RC_NAK;
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}
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}
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@ -416,6 +423,16 @@ enum i2c_master_rc i2c_master_read(uint32_t i2c, uint8_t* data, size_t data_size
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if (NULL == data || 0 == data_size) { // no data to read
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return I2C_MASTER_RC_NONE;
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}
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// I²C start condition check
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uint16_t sr1 = I2C_SR1(i2c); // read once
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if (!(sr1 & I2C_SR1_ADDR)) { // no slave have been selected
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return I2C_MASTER_RC_NOT_READY;
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}
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if (sr1 & I2C_SR1_AF) { // check if the previous transaction went well
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return I2C_MASTER_RC_NOT_READY;
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}
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if (1 == data_size) {
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i2c_nack_current(i2c); // [N]ACK current byte
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i2c_disable_ack(i2c); // NACK after first byte
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@ -426,16 +443,13 @@ enum i2c_master_rc i2c_master_read(uint32_t i2c, uint8_t* data, size_t data_size
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i2c_nack_current(i2c); // ACK current byte
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i2c_enable_ack(i2c); // NAK after next byte
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}
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// reading SR2 will also also clear ADDR and start the transaction
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if (!(I2C_SR2(i2c) & I2C_SR2_MSL)) { // I²C device is not master
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uint16_t sr2 = I2C_SR2(i2c); // reading SR2 will also also clear ADDR in SR1 and start the transaction
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if (!(sr2 & I2C_SR2_MSL)) { // I²C device is not master
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return I2C_MASTER_RC_NOT_MASTER;
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}
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if ((I2C_SR2(i2c) & I2C_SR2_TRA)) { // I²C device not in receiver mode
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if ((sr2 & I2C_SR2_TRA)) { // I²C device not in receiver mode
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return I2C_MASTER_RC_NOT_RECEIVE;
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}
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if (I2C_SR1(i2c) & I2C_SR1_AF) { // check if the previous transaction went well
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return I2C_MASTER_RC_NOT_READY;
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}
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// read data
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for (size_t i = 0; i < data_size; i++) { // read bytes
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@ -448,8 +462,8 @@ enum i2c_master_rc i2c_master_read(uint32_t i2c, uint8_t* data, size_t data_size
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} else {
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i2c_enable_ack(i2c); // ACK received byte to continue slave transmission
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}
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while (!(I2C_SR1(i2c) & I2C_SR1_RxNE) && !(I2C_SR1(i2c) & (I2C_SR1_BERR | I2C_SR1_ARLO))); // wait until byte has been received
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if (I2C_SR1(i2c) & (I2C_SR1_BERR|I2C_SR1_ARLO)) {
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while (!((sr1 = I2C_SR1(i2c)) & (I2C_SR1_RxNE | I2C_SR1_BERR | I2C_SR1_ARLO))); // wait until byte has been received
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if (sr1 & (I2C_SR1_BERR|I2C_SR1_ARLO)) {
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return I2C_MASTER_RC_BUS_ERROR;
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}
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data[i] = i2c_get_data(i2c); // read received byte
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@ -466,15 +480,24 @@ enum i2c_master_rc i2c_master_write(uint32_t i2c, const uint8_t* data, size_t da
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if (NULL == data || 0 == data_size) { // no data to write
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return I2C_MASTER_RC_NONE;
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}
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if (!(I2C_SR2(i2c) & I2C_SR2_MSL)) { // I²C device is not master
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// I²C start condition check
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uint16_t sr1 = I2C_SR1(i2c); // read once
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if (!(sr1 & I2C_SR1_ADDR)) { // no slave have been selected
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return I2C_MASTER_RC_NOT_READY;
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}
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if (sr1 & I2C_SR1_AF) { // check if the previous transaction went well
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return I2C_MASTER_RC_NOT_READY;
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}
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// master check
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uint16_t sr2 = I2C_SR2(i2c); // reading SR2 will also also clear ADDR in SR1 and start the transaction
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if (!(sr2 & I2C_SR2_MSL)) { // I²C device is not master
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return I2C_MASTER_RC_NOT_MASTER;
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}
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if (!(I2C_SR2(i2c) & I2C_SR2_TRA)) { // I²C device not in transmitter mode
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if (!(sr2 & I2C_SR2_TRA)) { // I²C device not in transmitter mode
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return I2C_MASTER_RC_NOT_TRANSMIT;
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}
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if (I2C_SR1(i2c) & I2C_SR1_AF) { // check if the previous transaction went well
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return I2C_MASTER_RC_NOT_READY;
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}
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// write data
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for (size_t i = 0; i < data_size; i++) { // write bytes
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@ -15,8 +15,8 @@
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/** library to communicate using I²C as master (API)
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* @file
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* @author King Kévin <kingkevin@cuvoodoo.info>
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* @date 2017-2019
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* @note peripherals used: I²C
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* @date 2017-2020
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* @note peripherals used: I2C
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*/
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#pragma once
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