I2C: allows multiple I2C peripherals to be used
This commit is contained in:
parent
fed8637079
commit
14cdeba690
434
lib/i2c_master.c
434
lib/i2c_master.c
|
|
@ -16,7 +16,7 @@
|
|||
* @file i2c_master.c
|
||||
* @author King Kévin <kingkevin@cuvoodoo.info>
|
||||
* @date 2017-2018
|
||||
* @note peripherals used: I2C @ref i2c_master_i2c, timer @ref i2c_master_timer
|
||||
* @note peripherals used: I2C, timer @ref i2c_master_timer
|
||||
*/
|
||||
|
||||
/* standard libraries */
|
||||
|
|
@ -34,12 +34,6 @@
|
|||
#include "global.h" // global utilities
|
||||
#include "i2c_master.h" // I2C header and definitions
|
||||
|
||||
/** @defgroup i2c_master_i2c I2C peripheral used to communicate
|
||||
* @{
|
||||
*/
|
||||
#define I2C_MASTER_I2C 1 /**< I2C peripheral */
|
||||
/** @} */
|
||||
|
||||
/** @defgroup i2c_master_timer timer peripheral used for timeouts
|
||||
* @{
|
||||
*/
|
||||
|
|
@ -47,101 +41,286 @@
|
|||
#define I2C_MASTER_TIMEOUT 4 /**< timeout factor (compared to expected time) */
|
||||
/** @} */
|
||||
|
||||
void i2c_master_setup(bool fast)
|
||||
/** if the I2C peripheral uses the timer */
|
||||
static bool i2c_master_timer_usage[] = {false, false};
|
||||
|
||||
/** get RCC for I2C based on I2C identifier
|
||||
* @param[in] i2c I2C base address
|
||||
* @return RCC address for I2C peripheral
|
||||
*/
|
||||
static uint32_t RCC_I2C(uint32_t i2c)
|
||||
{
|
||||
// configure I2C peripheral
|
||||
rcc_periph_clock_enable(RCC_I2C_SCL_PORT(I2C_MASTER_I2C)); // enable clock for I2C I/O peripheral
|
||||
gpio_set(I2C_SCL_PORT(I2C_MASTER_I2C), I2C_SCL_PIN(I2C_MASTER_I2C)); // already put signal high to avoid small pulse
|
||||
gpio_set_mode(I2C_SCL_PORT(I2C_MASTER_I2C), GPIO_MODE_OUTPUT_2_MHZ, GPIO_CNF_OUTPUT_ALTFN_OPENDRAIN, I2C_SCL_PIN(I2C_MASTER_I2C)); // setup I2C I/O pins
|
||||
rcc_periph_clock_enable(RCC_I2C_SCL_PORT(I2C_MASTER_I2C)); // enable clock for I2C I/O peripheral
|
||||
gpio_set(I2C_SDA_PORT(I2C_MASTER_I2C), I2C_SDA_PIN(I2C_MASTER_I2C)); // already put signal high to avoid small pulse
|
||||
gpio_set_mode(I2C_SDA_PORT(I2C_MASTER_I2C), GPIO_MODE_OUTPUT_2_MHZ, GPIO_CNF_OUTPUT_ALTFN_OPENDRAIN, I2C_SDA_PIN(I2C_MASTER_I2C)); // setup I2C I/O pins
|
||||
rcc_periph_clock_enable(RCC_AFIO); // enable clock for alternate function
|
||||
rcc_periph_clock_enable(RCC_I2C(I2C_MASTER_I2C)); // enable clock for I2C peripheral
|
||||
i2c_reset(I2C(I2C_MASTER_I2C)); // reset configuration
|
||||
i2c_peripheral_disable(I2C(I2C_MASTER_I2C)); // I2C needs to be disable to be configured
|
||||
i2c_set_clock_frequency(I2C(I2C_MASTER_I2C), rcc_apb1_frequency/1000000); // configure the peripheral clock to the APB1 freq (where it is connected to)
|
||||
if (fast) {
|
||||
i2c_set_fast_mode(I2C(I2C_MASTER_I2C));
|
||||
i2c_set_ccr(I2C(I2C_MASTER_I2C), rcc_apb1_frequency/(400000*2)); // set Thigh/Tlow to generate frequency of 400 kHz
|
||||
i2c_set_trise(I2C(I2C_MASTER_I2C), (300/(1000/(rcc_apb1_frequency/1000000)))+1); // max rise time for 300 kHz is 300 ns
|
||||
} else {
|
||||
i2c_set_standard_mode(I2C(I2C_MASTER_I2C)); // the DS1307 has a maximum I2C SCL freq if 100 kHz (corresponding to the standard mode)
|
||||
i2c_set_ccr(I2C(I2C_MASTER_I2C), rcc_apb1_frequency/(100000*2)); // set Thigh/Tlow to generate frequency of 100 kHz
|
||||
i2c_set_trise(I2C(I2C_MASTER_I2C), (1000/(1000/(rcc_apb1_frequency/1000000)))+1); // max rise time for 100 kHz is 1000 ns (~1 MHz)
|
||||
switch (i2c) {
|
||||
case I2C1:
|
||||
return RCC_I2C1;
|
||||
break;
|
||||
case I2C2:
|
||||
return RCC_I2C2;
|
||||
break;
|
||||
default:
|
||||
while (true);
|
||||
}
|
||||
i2c_peripheral_enable(I2C(I2C_MASTER_I2C)); // enable I2C after configuration completed
|
||||
|
||||
// configure time for timeouts
|
||||
rcc_periph_clock_enable(RCC_TIM(I2C_MASTER_TIMER)); // enable clock for timer block
|
||||
timer_reset(TIM(I2C_MASTER_TIMER)); // reset timer state
|
||||
timer_set_mode(TIM(I2C_MASTER_TIMER), TIM_CR1_CKD_CK_INT, TIM_CR1_CMS_EDGE, TIM_CR1_DIR_UP); // set timer mode, use undivided timer clock, edge alignment (simple count), and count up
|
||||
timer_one_shot_mode(TIM(I2C_MASTER_TIMER)); // stop counter after update event (we only need to one timeout and reset before next operation)
|
||||
if (fast) {
|
||||
timer_set_prescaler(TIM(I2C_MASTER_TIMER), rcc_ahb_frequency/400000-1); // set the prescaler so one tick is also one I2C bit (used I2C frequency)
|
||||
} else {
|
||||
timer_set_prescaler(TIM(I2C_MASTER_TIMER), rcc_ahb_frequency/100000-1); // set the prescaler so one tick is also one I2C bit (used I2C frequency)
|
||||
}
|
||||
/** get RCC for GPIO port for SCL pin based on I2C identifier
|
||||
* @param[in] i2c I2C base address
|
||||
* @return RCC GPIO address
|
||||
*/
|
||||
static uint32_t RCC_GPIO_PORT_SCL(uint32_t i2c)
|
||||
{
|
||||
switch (i2c) {
|
||||
case I2C1:
|
||||
case I2C2:
|
||||
return RCC_GPIOB;
|
||||
break;
|
||||
default:
|
||||
while (true);
|
||||
}
|
||||
}
|
||||
/** get RCC for GPIO port for SDA pin based on I2C identifier
|
||||
* @param[in] i2c I2C base address
|
||||
* @return RCC GPIO address
|
||||
*/
|
||||
static uint32_t RCC_GPIO_PORT_SDA(uint32_t i2c)
|
||||
{
|
||||
switch (i2c) {
|
||||
case I2C1:
|
||||
case I2C2:
|
||||
return RCC_GPIOB;
|
||||
break;
|
||||
default:
|
||||
while (true);
|
||||
}
|
||||
}
|
||||
/** get GPIO port for SCL pin based on I2C identifier
|
||||
* @param[in] i2c I2C base address
|
||||
* @return GPIO address
|
||||
*/
|
||||
static uint32_t GPIO_PORT_SCL(uint32_t i2c)
|
||||
{
|
||||
switch (i2c) {
|
||||
case I2C1:
|
||||
if (AFIO_MAPR & AFIO_MAPR_I2C1_REMAP) {
|
||||
return GPIO_BANK_I2C1_RE_SCL;
|
||||
} else {
|
||||
return GPIO_BANK_I2C1_SCL;
|
||||
}
|
||||
break;
|
||||
case I2C2:
|
||||
return GPIO_BANK_I2C2_SCL;
|
||||
break;
|
||||
default:
|
||||
while (true);
|
||||
}
|
||||
}
|
||||
/** get GPIO port for SDA pin based on I2C identifier
|
||||
* @param[in] i2c I2C base address
|
||||
* @return GPIO address
|
||||
*/
|
||||
static uint32_t GPIO_PORT_SDA(uint32_t i2c)
|
||||
{
|
||||
switch (i2c) {
|
||||
case I2C1:
|
||||
if (AFIO_MAPR & AFIO_MAPR_I2C1_REMAP) {
|
||||
return GPIO_BANK_I2C1_RE_SDA;
|
||||
} else {
|
||||
return GPIO_BANK_I2C1_SDA;
|
||||
}
|
||||
break;
|
||||
case I2C2:
|
||||
return GPIO_BANK_I2C2_SDA;
|
||||
break;
|
||||
default:
|
||||
while (true);
|
||||
}
|
||||
}
|
||||
/** get GPIO pin for SCL pin based on I2C identifier
|
||||
* @param[in] i2c I2C base address
|
||||
* @return GPIO address
|
||||
*/
|
||||
static uint32_t GPIO_PIN_SCL(uint32_t i2c)
|
||||
{
|
||||
switch (i2c) {
|
||||
case I2C1:
|
||||
if (AFIO_MAPR & AFIO_MAPR_I2C1_REMAP) {
|
||||
return GPIO_I2C1_RE_SCL;
|
||||
} else {
|
||||
return GPIO_I2C1_SCL;
|
||||
}
|
||||
break;
|
||||
case I2C2:
|
||||
return GPIO_I2C2_SCL;
|
||||
break;
|
||||
default:
|
||||
while (true);
|
||||
}
|
||||
}
|
||||
/** get GPIO pin for SDA pin based on I2C identifier
|
||||
* @param[in] i2c I2C base address
|
||||
* @return GPIO address
|
||||
*/
|
||||
static uint32_t GPIO_PIN_SDA(uint32_t i2c)
|
||||
{
|
||||
switch (i2c) {
|
||||
case I2C1:
|
||||
if (AFIO_MAPR & AFIO_MAPR_I2C1_REMAP) {
|
||||
return GPIO_I2C1_RE_SDA;
|
||||
} else {
|
||||
return GPIO_I2C1_SDA;
|
||||
}
|
||||
break;
|
||||
case I2C2:
|
||||
return GPIO_I2C2_SDA;
|
||||
break;
|
||||
default:
|
||||
while (true);
|
||||
}
|
||||
timer_set_period(TIM(I2C_MASTER_TIMER), I2C_MASTER_TIMEOUT*9); // use factor to wait for all 9 bits to be transmitted
|
||||
timer_update_on_overflow(TIM(I2C_MASTER_TIMER)); // only use counter overflow as UEV source (use overflow as timeout)
|
||||
|
||||
// wait one transaction for the signal to be stable (some slave have issues when an I2C transaction immediately follows)
|
||||
timer_set_counter(TIM(I2C_MASTER_TIMER),0); // restart timer
|
||||
timer_clear_flag(TIM(I2C_MASTER_TIMER), TIM_SR_UIF); // clear flag
|
||||
timer_enable_counter(TIM(I2C_MASTER_TIMER)); // enable timer for timeouts
|
||||
while ( !timer_get_flag(TIM(I2C_MASTER_TIMER), TIM_SR_UIF));
|
||||
timer_disable_counter(TIM(I2C_MASTER_TIMER)); // disable timer for timeouts
|
||||
timer_clear_flag(TIM(I2C_MASTER_TIMER), TIM_SR_UIF); // clear flag
|
||||
}
|
||||
|
||||
bool i2c_master_start(void)
|
||||
void i2c_master_setup(uint32_t i2c, bool fast)
|
||||
{
|
||||
// check I2C peripheral
|
||||
if (I2C1!=i2c && I2C2!=i2c) {
|
||||
while (true);
|
||||
}
|
||||
|
||||
// configure I2C peripheral
|
||||
rcc_periph_clock_enable(RCC_GPIO_PORT_SCL(i2c)); // enable clock for I2C I/O peripheral
|
||||
gpio_set(GPIO_PORT_SCL(i2c), GPIO_PIN_SCL(i2c)); // already put signal high to avoid small pulse
|
||||
gpio_set_mode(GPIO_PORT_SCL(i2c), GPIO_MODE_OUTPUT_2_MHZ, GPIO_CNF_OUTPUT_ALTFN_OPENDRAIN, GPIO_PIN_SCL(i2c)); // setup I2C I/O pins
|
||||
rcc_periph_clock_enable(RCC_GPIO_PORT_SDA(i2c)); // enable clock for I2C I/O peripheral
|
||||
gpio_set(GPIO_PORT_SDA(i2c), GPIO_PIN_SDA(i2c)); // already put signal high to avoid small pulse
|
||||
gpio_set_mode(GPIO_PORT_SDA(i2c), GPIO_MODE_OUTPUT_2_MHZ, GPIO_CNF_OUTPUT_ALTFN_OPENDRAIN, GPIO_PIN_SDA(i2c)); // setup I2C I/O pins
|
||||
rcc_periph_clock_enable(RCC_AFIO); // enable clock for alternate function
|
||||
rcc_periph_clock_enable(RCC_I2C(i2c)); // enable clock for I2C peripheral
|
||||
i2c_reset(i2c); // reset configuration
|
||||
i2c_peripheral_disable(i2c); // I2C needs to be disable to be configured
|
||||
i2c_set_clock_frequency(i2c, rcc_apb1_frequency/1000000); // configure the peripheral clock to the APB1 freq (where it is connected to)
|
||||
if (fast) {
|
||||
i2c_set_fast_mode(i2c);
|
||||
i2c_set_ccr(i2c, rcc_apb1_frequency/(400000*2)); // set Thigh/Tlow to generate frequency of 400 kHz
|
||||
i2c_set_trise(i2c, (300/(1000/(rcc_apb1_frequency/1000000)))+1); // max rise time for 300 kHz is 300 ns
|
||||
} else {
|
||||
i2c_set_standard_mode(i2c); // the DS1307 has a maximum I2C SCL freq if 100 kHz (corresponding to the standard mode)
|
||||
i2c_set_ccr(i2c, rcc_apb1_frequency/(100000*2)); // set Thigh/Tlow to generate frequency of 100 kHz
|
||||
i2c_set_trise(i2c, (1000/(1000/(rcc_apb1_frequency/1000000)))+1); // max rise time for 100 kHz is 1000 ns (~1 MHz)
|
||||
}
|
||||
i2c_peripheral_enable(i2c); // enable I2C after configuration completed
|
||||
|
||||
// configure time for timeouts
|
||||
if (!i2c_master_timer_usage[0] && !i2c_master_timer_usage[1]) {
|
||||
rcc_periph_clock_enable(RCC_TIM(I2C_MASTER_TIMER)); // enable clock for timer block
|
||||
timer_reset(TIM(I2C_MASTER_TIMER)); // reset timer state
|
||||
timer_set_mode(TIM(I2C_MASTER_TIMER), TIM_CR1_CKD_CK_INT, TIM_CR1_CMS_EDGE, TIM_CR1_DIR_UP); // set timer mode, use undivided timer clock, edge alignment (simple count), and count up
|
||||
timer_one_shot_mode(TIM(I2C_MASTER_TIMER)); // stop counter after update event (we only need to one timeout and reset before next operation)
|
||||
if (fast) {
|
||||
timer_set_prescaler(TIM(I2C_MASTER_TIMER), rcc_ahb_frequency/400000-1); // set the prescaler so one tick is also one I2C bit (used I2C frequency)
|
||||
} else {
|
||||
timer_set_prescaler(TIM(I2C_MASTER_TIMER), rcc_ahb_frequency/100000-1); // set the prescaler so one tick is also one I2C bit (used I2C frequency)
|
||||
}
|
||||
timer_set_period(TIM(I2C_MASTER_TIMER), I2C_MASTER_TIMEOUT*9); // use factor to wait for all 9 bits to be transmitted
|
||||
timer_update_on_overflow(TIM(I2C_MASTER_TIMER)); // only use counter overflow as UEV source (use overflow as timeout)
|
||||
|
||||
// wait one transaction for the signal to be stable (some slave have issues when an I2C transaction immediately follows)
|
||||
timer_set_counter(TIM(I2C_MASTER_TIMER),0); // restart timer
|
||||
timer_clear_flag(TIM(I2C_MASTER_TIMER), TIM_SR_UIF); // clear flag
|
||||
timer_enable_counter(TIM(I2C_MASTER_TIMER)); // enable timer for timeouts
|
||||
while ( !timer_get_flag(TIM(I2C_MASTER_TIMER), TIM_SR_UIF));
|
||||
timer_disable_counter(TIM(I2C_MASTER_TIMER)); // disable timer for timeouts
|
||||
timer_clear_flag(TIM(I2C_MASTER_TIMER), TIM_SR_UIF); // clear flag
|
||||
}
|
||||
|
||||
// remember the I2C peripheral uses the timer
|
||||
if (I2C1==i2c) {
|
||||
i2c_master_timer_usage[0]=true;
|
||||
} else if (I2C2==i2c) {
|
||||
i2c_master_timer_usage[1]=true;
|
||||
}
|
||||
}
|
||||
|
||||
void i2c_master_release(uint32_t i2c)
|
||||
{
|
||||
i2c_reset(i2c); // reset I2C peripheral configuration
|
||||
i2c_peripheral_disable(i2c); // disable I2C peripheral
|
||||
rcc_periph_clock_disable(RCC_I2C(i2c)); // disable clock for I2C peripheral
|
||||
gpio_set_mode(GPIO_PORT_SCL(i2c), GPIO_MODE_INPUT, GPIO_CNF_INPUT_FLOAT, GPIO_PIN_SCL(i2c)); // put I2C I/O pins back to floating
|
||||
gpio_set_mode(GPIO_PORT_SDA(i2c), GPIO_MODE_INPUT, GPIO_CNF_INPUT_FLOAT, GPIO_PIN_SDA(i2c)); // put I2C I/O pins back to floating
|
||||
// remember the I2C peripheral doesn't use the timer anymore
|
||||
if (I2C1==i2c) {
|
||||
i2c_master_timer_usage[0]=false;
|
||||
} else if (I2C2==i2c) {
|
||||
i2c_master_timer_usage[1]=false;
|
||||
}
|
||||
if (!i2c_master_timer_usage[0] && !i2c_master_timer_usage[1]) {
|
||||
timer_reset(TIM(I2C_MASTER_TIMER)); // reset timer configuration
|
||||
timer_disable_counter(TIM(I2C_MASTER_TIMER)); // disable timer
|
||||
rcc_periph_clock_disable(RCC_TIM(I2C_MASTER_TIMER)); // disable clock for timer block
|
||||
}
|
||||
}
|
||||
|
||||
bool i2c_master_check_signals(uint32_t i2c)
|
||||
{
|
||||
return (0!=gpio_get(GPIO_PORT_SCL(i2c), GPIO_PIN_SCL(i2c)) && 0!=gpio_get(GPIO_PORT_SDA(i2c), GPIO_PIN_SDA(i2c)));
|
||||
}
|
||||
|
||||
|
||||
bool i2c_master_start(uint32_t i2c)
|
||||
{
|
||||
// check I2C peripheral
|
||||
if (I2C1!=i2c && I2C2!=i2c) {
|
||||
while (true);
|
||||
}
|
||||
|
||||
// send (re-)start condition
|
||||
i2c_send_start(I2C(I2C_MASTER_I2C)); // send start condition to start transaction
|
||||
i2c_send_start(i2c); // send start condition to start transaction
|
||||
timer_set_counter(TIM(I2C_MASTER_TIMER), 0); // restart timer
|
||||
timer_clear_flag(TIM(I2C_MASTER_TIMER), TIM_SR_UIF); // clear flag
|
||||
timer_enable_counter(TIM(I2C_MASTER_TIMER)); // enable timer for timeouts
|
||||
while (!(I2C_SR1(I2C(I2C_MASTER_I2C)) & I2C_SR1_SB) && !timer_get_flag(TIM(I2C_MASTER_TIMER), TIM_SR_UIF)); // wait until start condition is transmitted
|
||||
while (!(I2C_SR1(i2c) & I2C_SR1_SB) && !timer_get_flag(TIM(I2C_MASTER_TIMER), TIM_SR_UIF)); // wait until start condition is transmitted
|
||||
timer_disable_counter(TIM(I2C_MASTER_TIMER)); // disable timer for timeouts
|
||||
if (timer_get_flag(TIM(I2C_MASTER_TIMER), TIM_SR_UIF)) { // timeout occurred
|
||||
timer_clear_flag(TIM(I2C_MASTER_TIMER), TIM_SR_UIF); // clear flag
|
||||
return false;
|
||||
}
|
||||
if (!(I2C_SR2(I2C(I2C_MASTER_I2C)) & I2C_SR2_MSL)) { // verify if in master mode
|
||||
if (!(I2C_SR2(i2c) & I2C_SR2_MSL)) { // verify if in master mode
|
||||
return false;
|
||||
}
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
bool i2c_master_select_slave(uint8_t slave, bool write)
|
||||
bool i2c_master_select_slave(uint32_t i2c, uint8_t slave, bool write)
|
||||
{
|
||||
if (!(I2C_SR2(I2C(I2C_MASTER_I2C)) & I2C_SR2_BUSY)) { // I2C device is not busy (start condition has not been sent)
|
||||
if (!i2c_master_start()) { // send start condition
|
||||
// check I2C peripheral
|
||||
if (I2C1!=i2c && I2C2!=i2c) {
|
||||
while (true);
|
||||
}
|
||||
|
||||
if (!(I2C_SR2(i2c) & I2C_SR2_BUSY)) { // I2C device is not busy (start condition has not been sent)
|
||||
if (!i2c_master_start(i2c)) { // send start condition
|
||||
return false; // could not send start condition
|
||||
}
|
||||
}
|
||||
if (!(I2C_SR2(I2C(I2C_MASTER_I2C)) & I2C_SR2_MSL)) { // I2C device is already not master mode
|
||||
if (!(I2C_SR2(i2c) & I2C_SR2_MSL)) { // I2C device is already not master mode
|
||||
return false;
|
||||
}
|
||||
|
||||
// select slave
|
||||
i2c_send_7bit_address(I2C(I2C_MASTER_I2C), slave, write ? I2C_WRITE : I2C_READ); // select slave, with read/write flag
|
||||
i2c_send_7bit_address(i2c, slave, write ? I2C_WRITE : I2C_READ); // select slave, with read/write flag
|
||||
timer_set_counter(TIM(I2C_MASTER_TIMER), 0); // restart timer
|
||||
timer_clear_flag(TIM(I2C_MASTER_TIMER), TIM_SR_UIF); // clear flag
|
||||
timer_enable_counter(TIM(I2C_MASTER_TIMER)); // enable timer for timeouts
|
||||
while (!(I2C_SR1(I2C(I2C_MASTER_I2C)) & I2C_SR1_ADDR) && !timer_get_flag(TIM(I2C_MASTER_TIMER), TIM_SR_UIF)); // wait until address is transmitted
|
||||
while (!(I2C_SR1(i2c) & I2C_SR1_ADDR) && !timer_get_flag(TIM(I2C_MASTER_TIMER), TIM_SR_UIF)); // wait until address is transmitted
|
||||
timer_disable_counter(TIM(I2C_MASTER_TIMER)); // disable timer for timeouts
|
||||
if (timer_get_flag(TIM(I2C_MASTER_TIMER), TIM_SR_UIF)) { // timeout occurred (no ACK received)
|
||||
timer_clear_flag(TIM(I2C_MASTER_TIMER), TIM_SR_UIF); // clear flag
|
||||
return false;
|
||||
}
|
||||
if (write) {
|
||||
if (!((I2C_SR2(I2C(I2C_MASTER_I2C)) & I2C_SR2_TRA))) { // verify we are in transmit mode (and read SR2 to clear ADDR)
|
||||
if (!((I2C_SR2(i2c) & I2C_SR2_TRA))) { // verify we are in transmit mode (and read SR2 to clear ADDR)
|
||||
return false;
|
||||
}
|
||||
} else {
|
||||
if ((I2C_SR2(I2C(I2C_MASTER_I2C)) & I2C_SR2_TRA)) { // verify we are in read mode (and read SR2 to clear ADDR)
|
||||
if ((I2C_SR2(i2c) & I2C_SR2_TRA)) { // verify we are in read mode (and read SR2 to clear ADDR)
|
||||
return false;
|
||||
}
|
||||
}
|
||||
|
|
@ -149,62 +328,72 @@ bool i2c_master_select_slave(uint8_t slave, bool write)
|
|||
return true;
|
||||
}
|
||||
|
||||
bool i2c_master_read(uint8_t* data, size_t data_size)
|
||||
bool i2c_master_read(uint32_t i2c, uint8_t* data, size_t data_size)
|
||||
{
|
||||
// check I2C peripheral
|
||||
if (I2C1!=i2c && I2C2!=i2c) {
|
||||
while (true);
|
||||
}
|
||||
|
||||
// sanity check
|
||||
if (data==NULL || data_size==0) { // no data to read
|
||||
return true;
|
||||
}
|
||||
if (!(I2C_SR2(I2C(I2C_MASTER_I2C)) & I2C_SR2_BUSY)) { // I2C device is not busy (start condition has not been sent)
|
||||
if (!(I2C_SR2(i2c) & I2C_SR2_BUSY)) { // I2C device is not busy (start condition has not been sent)
|
||||
return false; // address has probably also not been sent
|
||||
}
|
||||
if (!(I2C_SR2(I2C(I2C_MASTER_I2C)) & I2C_SR2_MSL)) { // I2C device not master mode
|
||||
if (!(I2C_SR2(i2c) & I2C_SR2_MSL)) { // I2C device not master mode
|
||||
return false;
|
||||
}
|
||||
|
||||
// read data
|
||||
for (size_t i=0; i<data_size; i++) { // read bytes
|
||||
if (i==data_size-1) { // prepare to sent NACK for last byte
|
||||
i2c_disable_ack(I2C(I2C_MASTER_I2C)); // NACK received to stop slave transmission
|
||||
i2c_send_stop(I2C(I2C_MASTER_I2C)); // send STOP after receiving byte
|
||||
i2c_disable_ack(i2c); // NACK received to stop slave transmission
|
||||
i2c_send_stop(i2c); // send STOP after receiving byte
|
||||
} else {
|
||||
i2c_enable_ack(I2C(I2C_MASTER_I2C)); // ACK received byte to continue slave transmission
|
||||
i2c_enable_ack(i2c); // ACK received byte to continue slave transmission
|
||||
}
|
||||
timer_set_counter(TIM(I2C_MASTER_TIMER), 0); // restart timer
|
||||
timer_clear_flag(TIM(I2C_MASTER_TIMER), TIM_SR_UIF); // clear flag
|
||||
timer_enable_counter(TIM(I2C_MASTER_TIMER)); // enable timer for timeouts
|
||||
while (!(I2C_SR1(I2C(I2C_MASTER_I2C)) & I2C_SR1_RxNE) && !timer_get_flag(TIM(I2C_MASTER_TIMER), TIM_SR_UIF)); // wait until byte has been received
|
||||
while (!(I2C_SR1(i2c) & I2C_SR1_RxNE) && !timer_get_flag(TIM(I2C_MASTER_TIMER), TIM_SR_UIF)); // wait until byte has been received
|
||||
timer_disable_counter(TIM(I2C_MASTER_TIMER)); // disable timer for timeouts
|
||||
if (timer_get_flag(TIM(I2C_MASTER_TIMER), TIM_SR_UIF)) { // timeout occurred
|
||||
timer_clear_flag(TIM(I2C_MASTER_TIMER), TIM_SR_UIF); // clear flag
|
||||
return false;
|
||||
}
|
||||
data[i] = i2c_get_data(I2C(I2C_MASTER_I2C)); // read received byte
|
||||
data[i] = i2c_get_data(i2c); // read received byte
|
||||
}
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
bool i2c_master_write(const uint8_t* data, size_t data_size)
|
||||
bool i2c_master_write(uint32_t i2c, const uint8_t* data, size_t data_size)
|
||||
{
|
||||
// check I2C peripheral
|
||||
if (I2C1!=i2c && I2C2!=i2c) {
|
||||
while (true);
|
||||
}
|
||||
|
||||
// sanity check
|
||||
if (data==NULL || data_size==0) { // no data to write
|
||||
return true;
|
||||
}
|
||||
if (!(I2C_SR2(I2C(I2C_MASTER_I2C)) & I2C_SR2_BUSY)) { // I2C device is not busy (start condition has not been sent)
|
||||
if (!(I2C_SR2(i2c) & I2C_SR2_BUSY)) { // I2C device is not busy (start condition has not been sent)
|
||||
return false; // address has probably also not been sent
|
||||
}
|
||||
if (!(I2C_SR2(I2C(I2C_MASTER_I2C)) & I2C_SR2_MSL)) { // I2C device is not master mode
|
||||
if (!(I2C_SR2(i2c) & I2C_SR2_MSL)) { // I2C device is not master mode
|
||||
return false;
|
||||
}
|
||||
|
||||
// write data
|
||||
for (size_t i=0; i<data_size; i++) { // write bytes
|
||||
i2c_send_data(I2C(I2C_MASTER_I2C), data[i]); // send byte to be written in memory
|
||||
i2c_send_data(i2c, data[i]); // send byte to be written in memory
|
||||
timer_set_counter(TIM(I2C_MASTER_TIMER),0); // restart timer
|
||||
timer_clear_flag(TIM(I2C_MASTER_TIMER), TIM_SR_UIF); // clear flag
|
||||
timer_enable_counter(TIM(I2C_MASTER_TIMER)); // enable timer for timeouts
|
||||
while (!(I2C_SR1(I2C(I2C_MASTER_I2C)) & I2C_SR1_TxE) && !timer_get_flag(TIM(I2C_MASTER_TIMER), TIM_SR_UIF)); // wait until byte has been transmitted
|
||||
while (!(I2C_SR1(i2c) & I2C_SR1_TxE) && !timer_get_flag(TIM(I2C_MASTER_TIMER), TIM_SR_UIF)); // wait until byte has been transmitted
|
||||
timer_disable_counter(TIM(I2C_MASTER_TIMER)); // disable timer for timeouts
|
||||
if (timer_get_flag(TIM(I2C_MASTER_TIMER), TIM_SR_UIF)) { // timeout occurred (no ACK received)
|
||||
timer_clear_flag(TIM(I2C_MASTER_TIMER), TIM_SR_UIF); // clear flag
|
||||
|
|
@ -215,99 +404,119 @@ bool i2c_master_write(const uint8_t* data, size_t data_size)
|
|||
return true;
|
||||
}
|
||||
|
||||
void i2c_master_stop(void)
|
||||
void i2c_master_stop(uint32_t i2c)
|
||||
{
|
||||
// check I2C peripheral
|
||||
if (I2C1!=i2c && I2C2!=i2c) {
|
||||
while (true);
|
||||
}
|
||||
|
||||
// sanity check
|
||||
if (!(I2C_SR2(I2C(I2C_MASTER_I2C)) & I2C_SR2_BUSY)) { // release is not busy
|
||||
if (!(I2C_SR2(i2c) & I2C_SR2_BUSY)) { // release is not busy
|
||||
return; // bus has probably already been released
|
||||
}
|
||||
|
||||
// send stop condition
|
||||
i2c_send_stop(I2C(I2C_MASTER_I2C)); // send stop to release bus
|
||||
i2c_send_stop(i2c); // send stop to release bus
|
||||
timer_set_counter(TIM(I2C_MASTER_TIMER), 0); // restart timer
|
||||
timer_clear_flag(TIM(I2C_MASTER_TIMER), TIM_SR_UIF); // clear flag
|
||||
timer_enable_counter(TIM(I2C_MASTER_TIMER)); // enable timer for timeouts
|
||||
while ((I2C_SR2(I2C(I2C_MASTER_I2C)) & I2C_SR2_MSL) && !timer_get_flag(TIM(I2C_MASTER_TIMER), TIM_SR_UIF)); // wait until bus released (non master mode)
|
||||
while ((I2C_SR2(i2c) & I2C_SR2_MSL) && !timer_get_flag(TIM(I2C_MASTER_TIMER), TIM_SR_UIF)); // wait until bus released (non master mode)
|
||||
timer_disable_counter(TIM(I2C_MASTER_TIMER)); // disable timer for timeouts
|
||||
if (timer_get_flag(TIM(I2C_MASTER_TIMER), TIM_SR_UIF)) { // timeout occurred
|
||||
timer_clear_flag(TIM(I2C_MASTER_TIMER), TIM_SR_UIF); // clear flag
|
||||
}
|
||||
}
|
||||
|
||||
bool i2c_master_slave_read(uint8_t slave, uint8_t* data, size_t data_size)
|
||||
bool i2c_master_slave_read(uint32_t i2c, uint8_t slave, uint8_t* data, size_t data_size)
|
||||
{
|
||||
// check I2C peripheral
|
||||
if (I2C1!=i2c && I2C2!=i2c) {
|
||||
while (true);
|
||||
}
|
||||
|
||||
// sanity check
|
||||
if (I2C_SR2(I2C(I2C_MASTER_I2C)) & I2C_SR2_BUSY) { // I2C device is busy
|
||||
if (I2C_SR2(i2c) & I2C_SR2_BUSY) { // I2C device is busy
|
||||
return false;
|
||||
}
|
||||
if (I2C_SR2(I2C(I2C_MASTER_I2C)) & I2C_SR2_MSL) { // I2C device is already in master mode
|
||||
if (I2C_SR2(i2c) & I2C_SR2_MSL) { // I2C device is already in master mode
|
||||
return false;
|
||||
}
|
||||
|
||||
bool success = false; // return if read succeeded
|
||||
|
||||
// send start condition
|
||||
if (!i2c_master_start()) {
|
||||
if (!i2c_master_start(i2c)) {
|
||||
goto error;
|
||||
}
|
||||
// select slave to write
|
||||
if (!i2c_master_select_slave(slave, true)) {
|
||||
if (!i2c_master_select_slave(i2c, slave, true)) {
|
||||
goto error;
|
||||
}
|
||||
// read data
|
||||
if (NULL!=data && data_size>0) {
|
||||
// read data
|
||||
if (!i2c_master_read(data, data_size)) {
|
||||
if (!i2c_master_read(i2c, data, data_size)) {
|
||||
goto error;
|
||||
}
|
||||
}
|
||||
|
||||
success = true;
|
||||
error:
|
||||
i2c_master_stop(); // sent stop condition
|
||||
i2c_master_stop(i2c); // sent stop condition
|
||||
return success;
|
||||
}
|
||||
|
||||
bool i2c_master_slave_write(uint8_t slave, const uint8_t* data, size_t data_size)
|
||||
bool i2c_master_slave_write(uint32_t i2c, uint8_t slave, const uint8_t* data, size_t data_size)
|
||||
{
|
||||
// check I2C peripheral
|
||||
if (I2C1!=i2c && I2C2!=i2c) {
|
||||
while (true);
|
||||
}
|
||||
|
||||
// sanity check
|
||||
if (I2C_SR2(I2C(I2C_MASTER_I2C)) & I2C_SR2_BUSY) { // I2C device is busy
|
||||
if (I2C_SR2(i2c) & I2C_SR2_BUSY) { // I2C device is busy
|
||||
return false;
|
||||
}
|
||||
if (I2C_SR2(I2C(I2C_MASTER_I2C)) & I2C_SR2_MSL) { // I2C device is already in master mode
|
||||
if (I2C_SR2(i2c) & I2C_SR2_MSL) { // I2C device is already in master mode
|
||||
return false;
|
||||
}
|
||||
|
||||
bool success = false; // return if read succeeded
|
||||
|
||||
// send start condition
|
||||
if (!i2c_master_start()) {
|
||||
if (!i2c_master_start(i2c)) {
|
||||
goto error;
|
||||
}
|
||||
// select slave to write
|
||||
if (!i2c_master_select_slave(slave, true)) {
|
||||
if (!i2c_master_select_slave(i2c, slave, true)) {
|
||||
goto error;
|
||||
}
|
||||
// write data
|
||||
if (NULL!=data && data_size>0) {
|
||||
if (!i2c_master_write(data, data_size)) {
|
||||
if (!i2c_master_write(i2c, data, data_size)) {
|
||||
goto error;
|
||||
}
|
||||
}
|
||||
|
||||
success = true;
|
||||
error:
|
||||
i2c_master_stop(); // sent stop condition
|
||||
i2c_master_stop(i2c); // sent stop condition
|
||||
return success;
|
||||
}
|
||||
|
||||
bool i2c_master_address_read(uint8_t slave, const uint8_t* address, size_t address_size, uint8_t* data, size_t data_size)
|
||||
bool i2c_master_address_read(uint32_t i2c, uint8_t slave, const uint8_t* address, size_t address_size, uint8_t* data, size_t data_size)
|
||||
{
|
||||
// check I2C peripheral
|
||||
if (I2C1!=i2c && I2C2!=i2c) {
|
||||
while (true);
|
||||
}
|
||||
|
||||
// sanity check
|
||||
if (I2C_SR2(I2C(I2C_MASTER_I2C)) & I2C_SR2_BUSY) { // I2C device is busy
|
||||
if (I2C_SR2(i2c) & I2C_SR2_BUSY) { // I2C device is busy
|
||||
return false;
|
||||
}
|
||||
if (I2C_SR2(I2C(I2C_MASTER_I2C)) & I2C_SR2_MSL) { // I2C device is already in master mode
|
||||
if (I2C_SR2(i2c) & I2C_SR2_MSL) { // I2C device is already in master mode
|
||||
return false;
|
||||
}
|
||||
|
||||
|
|
@ -316,76 +525,81 @@ bool i2c_master_address_read(uint8_t slave, const uint8_t* address, size_t addre
|
|||
// write address
|
||||
if (NULL!=address && address_size>0) {
|
||||
// send start condition
|
||||
if (!i2c_master_start()) {
|
||||
if (!i2c_master_start(i2c)) {
|
||||
goto error;
|
||||
}
|
||||
// select slave to write
|
||||
if (!i2c_master_select_slave(slave, true)) {
|
||||
if (!i2c_master_select_slave(i2c, slave, true)) {
|
||||
goto error;
|
||||
}
|
||||
// send address
|
||||
if (!i2c_master_write(address, address_size)) {
|
||||
if (!i2c_master_write(i2c, address, address_size)) {
|
||||
goto error;
|
||||
}
|
||||
}
|
||||
// read data
|
||||
if (NULL!=data && data_size>0) {
|
||||
// send re-start condition
|
||||
if (!i2c_master_start()) {
|
||||
if (!i2c_master_start(i2c)) {
|
||||
goto error;
|
||||
}
|
||||
// select slave to read
|
||||
if (!i2c_master_select_slave(slave, false)) {
|
||||
if (!i2c_master_select_slave(i2c, slave, false)) {
|
||||
goto error;
|
||||
}
|
||||
// read data
|
||||
if (!i2c_master_read(data, data_size)) {
|
||||
if (!i2c_master_read(i2c, data, data_size)) {
|
||||
goto error;
|
||||
}
|
||||
}
|
||||
|
||||
success = true;
|
||||
error:
|
||||
i2c_master_stop(); // sent stop condition
|
||||
i2c_master_stop(i2c); // sent stop condition
|
||||
return success;
|
||||
}
|
||||
|
||||
bool i2c_master_address_write(uint8_t slave, const uint8_t* address, size_t address_size, const uint8_t* data, size_t data_size)
|
||||
bool i2c_master_address_write(uint32_t i2c, uint8_t slave, const uint8_t* address, size_t address_size, const uint8_t* data, size_t data_size)
|
||||
{
|
||||
// check I2C peripheral
|
||||
if (I2C1!=i2c && I2C2!=i2c) {
|
||||
while (true);
|
||||
}
|
||||
|
||||
// sanity check
|
||||
if (I2C_SR2(I2C(I2C_MASTER_I2C)) & I2C_SR2_BUSY) { // I2C device is busy
|
||||
if (I2C_SR2(i2c) & I2C_SR2_BUSY) { // I2C device is busy
|
||||
return false;
|
||||
}
|
||||
if (I2C_SR2(I2C(I2C_MASTER_I2C)) & I2C_SR2_MSL) { // I2C device is already in master mode
|
||||
if (I2C_SR2(i2c) & I2C_SR2_MSL) { // I2C device is already in master mode
|
||||
return false;
|
||||
}
|
||||
|
||||
bool success = false; // return if read succeeded
|
||||
|
||||
// send start condition
|
||||
if (!i2c_master_start()) {
|
||||
if (!i2c_master_start(i2c)) {
|
||||
goto error;
|
||||
}
|
||||
// select slave to write
|
||||
if (!i2c_master_select_slave(slave, true)) {
|
||||
if (!i2c_master_select_slave(i2c, slave, true)) {
|
||||
goto error;
|
||||
}
|
||||
// write address
|
||||
if (NULL!=address && address_size>0) {
|
||||
// send address
|
||||
if (!i2c_master_write(address, address_size)) {
|
||||
if (!i2c_master_write(i2c, address, address_size)) {
|
||||
goto error;
|
||||
}
|
||||
}
|
||||
// write data
|
||||
if (NULL!=data && data_size>0) {
|
||||
if (!i2c_master_write(data, data_size)) {
|
||||
if (!i2c_master_write(i2c, data, data_size)) {
|
||||
goto error;
|
||||
}
|
||||
}
|
||||
|
||||
success = true;
|
||||
error:
|
||||
i2c_master_stop(); // sent stop condition
|
||||
i2c_master_stop(i2c); // sent stop condition
|
||||
return success;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -16,55 +16,74 @@
|
|||
* @file i2c_master.h
|
||||
* @author King Kévin <kingkevin@cuvoodoo.info>
|
||||
* @date 2017-2018
|
||||
* @note peripherals used: I2C @ref i2c_master_i2c, timer @ref i2c_master_timer
|
||||
* @note peripherals used: I2C, timer @ref i2c_master_timer
|
||||
* @warning only 7-byte I2C slave addresses are supported
|
||||
*/
|
||||
#pragma once
|
||||
|
||||
/** setup I2C peripheral
|
||||
* @param[in] i2c I2C base address
|
||||
* @param[in] fast use standard (100 kHz) or fast (400 kHz) mode
|
||||
*/
|
||||
void i2c_master_setup(bool fast);
|
||||
void i2c_master_setup(uint32_t i2c, bool fast);
|
||||
/** release I2C peripheral
|
||||
* @param[in] i2c I2C base address
|
||||
*/
|
||||
void i2c_master_release(uint32_t i2c);
|
||||
/** check if SDA and SCL signals are high
|
||||
* @param[in] i2c I2C base address
|
||||
* @return SDA and SCL signals are high
|
||||
*/
|
||||
bool i2c_master_check_signals(uint32_t i2c);
|
||||
/** send start condition
|
||||
* @param[in] i2c I2C base address
|
||||
* @return if start condition was sent successfully (true) or error occurred (false)
|
||||
*/
|
||||
bool i2c_master_start(void);
|
||||
bool i2c_master_start(uint32_t i2c);
|
||||
/** select slave device
|
||||
* @warning a start condition should be sent before this operation
|
||||
* @param[in] i2c I2C base address
|
||||
* @param[in] slave 7-bit I2C address of slave device to select
|
||||
* @param[in] write this transaction will be followed by a read (false) or write (true) operation
|
||||
* @return if slave was selected successfully (true) or error occurred (false)
|
||||
*/
|
||||
bool i2c_master_select_slave(uint8_t slave, bool write);
|
||||
bool i2c_master_select_slave(uint32_t i2c, uint8_t slave, bool write);
|
||||
/** read data
|
||||
* @warning the slave device must be selected before this operation
|
||||
* @param[in] i2c I2C base address
|
||||
* @param[out] data array to store bytes read
|
||||
* @param[in] data_size number of bytes to read
|
||||
*/
|
||||
bool i2c_master_read(uint8_t* data, size_t data_size);
|
||||
bool i2c_master_read(uint32_t i2c, uint8_t* data, size_t data_size);
|
||||
/** write data
|
||||
* @warning the slave device must be selected before this operation
|
||||
* @param[in] i2c I2C base address
|
||||
* @param[in] data array of byte to write to slave
|
||||
* @param[in] data_size number of bytes to write
|
||||
*/
|
||||
bool i2c_master_write(const uint8_t* data, size_t data_size);
|
||||
/** sent stop condition */
|
||||
void i2c_master_stop(void);
|
||||
bool i2c_master_write(uint32_t i2c, const uint8_t* data, size_t data_size);
|
||||
/** sent stop condition
|
||||
* @param[in] i2c I2C base address
|
||||
*/
|
||||
void i2c_master_stop(uint32_t i2c);
|
||||
/** read from date from an I2C slave
|
||||
* @param[in] i2c I2C base address
|
||||
* @param[in] slave 7-bit I2C salve device address to read from
|
||||
* @param[out] data array to store bytes read
|
||||
* @param[in] data_size number of bytes to read
|
||||
* @return if read succeeded
|
||||
*/
|
||||
bool i2c_master_slave_read(uint8_t slave, uint8_t* data, size_t data_size);
|
||||
bool i2c_master_slave_read(uint32_t i2c, uint8_t slave, uint8_t* data, size_t data_size);
|
||||
/** write data to an I2C slave
|
||||
* @param[in] i2c I2C base address
|
||||
* @param[in] slave 7-bit I2C salve device address to write to
|
||||
* @param[in] data array of byte to write to slave
|
||||
* @param[in] data_size number of bytes to write
|
||||
* @return if write succeeded
|
||||
*/
|
||||
bool i2c_master_slave_write(uint8_t slave, const uint8_t* data, size_t data_size);
|
||||
bool i2c_master_slave_write(uint32_t i2c, uint8_t slave, const uint8_t* data, size_t data_size);
|
||||
/** read data at specific address from an I2C memory slave
|
||||
* @param[in] i2c I2C base address
|
||||
* @param[in] slave 7-bit I2C salve device address to read from
|
||||
* @param[in] address memory address of slave to read from
|
||||
* @param[in] address_size address size in bytes
|
||||
|
|
@ -72,8 +91,9 @@ bool i2c_master_slave_write(uint8_t slave, const uint8_t* data, size_t data_size
|
|||
* @param[in] data_size number of bytes to read
|
||||
* @return if read succeeded
|
||||
*/
|
||||
bool i2c_master_address_read(uint8_t slave, const uint8_t* address, size_t address_size, uint8_t* data, size_t data_size);
|
||||
bool i2c_master_address_read(uint32_t i2c, uint8_t slave, const uint8_t* address, size_t address_size, uint8_t* data, size_t data_size);
|
||||
/** write data at specific address on an I2C memory slave
|
||||
* @param[in] i2c I2C base address
|
||||
* @param[in] slave 7-bit I2C salve device address to write to
|
||||
* @param[in] address memory address of slave to write to
|
||||
* @param[in] address_size address size in bytes
|
||||
|
|
@ -81,4 +101,4 @@ bool i2c_master_address_read(uint8_t slave, const uint8_t* address, size_t addre
|
|||
* @param[in] data_size number of bytes to write
|
||||
* @return if write succeeded
|
||||
*/
|
||||
bool i2c_master_address_write(uint8_t slave, const uint8_t* address, size_t address_size, const uint8_t* data, size_t data_size);
|
||||
bool i2c_master_address_write(uint32_t i2c, uint8_t slave, const uint8_t* address, size_t address_size, const uint8_t* data, size_t data_size);
|
||||
|
|
|
|||
Loading…
Reference in New Issue