add stm32f042
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name: STM32F042
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# not all variations added, just as needed
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variations: FxP, GxU
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# not verified: CxT, CxU
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# STM32F042xyz
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# x = pin count: F=20, G=28, K=32, T=36, C=48
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# y = flash size: 4=16KB, 6=32KB
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# z = package: R=TSSOP, T=LQFP, U=UFQFPN, Y=WLCSP
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description: Cortex-M0 USB line MCU
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keywords: MCU, micro-controller
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datasheet: https://www.st.com/resource/en/datasheet/stm32f042g6.pdf
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pinout@FxP: # TSSOP20
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PORTA:
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PA0: 6
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PA1: 7
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PA2: 8
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PA3: 9
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PA4: 10
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PA5: 11
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PA6: 12
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PA7: 13
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PA9-PA11: 17
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PA10-PA12: 18
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PA13-SWDIO: 19
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PA14-SWCLK: 20
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PORTB:
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PB1: 14
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PB8-BOOT0: 1
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PORTF:
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PF0-OSC_IN: 2
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PF1-OSC_OUT: 3
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CTRL:
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NRST: 4
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GROUND:
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VSS: 15
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POWER:
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VDD-VDDIO2: 16
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VDDA: 5
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pinout@GxU: # QFN28
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PORTA:
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PA0: 6
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PA1: 7
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PA2: 8
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PA3: 9
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PA4: 10
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PA5: 11
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PA6: 12
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PA7: 13
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PA9-PA11: 19
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PA10-PA12: 20
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PA13-SWDIO: 21
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PA14-SWCLK: 22
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PA15: 23
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PORTB:
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PB0: 14
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PB1: 15
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PB3: 24
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PB4: 25
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PB5: 26
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PB6: 27
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PB7: 28
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PB8-BOOT0: 1
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PORTF:
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PF0-OSC_IN: 2
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PF1-OSC_OUT: 3
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CTRL:
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NRST: 4
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GROUND:
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VSS: 16
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POWER:
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VDD: 17
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VDDIO2: 18
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VDDA: 5
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pinout@CxT: # LQFP48
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PORTA:
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PA0-WKUP: 10
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PA1: 11
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PA2: 12
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PA3: 13
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PA4: 14
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PA5: 15
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PA6: 16
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PA7: 17
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PA8: 29
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PA9: 30
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PA10: 31
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PA11: 32
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PA12: 33
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PA13: 34
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PA14: 37
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PA15: 38
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PORTB:
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PB0: 18
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PB1: 19
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PB2: 20
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PB3: 39
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PB4: 40
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PB5: 41
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PB6: 42
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PB7: 43
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PB8: 45
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PB9: 46
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PB10: 21
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PB11: 22
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PB12: 25
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PB13: 26
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PB14: 27
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PB15: 28
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PORTC:
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PC13-TAMPER-RTC: 2
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PC14-OSC32_IN: 3
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PC15-OSC32_OUT: 4
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CTRL:
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BOOT0: 44
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OSC_IN: 5
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OSC_OUT: 6
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NRST: 7
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GROUND:
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VSS: 23, 35, 47
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VSSA: 8
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POWER:
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VDD: 24, 36, 48
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VDDA: 9
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VBAT: 1
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pinout@CxU: # QFN48
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PORTA:
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PA0-WKUP: 10
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PA1: 11
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PA2: 12
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PA3: 13
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PA4: 14
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PA5: 15
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PA6: 16
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PA7: 17
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PA8: 29
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PA9: 30
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PA10: 31
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PA11: 32
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PA12: 33
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PA13: 34
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PA14: 37
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PA15: 38
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PORTB:
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PB0: 18
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PB1: 19
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PB2: 20
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PB3: 39
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PB4: 40
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PB5: 41
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PB6: 42
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PB7: 43
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PB8: 45
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PB9: 46
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PB10: 21
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PB11: 22
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PB12: 25
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PB13: 26
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PB14: 27
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PB15: 28
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PORTC:
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PC13-TAMPER-RTC: 2
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PC14-OSC32_IN: 3
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PC15-OSC32_OUT: 4
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CTRL:
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BOOT0: 44
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OSC_IN: 5
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OSC_OUT: 6
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NRST: 7
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GROUND:
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VSS: 23, 35, 47, 49
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VSSA: 8
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POWER:
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VDD: 24, 36, 48
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VDDA: 9
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VBAT: 1
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properties:
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in: NRST, BOOT0
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bidir: PORTA, PORTB, PORTC, PORTF
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power: VDD, VDDA, VDDIO2, VBAT
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ground: VSS, VSSA
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inverted: NRST
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schematic:
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symbol: IC
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left: PORTA, PORTF
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right: PORTB, PORTC, CTRL
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top: POWER
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bottom: GROUND
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housing@FxP: # TSSOP20
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suffix: FxP
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pattern: SOP
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bodyWidth: 4.3-4.5 # E1
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bodyLength: 6.4-6.6 # D
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height: 1.2 # A
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leadWidth: 0.19-0.30 # b
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leadLength: 0.45-0.75 # L
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leadSpan: 6.2-6.6 # E
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pitch: 0.65 # e
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leadCount: 20
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housing@GxU: # QFN28
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suffix: GxU
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pattern: QFN
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bodyWidth: 3.9-4.1 # D
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bodyLength: 3.9-4.1 # E
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height: 0.5-0.6 # A
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leadWidth: 0.2-0.3 # b
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leadLength: 0.3-0.5 # L
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pitch: 0.5 # e
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leadCount: 28
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rowCount: 7
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columnCount: 7
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# no tab
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housing@CxU: # QFN48
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suffix: CxU
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pattern: QFN
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bodyWidth: 7.0
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bodyLength: 7.0
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height: 0.85
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leadWidth: 0.25
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leadLength: 0.4
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pitch: 0.5
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leadCount: 48
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tabWidth: 5.5
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tabLength: 5.5
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tabPosition: 0.0, 0.0
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housing@CxT: # LQFP48
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suffix: CxT
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pattern: QFP
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bodyWidth: 7.0
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bodyLength: 7.0
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height: 1.5
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leadWidth: 0.2
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leadLength: 0.6
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leadSpan: 9.0
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pitch: 0.5
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leadCount: 48
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rowCount: 12
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columnCount: 12
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