469 lines
21 KiB
C
469 lines
21 KiB
C
/*
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* Copyright 2023 NXP
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* All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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/***********************************************************************************************************************
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* This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
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* will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
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**********************************************************************************************************************/
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/*
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* How to setup clock using clock driver functions:
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*
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* 1. Setup clock sources.
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*
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* 2. Set up wait states of the flash.
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*
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* 3. Set up all dividers.
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*
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* 4. Set up all selectors to provide selected clocks.
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*
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*/
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/* clang-format off */
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/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
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!!GlobalInfo
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product: Clocks v12.0
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processor: MCXA153
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package_id: MCXA153VLH
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mcu_data: ksdk2_0
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processor_version: 0.13.0
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* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
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/* clang-format on */
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#include "fsl_clock.h"
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#include "clock_config.h"
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#include "fsl_spc.h"
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/*******************************************************************************
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* Definitions
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******************************************************************************/
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/*******************************************************************************
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* Variables
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******************************************************************************/
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/* System clock frequency. */
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//uint32_t SystemCoreClock;
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/*******************************************************************************
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************************ BOARD_InitBootClocks function ************************
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******************************************************************************/
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void BOARD_InitBootClocks(void)
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{
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BOARD_BootClockFRO96M();
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}
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/*******************************************************************************
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******************** Configuration BOARD_BootClockFRO12M **********************
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******************************************************************************/
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/* clang-format off */
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/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
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!!Configuration
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name: BOARD_BootClockFRO12M
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outputs:
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- {id: CLK_1M_clock.outFreq, value: 1 MHz}
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- {id: CPU_clock.outFreq, value: 12 MHz}
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- {id: FRO_12M_clock.outFreq, value: 12 MHz}
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- {id: MAIN_clock.outFreq, value: 12 MHz}
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- {id: Slow_clock.outFreq, value: 3 MHz}
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- {id: System_clock.outFreq, value: 12 MHz}
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settings:
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- {id: SCGMode, value: SIRC}
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- {id: FRO_HF_PERIPHERALS_EN_CFG, value: Disabled}
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- {id: MRCC.OSTIMERCLKSEL.sel, value: VBAT.CLK16K_1}
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- {id: SCG.SCSSEL.sel, value: SCG.SIRC}
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- {id: SCG_FIRCCSR_FIRCEN_CFG, value: Disabled}
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* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
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/* clang-format on */
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/*******************************************************************************
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* Variables for BOARD_BootClockFRO12M configuration
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******************************************************************************/
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/*******************************************************************************
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* Code for BOARD_BootClockFRO12M configuration
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******************************************************************************/
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void BOARD_BootClockFRO12M(void)
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{
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uint32_t coreFreq;
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spc_active_mode_core_ldo_option_t ldoOption;
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spc_sram_voltage_config_t sramOption;
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/* Get the CPU Core frequency */
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coreFreq = CLOCK_GetCoreSysClkFreq();
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/* The flow of increasing voltage and frequency */
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if (coreFreq <= BOARD_BOOTCLOCKFRO12M_CORE_CLOCK) {
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/* Set the LDO_CORE VDD regulator level */
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ldoOption.CoreLDOVoltage = kSPC_CoreLDO_MidDriveVoltage;
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ldoOption.CoreLDODriveStrength = kSPC_CoreLDO_NormalDriveStrength;
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(void)SPC_SetActiveModeCoreLDORegulatorConfig(SPC0, &ldoOption);
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/* Configure Flash to support different voltage level and frequency */
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FMU0->FCTRL = (FMU0->FCTRL & ~((uint32_t)FMU_FCTRL_RWSC_MASK)) | (FMU_FCTRL_RWSC(0x0U));
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/* Specifies the operating voltage for the SRAM's read/write timing margin */
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sramOption.operateVoltage = kSPC_sramOperateAt1P0V;
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sramOption.requestVoltageUpdate = true;
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(void)SPC_SetSRAMOperateVoltage(SPC0, &sramOption);
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}
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CLOCK_SetupFRO12MClocking(); /*!< Setup FRO12M clock */
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CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /* !< Switch MAIN_CLK to FRO12M */
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/* The flow of decreasing voltage and frequency */
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if (coreFreq > BOARD_BOOTCLOCKFRO12M_CORE_CLOCK) {
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/* Configure Flash to support different voltage level and frequency */
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FMU0->FCTRL = (FMU0->FCTRL & ~((uint32_t)FMU_FCTRL_RWSC_MASK)) | (FMU_FCTRL_RWSC(0x0U));
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/* Specifies the operating voltage for the SRAM's read/write timing margin */
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sramOption.operateVoltage = kSPC_sramOperateAt1P0V;
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sramOption.requestVoltageUpdate = true;
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(void)SPC_SetSRAMOperateVoltage(SPC0, &sramOption);
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/* Set the LDO_CORE VDD regulator level */
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ldoOption.CoreLDOVoltage = kSPC_CoreLDO_MidDriveVoltage;
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ldoOption.CoreLDODriveStrength = kSPC_CoreLDO_NormalDriveStrength;
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(void)SPC_SetActiveModeCoreLDORegulatorConfig(SPC0, &ldoOption);
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}
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/*!< Set up clock selectors - Attach clocks to the peripheries */
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/*!< Set up dividers */
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CLOCK_SetClockDiv(kCLOCK_DivAHBCLK, 1U); /* !< Set AHBCLKDIV divider to value 1 */
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/* Set SystemCoreClock variable */
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SystemCoreClock = BOARD_BOOTCLOCKFRO12M_CORE_CLOCK;
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}
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/*******************************************************************************
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******************** Configuration BOARD_BootClockFRO24M **********************
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******************************************************************************/
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/* clang-format off */
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/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
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!!Configuration
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name: BOARD_BootClockFRO24M
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outputs:
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- {id: CLK_1M_clock.outFreq, value: 1 MHz}
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- {id: CLK_48M_clock.outFreq, value: 48 MHz}
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- {id: CPU_clock.outFreq, value: 24 MHz}
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- {id: FRO_12M_clock.outFreq, value: 12 MHz}
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- {id: FRO_HF_DIV_clock.outFreq, value: 48 MHz}
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- {id: FRO_HF_clock.outFreq, value: 48 MHz}
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- {id: MAIN_clock.outFreq, value: 48 MHz}
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- {id: Slow_clock.outFreq, value: 6 MHz}
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- {id: System_clock.outFreq, value: 24 MHz}
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settings:
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- {id: MRCC.OSTIMERCLKSEL.sel, value: VBAT.CLK16K_1}
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- {id: SYSCON.AHBCLKDIV.scale, value: '2', locked: true}
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* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
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/* clang-format on */
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/*******************************************************************************
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* Variables for BOARD_BootClockFRO24M configuration
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******************************************************************************/
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/*******************************************************************************
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* Code for BOARD_BootClockFRO24M configuration
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******************************************************************************/
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void BOARD_BootClockFRO24M(void)
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{
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uint32_t coreFreq;
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spc_active_mode_core_ldo_option_t ldoOption;
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spc_sram_voltage_config_t sramOption;
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/* Get the CPU Core frequency */
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coreFreq = CLOCK_GetCoreSysClkFreq();
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/* The flow of increasing voltage and frequency */
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if (coreFreq <= BOARD_BOOTCLOCKFRO24M_CORE_CLOCK) {
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/* Set the LDO_CORE VDD regulator level */
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ldoOption.CoreLDOVoltage = kSPC_CoreLDO_MidDriveVoltage;
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ldoOption.CoreLDODriveStrength = kSPC_CoreLDO_NormalDriveStrength;
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(void)SPC_SetActiveModeCoreLDORegulatorConfig(SPC0, &ldoOption);
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/* Configure Flash to support different voltage level and frequency */
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FMU0->FCTRL = (FMU0->FCTRL & ~((uint32_t)FMU_FCTRL_RWSC_MASK)) | (FMU_FCTRL_RWSC(0x0U));
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/* Specifies the operating voltage for the SRAM's read/write timing margin */
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sramOption.operateVoltage = kSPC_sramOperateAt1P0V;
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sramOption.requestVoltageUpdate = true;
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(void)SPC_SetSRAMOperateVoltage(SPC0, &sramOption);
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}
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CLOCK_SetupFROHFClocking(48000000U); /*!< Enable FRO HF(48MHz) output */
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CLOCK_SetupFRO12MClocking(); /*!< Setup FRO12M clock */
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CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK); /* !< Switch MAIN_CLK to FRO_HF */
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/* The flow of decreasing voltage and frequency */
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if (coreFreq > BOARD_BOOTCLOCKFRO24M_CORE_CLOCK) {
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/* Configure Flash to support different voltage level and frequency */
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FMU0->FCTRL = (FMU0->FCTRL & ~((uint32_t)FMU_FCTRL_RWSC_MASK)) | (FMU_FCTRL_RWSC(0x0U));
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/* Specifies the operating voltage for the SRAM's read/write timing margin */
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sramOption.operateVoltage = kSPC_sramOperateAt1P0V;
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sramOption.requestVoltageUpdate = true;
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(void)SPC_SetSRAMOperateVoltage(SPC0, &sramOption);
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/* Set the LDO_CORE VDD regulator level */
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ldoOption.CoreLDOVoltage = kSPC_CoreLDO_MidDriveVoltage;
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ldoOption.CoreLDODriveStrength = kSPC_CoreLDO_NormalDriveStrength;
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(void)SPC_SetActiveModeCoreLDORegulatorConfig(SPC0, &ldoOption);
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}
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/*!< Set up clock selectors - Attach clocks to the peripheries */
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/*!< Set up dividers */
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CLOCK_SetClockDiv(kCLOCK_DivAHBCLK, 2U); /* !< Set AHBCLKDIV divider to value 2 */
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CLOCK_SetClockDiv(kCLOCK_DivFRO_HF_DIV, 1U); /* !< Set FROHFDIV divider to value 1 */
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/* Set SystemCoreClock variable */
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SystemCoreClock = BOARD_BOOTCLOCKFRO24M_CORE_CLOCK;
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}
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/*******************************************************************************
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******************** Configuration BOARD_BootClockFRO48M **********************
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******************************************************************************/
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/* clang-format off */
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/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
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!!Configuration
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name: BOARD_BootClockFRO48M
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outputs:
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- {id: CLK_1M_clock.outFreq, value: 1 MHz}
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- {id: CLK_48M_clock.outFreq, value: 48 MHz}
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- {id: CPU_clock.outFreq, value: 48 MHz}
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- {id: FRO_12M_clock.outFreq, value: 12 MHz}
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- {id: FRO_HF_DIV_clock.outFreq, value: 48 MHz}
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- {id: FRO_HF_clock.outFreq, value: 48 MHz}
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- {id: MAIN_clock.outFreq, value: 48 MHz}
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- {id: Slow_clock.outFreq, value: 12 MHz}
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- {id: System_clock.outFreq, value: 48 MHz}
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settings:
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- {id: MRCC.OSTIMERCLKSEL.sel, value: VBAT.CLK16K_1}
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* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
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/* clang-format on */
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/*******************************************************************************
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* Variables for BOARD_BootClockFRO48M configuration
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******************************************************************************/
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/*******************************************************************************
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* Code for BOARD_BootClockFRO48M configuration
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******************************************************************************/
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void BOARD_BootClockFRO48M(void)
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{
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uint32_t coreFreq;
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spc_active_mode_core_ldo_option_t ldoOption;
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spc_sram_voltage_config_t sramOption;
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/* Get the CPU Core frequency */
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coreFreq = CLOCK_GetCoreSysClkFreq();
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/* The flow of increasing voltage and frequency */
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if (coreFreq <= BOARD_BOOTCLOCKFRO48M_CORE_CLOCK) {
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/* Set the LDO_CORE VDD regulator level */
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ldoOption.CoreLDOVoltage = kSPC_CoreLDO_MidDriveVoltage;
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ldoOption.CoreLDODriveStrength = kSPC_CoreLDO_NormalDriveStrength;
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(void)SPC_SetActiveModeCoreLDORegulatorConfig(SPC0, &ldoOption);
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/* Configure Flash to support different voltage level and frequency */
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FMU0->FCTRL = (FMU0->FCTRL & ~((uint32_t)FMU_FCTRL_RWSC_MASK)) | (FMU_FCTRL_RWSC(0x1U));
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/* Specifies the operating voltage for the SRAM's read/write timing margin */
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sramOption.operateVoltage = kSPC_sramOperateAt1P0V;
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sramOption.requestVoltageUpdate = true;
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(void)SPC_SetSRAMOperateVoltage(SPC0, &sramOption);
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}
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CLOCK_SetupFROHFClocking(48000000U); /*!< Enable FRO HF(48MHz) output */
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CLOCK_SetupFRO12MClocking(); /*!< Setup FRO12M clock */
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CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK); /* !< Switch MAIN_CLK to FRO_HF */
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/* The flow of decreasing voltage and frequency */
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if (coreFreq > BOARD_BOOTCLOCKFRO48M_CORE_CLOCK) {
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/* Configure Flash to support different voltage level and frequency */
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FMU0->FCTRL = (FMU0->FCTRL & ~((uint32_t)FMU_FCTRL_RWSC_MASK)) | (FMU_FCTRL_RWSC(0x1U));
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/* Specifies the operating voltage for the SRAM's read/write timing margin */
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sramOption.operateVoltage = kSPC_sramOperateAt1P0V;
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sramOption.requestVoltageUpdate = true;
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(void)SPC_SetSRAMOperateVoltage(SPC0, &sramOption);
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/* Set the LDO_CORE VDD regulator level */
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ldoOption.CoreLDOVoltage = kSPC_CoreLDO_MidDriveVoltage;
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ldoOption.CoreLDODriveStrength = kSPC_CoreLDO_NormalDriveStrength;
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(void)SPC_SetActiveModeCoreLDORegulatorConfig(SPC0, &ldoOption);
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}
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/*!< Set up clock selectors - Attach clocks to the peripheries */
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/*!< Set up dividers */
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CLOCK_SetClockDiv(kCLOCK_DivAHBCLK, 1U); /* !< Set AHBCLKDIV divider to value 1 */
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CLOCK_SetClockDiv(kCLOCK_DivFRO_HF_DIV, 1U); /* !< Set FROHFDIV divider to value 1 */
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/* Set SystemCoreClock variable */
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SystemCoreClock = BOARD_BOOTCLOCKFRO48M_CORE_CLOCK;
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}
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/*******************************************************************************
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******************** Configuration BOARD_BootClockFRO64M **********************
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******************************************************************************/
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/* clang-format off */
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/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
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!!Configuration
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name: BOARD_BootClockFRO64M
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outputs:
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- {id: CLK_1M_clock.outFreq, value: 1 MHz}
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- {id: CLK_48M_clock.outFreq, value: 48 MHz}
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- {id: CPU_clock.outFreq, value: 64 MHz}
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- {id: FRO_12M_clock.outFreq, value: 12 MHz}
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- {id: FRO_HF_DIV_clock.outFreq, value: 64 MHz}
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- {id: FRO_HF_clock.outFreq, value: 64 MHz}
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- {id: MAIN_clock.outFreq, value: 64 MHz}
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- {id: Slow_clock.outFreq, value: 16 MHz}
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- {id: System_clock.outFreq, value: 64 MHz}
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settings:
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- {id: VDD_CORE, value: voltage_1v1}
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- {id: MRCC.FROHFDIV.scale, value: '1', locked: true}
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- {id: MRCC.OSTIMERCLKSEL.sel, value: VBAT.CLK16K_1}
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- {id: SYSCON.AHBCLKDIV.scale, value: '1', locked: true}
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sources:
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- {id: SCG.FIRC.outFreq, value: 64 MHz}
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* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
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/* clang-format on */
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/*******************************************************************************
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* Variables for BOARD_BootClockFRO64M configuration
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******************************************************************************/
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/*******************************************************************************
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* Code for BOARD_BootClockFRO64M configuration
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******************************************************************************/
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void BOARD_BootClockFRO64M(void)
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{
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uint32_t coreFreq;
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spc_active_mode_core_ldo_option_t ldoOption;
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spc_sram_voltage_config_t sramOption;
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/* Get the CPU Core frequency */
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coreFreq = CLOCK_GetCoreSysClkFreq();
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/* The flow of increasing voltage and frequency */
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if (coreFreq <= BOARD_BOOTCLOCKFRO64M_CORE_CLOCK) {
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/* Set the LDO_CORE VDD regulator level */
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ldoOption.CoreLDOVoltage = kSPC_CoreLDO_NormalVoltage;
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ldoOption.CoreLDODriveStrength = kSPC_CoreLDO_NormalDriveStrength;
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(void)SPC_SetActiveModeCoreLDORegulatorConfig(SPC0, &ldoOption);
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/* Configure Flash to support different voltage level and frequency */
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FMU0->FCTRL = (FMU0->FCTRL & ~((uint32_t)FMU_FCTRL_RWSC_MASK)) | (FMU_FCTRL_RWSC(0x1U));
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/* Specifies the operating voltage for the SRAM's read/write timing margin */
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sramOption.operateVoltage = kSPC_sramOperateAt1P1V;
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sramOption.requestVoltageUpdate = true;
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(void)SPC_SetSRAMOperateVoltage(SPC0, &sramOption);
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}
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CLOCK_SetupFROHFClocking(64000000U); /*!< Enable FRO HF(64MHz) output */
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CLOCK_SetupFRO12MClocking(); /*!< Setup FRO12M clock */
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CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK); /* !< Switch MAIN_CLK to FRO_HF */
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/* The flow of decreasing voltage and frequency */
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if (coreFreq > BOARD_BOOTCLOCKFRO64M_CORE_CLOCK) {
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/* Configure Flash to support different voltage level and frequency */
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FMU0->FCTRL = (FMU0->FCTRL & ~((uint32_t)FMU_FCTRL_RWSC_MASK)) | (FMU_FCTRL_RWSC(0x1U));
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/* Specifies the operating voltage for the SRAM's read/write timing margin */
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sramOption.operateVoltage = kSPC_sramOperateAt1P1V;
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sramOption.requestVoltageUpdate = true;
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(void)SPC_SetSRAMOperateVoltage(SPC0, &sramOption);
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/* Set the LDO_CORE VDD regulator level */
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ldoOption.CoreLDOVoltage = kSPC_CoreLDO_NormalVoltage;
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ldoOption.CoreLDODriveStrength = kSPC_CoreLDO_NormalDriveStrength;
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(void)SPC_SetActiveModeCoreLDORegulatorConfig(SPC0, &ldoOption);
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}
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/*!< Set up clock selectors - Attach clocks to the peripheries */
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/*!< Set up dividers */
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CLOCK_SetClockDiv(kCLOCK_DivAHBCLK, 1U); /* !< Set AHBCLKDIV divider to value 1 */
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CLOCK_SetClockDiv(kCLOCK_DivFRO_HF_DIV, 1U); /* !< Set FROHFDIV divider to value 1 */
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/* Set SystemCoreClock variable */
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SystemCoreClock = BOARD_BOOTCLOCKFRO64M_CORE_CLOCK;
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}
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/*******************************************************************************
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******************** Configuration BOARD_BootClockFRO96M **********************
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******************************************************************************/
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/* clang-format off */
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/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
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!!Configuration
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name: BOARD_BootClockFRO96M
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called_from_default_init: true
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outputs:
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- {id: CLK_1M_clock.outFreq, value: 1 MHz}
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- {id: CLK_48M_clock.outFreq, value: 48 MHz}
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- {id: CPU_clock.outFreq, value: 96 MHz}
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- {id: FRO_12M_clock.outFreq, value: 12 MHz}
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- {id: FRO_HF_DIV_clock.outFreq, value: 96 MHz}
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- {id: FRO_HF_clock.outFreq, value: 96 MHz}
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- {id: MAIN_clock.outFreq, value: 96 MHz}
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- {id: Slow_clock.outFreq, value: 24 MHz}
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- {id: System_clock.outFreq, value: 96 MHz}
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settings:
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- {id: VDD_CORE, value: voltage_1v1}
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- {id: CLKOUTDIV_HALT, value: Enable}
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- {id: MRCC.FROHFDIV.scale, value: '1', locked: true}
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- {id: MRCC.OSTIMERCLKSEL.sel, value: VBAT.CLK16K_1}
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- {id: SYSCON.AHBCLKDIV.scale, value: '1', locked: true}
|
|
sources:
|
|
- {id: SCG.FIRC.outFreq, value: 96 MHz}
|
|
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
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|
/* clang-format on */
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|
|
|
/*******************************************************************************
|
|
* Variables for BOARD_BootClockFRO96M configuration
|
|
******************************************************************************/
|
|
/*******************************************************************************
|
|
* Code for BOARD_BootClockFRO96M configuration
|
|
******************************************************************************/
|
|
void BOARD_BootClockFRO96M(void)
|
|
{
|
|
uint32_t coreFreq;
|
|
spc_active_mode_core_ldo_option_t ldoOption;
|
|
spc_sram_voltage_config_t sramOption;
|
|
|
|
/* Get the CPU Core frequency */
|
|
coreFreq = CLOCK_GetCoreSysClkFreq();
|
|
|
|
/* The flow of increasing voltage and frequency */
|
|
if (coreFreq <= BOARD_BOOTCLOCKFRO96M_CORE_CLOCK) {
|
|
/* Set the LDO_CORE VDD regulator level */
|
|
ldoOption.CoreLDOVoltage = kSPC_CoreLDO_NormalVoltage;
|
|
ldoOption.CoreLDODriveStrength = kSPC_CoreLDO_NormalDriveStrength;
|
|
(void)SPC_SetActiveModeCoreLDORegulatorConfig(SPC0, &ldoOption);
|
|
/* Configure Flash to support different voltage level and frequency */
|
|
FMU0->FCTRL = (FMU0->FCTRL & ~((uint32_t)FMU_FCTRL_RWSC_MASK)) | (FMU_FCTRL_RWSC(0x2U));
|
|
/* Specifies the operating voltage for the SRAM's read/write timing margin */
|
|
sramOption.operateVoltage = kSPC_sramOperateAt1P1V;
|
|
sramOption.requestVoltageUpdate = true;
|
|
(void)SPC_SetSRAMOperateVoltage(SPC0, &sramOption);
|
|
}
|
|
|
|
CLOCK_SetupFROHFClocking(96000000U); /*!< Enable FRO HF(96MHz) output */
|
|
|
|
CLOCK_SetupFRO12MClocking(); /*!< Setup FRO12M clock */
|
|
|
|
CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK); /* !< Switch MAIN_CLK to FRO_HF */
|
|
|
|
/* The flow of decreasing voltage and frequency */
|
|
if (coreFreq > BOARD_BOOTCLOCKFRO96M_CORE_CLOCK) {
|
|
/* Configure Flash to support different voltage level and frequency */
|
|
FMU0->FCTRL = (FMU0->FCTRL & ~((uint32_t)FMU_FCTRL_RWSC_MASK)) | (FMU_FCTRL_RWSC(0x2U));
|
|
/* Specifies the operating voltage for the SRAM's read/write timing margin */
|
|
sramOption.operateVoltage = kSPC_sramOperateAt1P1V;
|
|
sramOption.requestVoltageUpdate = true;
|
|
(void)SPC_SetSRAMOperateVoltage(SPC0, &sramOption);
|
|
/* Set the LDO_CORE VDD regulator level */
|
|
ldoOption.CoreLDOVoltage = kSPC_CoreLDO_NormalVoltage;
|
|
ldoOption.CoreLDODriveStrength = kSPC_CoreLDO_NormalDriveStrength;
|
|
(void)SPC_SetActiveModeCoreLDORegulatorConfig(SPC0, &ldoOption);
|
|
}
|
|
|
|
/*!< Set up clock selectors - Attach clocks to the peripheries */
|
|
|
|
/*!< Set up dividers */
|
|
CLOCK_SetClockDiv(kCLOCK_DivAHBCLK, 1U); /* !< Set AHBCLKDIV divider to value 1 */
|
|
CLOCK_SetClockDiv(kCLOCK_DivFRO_HF_DIV, 1U); /* !< Set FROHFDIV divider to value 1 */
|
|
|
|
/* Set SystemCoreClock variable */
|
|
SystemCoreClock = BOARD_BOOTCLOCKFRO96M_CORE_CLOCK;
|
|
}
|