384 lines
15 KiB
ArmAsm
384 lines
15 KiB
ArmAsm
/* ---------------------------------------------------------------------------------------*/
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/* @file: startup_MKL25Z4.s */
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/* @purpose: CMSIS Cortex-M0P Core Device Startup File */
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/* MKL25Z4 */
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/* @version: 2.5 */
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/* @date: 2015-2-19 */
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/* @build: b170112 */
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/* ---------------------------------------------------------------------------------------*/
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/* */
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/* Copyright (c) 1997 - 2016, Freescale Semiconductor, Inc. */
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/* Copyright 2016 - 2017 NXP */
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/* Redistribution and use in source and binary forms, with or without modification, */
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/* are permitted provided that the following conditions are met: */
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/* */
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/* o Redistributions of source code must retain the above copyright notice, this list */
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/* of conditions and the following disclaimer. */
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/* */
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/* o Redistributions in binary form must reproduce the above copyright notice, this */
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/* list of conditions and the following disclaimer in the documentation and/or */
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/* other materials provided with the distribution. */
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/* */
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/* o Neither the name of the copyright holder nor the names of its */
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/* contributors may be used to endorse or promote products derived from this */
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/* software without specific prior written permission. */
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/* */
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/* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND */
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/* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED */
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/* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE */
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/* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR */
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/* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES */
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/* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; */
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/* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON */
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/* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT */
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/* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS */
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/* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
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/*****************************************************************************/
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/* Version: GCC for ARM Embedded Processors */
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/*****************************************************************************/
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.syntax unified
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.arch armv6-m
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.section .isr_vector, "a"
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.align 2
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.globl __isr_vector
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__isr_vector:
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.long __StackTop /* Top of Stack */
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.long Reset_Handler /* Reset Handler */
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.long NMI_Handler /* NMI Handler*/
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.long HardFault_Handler /* Hard Fault Handler*/
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.long 0 /* Reserved*/
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.long 0 /* Reserved*/
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.long 0 /* Reserved*/
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.long 0 /* Reserved*/
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.long 0 /* Reserved*/
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.long 0 /* Reserved*/
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.long 0 /* Reserved*/
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.long SVC_Handler /* SVCall Handler*/
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.long 0 /* Reserved*/
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.long 0 /* Reserved*/
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.long PendSV_Handler /* PendSV Handler*/
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.long SysTick_Handler /* SysTick Handler*/
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/* External Interrupts*/
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.long DMA0_IRQHandler /* DMA channel 0 transfer complete*/
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.long DMA1_IRQHandler /* DMA channel 1 transfer complete*/
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.long DMA2_IRQHandler /* DMA channel 2 transfer complete*/
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.long DMA3_IRQHandler /* DMA channel 3 transfer complete*/
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.long Reserved20_IRQHandler /* Reserved interrupt*/
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.long FTFA_IRQHandler /* Command complete and read collision*/
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.long LVD_LVW_IRQHandler /* Low-voltage detect, low-voltage warning*/
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.long LLWU_IRQHandler /* Low leakage wakeup Unit*/
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.long I2C0_IRQHandler /* I2C0 interrupt*/
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.long I2C1_IRQHandler /* I2C1 interrupt*/
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.long SPI0_IRQHandler /* SPI0 single interrupt vector for all sources*/
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.long SPI1_IRQHandler /* SPI1 single interrupt vector for all sources*/
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.long UART0_IRQHandler /* UART0 status and error*/
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.long UART1_IRQHandler /* UART1 status and error*/
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.long UART2_IRQHandler /* UART2 status and error*/
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.long ADC0_IRQHandler /* ADC0 interrupt*/
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.long CMP0_IRQHandler /* CMP0 interrupt*/
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.long TPM0_IRQHandler /* TPM0 single interrupt vector for all sources*/
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.long TPM1_IRQHandler /* TPM1 single interrupt vector for all sources*/
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.long TPM2_IRQHandler /* TPM2 single interrupt vector for all sources*/
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.long RTC_IRQHandler /* RTC alarm*/
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.long RTC_Seconds_IRQHandler /* RTC seconds*/
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.long PIT_IRQHandler /* PIT interrupt*/
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.long Reserved39_IRQHandler /* Reserved interrupt*/
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.long USB0_IRQHandler /* USB0 interrupt*/
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.long DAC0_IRQHandler /* DAC0 interrupt*/
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.long TSI0_IRQHandler /* TSI0 interrupt*/
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.long MCG_IRQHandler /* MCG interrupt*/
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.long LPTMR0_IRQHandler /* LPTMR0 interrupt*/
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.long Reserved45_IRQHandler /* Reserved interrupt*/
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.long PORTA_IRQHandler /* PORTA Pin detect*/
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.long PORTD_IRQHandler /* PORTD Pin detect*/
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.size __isr_vector, . - __isr_vector
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/* Flash Configuration */
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.section .FlashConfig, "a"
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.long 0xFFFFFFFF
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.long 0xFFFFFFFF
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.long 0xFFFFFFFF
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.long 0xFFFFFFFE
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.text
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.thumb
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/* Reset Handler */
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.thumb_func
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.align 2
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.globl Reset_Handler
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.weak Reset_Handler
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.type Reset_Handler, %function
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Reset_Handler:
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cpsid i /* Mask interrupts */
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.equ VTOR, 0xE000ED08
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ldr r0, =VTOR
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ldr r1, =__isr_vector
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str r1, [r0]
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ldr r2, [r1]
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msr msp, r2
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#ifndef __NO_SYSTEM_INIT
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ldr r0,=SystemInit
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blx r0
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#endif
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/* Loop to copy data from read only memory to RAM. The ranges
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* of copy from/to are specified by following symbols evaluated in
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* linker script.
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* __etext: End of code section, i.e., begin of data sections to copy from.
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* __data_start__/__data_end__: RAM address range that data should be
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* copied to. Both must be aligned to 4 bytes boundary. */
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ldr r1, =__etext
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ldr r2, =__data_start__
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ldr r3, =__data_end__
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subs r3, r2
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ble .LC0
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.LC1:
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subs r3, 4
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ldr r0, [r1,r3]
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str r0, [r2,r3]
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bgt .LC1
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.LC0:
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#ifdef __STARTUP_CLEAR_BSS
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/* This part of work usually is done in C library startup code. Otherwise,
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* define this macro to enable it in this startup.
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*
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* Loop to zero out BSS section, which uses following symbols
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* in linker script:
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* __bss_start__: start of BSS section. Must align to 4
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* __bss_end__: end of BSS section. Must align to 4
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*/
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ldr r1, =__bss_start__
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ldr r2, =__bss_end__
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subs r2, r1
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ble .LC3
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movs r0, 0
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.LC2:
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str r0, [r1, r2]
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subs r2, 4
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bge .LC2
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.LC3:
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#endif
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cpsie i /* Unmask interrupts */
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#ifndef __START
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#define __START _start
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#endif
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#ifndef __ATOLLIC__
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ldr r0,=__START
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blx r0
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#else
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ldr r0,=__libc_init_array
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blx r0
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ldr r0,=main
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bx r0
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#endif
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.pool
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.size Reset_Handler, . - Reset_Handler
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.align 1
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.thumb_func
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.weak DefaultISR
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.type DefaultISR, %function
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DefaultISR:
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ldr r0, =DefaultISR
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bx r0
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.size DefaultISR, . - DefaultISR
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.align 1
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.thumb_func
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.weak NMI_Handler
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.type NMI_Handler, %function
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NMI_Handler:
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ldr r0,=NMI_Handler
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bx r0
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.size NMI_Handler, . - NMI_Handler
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.align 1
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.thumb_func
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.weak HardFault_Handler
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.type HardFault_Handler, %function
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HardFault_Handler:
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ldr r0,=HardFault_Handler
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bx r0
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.size HardFault_Handler, . - HardFault_Handler
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.align 1
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.thumb_func
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.weak SVC_Handler
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.type SVC_Handler, %function
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SVC_Handler:
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ldr r0,=SVC_Handler
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bx r0
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.size SVC_Handler, . - SVC_Handler
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.align 1
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.thumb_func
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.weak PendSV_Handler
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.type PendSV_Handler, %function
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PendSV_Handler:
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ldr r0,=PendSV_Handler
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bx r0
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.size PendSV_Handler, . - PendSV_Handler
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.align 1
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.thumb_func
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.weak SysTick_Handler
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.type SysTick_Handler, %function
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SysTick_Handler:
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ldr r0,=SysTick_Handler
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bx r0
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.size SysTick_Handler, . - SysTick_Handler
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.align 1
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.thumb_func
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.weak DMA0_IRQHandler
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.type DMA0_IRQHandler, %function
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DMA0_IRQHandler:
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ldr r0,=DMA0_DriverIRQHandler
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bx r0
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.size DMA0_IRQHandler, . - DMA0_IRQHandler
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.align 1
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.thumb_func
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.weak DMA1_IRQHandler
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.type DMA1_IRQHandler, %function
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DMA1_IRQHandler:
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ldr r0,=DMA1_DriverIRQHandler
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bx r0
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.size DMA1_IRQHandler, . - DMA1_IRQHandler
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.align 1
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.thumb_func
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.weak DMA2_IRQHandler
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.type DMA2_IRQHandler, %function
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DMA2_IRQHandler:
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ldr r0,=DMA2_DriverIRQHandler
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bx r0
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.size DMA2_IRQHandler, . - DMA2_IRQHandler
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.align 1
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.thumb_func
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.weak DMA3_IRQHandler
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.type DMA3_IRQHandler, %function
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DMA3_IRQHandler:
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ldr r0,=DMA3_DriverIRQHandler
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bx r0
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.size DMA3_IRQHandler, . - DMA3_IRQHandler
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.align 1
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.thumb_func
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.weak I2C0_IRQHandler
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.type I2C0_IRQHandler, %function
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I2C0_IRQHandler:
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ldr r0,=I2C0_DriverIRQHandler
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bx r0
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.size I2C0_IRQHandler, . - I2C0_IRQHandler
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.align 1
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.thumb_func
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.weak I2C1_IRQHandler
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.type I2C1_IRQHandler, %function
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I2C1_IRQHandler:
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ldr r0,=I2C1_DriverIRQHandler
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bx r0
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.size I2C1_IRQHandler, . - I2C1_IRQHandler
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.align 1
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.thumb_func
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.weak SPI0_IRQHandler
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.type SPI0_IRQHandler, %function
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SPI0_IRQHandler:
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ldr r0,=SPI0_DriverIRQHandler
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bx r0
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.size SPI0_IRQHandler, . - SPI0_IRQHandler
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.align 1
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.thumb_func
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.weak SPI1_IRQHandler
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.type SPI1_IRQHandler, %function
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SPI1_IRQHandler:
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ldr r0,=SPI1_DriverIRQHandler
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bx r0
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.size SPI1_IRQHandler, . - SPI1_IRQHandler
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.align 1
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.thumb_func
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.weak UART0_IRQHandler
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.type UART0_IRQHandler, %function
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UART0_IRQHandler:
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ldr r0,=UART0_DriverIRQHandler
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bx r0
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.size UART0_IRQHandler, . - UART0_IRQHandler
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.align 1
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.thumb_func
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.weak UART1_IRQHandler
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.type UART1_IRQHandler, %function
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UART1_IRQHandler:
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ldr r0,=UART1_DriverIRQHandler
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bx r0
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.size UART1_IRQHandler, . - UART1_IRQHandler
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.align 1
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.thumb_func
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.weak UART2_IRQHandler
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.type UART2_IRQHandler, %function
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UART2_IRQHandler:
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ldr r0,=UART2_DriverIRQHandler
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bx r0
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.size UART2_IRQHandler, . - UART2_IRQHandler
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/* Macro to define default handlers. Default handler
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* will be weak symbol and just dead loops. They can be
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* overwritten by other handlers */
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.macro def_irq_handler handler_name
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.weak \handler_name
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.set \handler_name, DefaultISR
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.endm
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/* Exception Handlers */
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def_irq_handler DMA0_DriverIRQHandler
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def_irq_handler DMA1_DriverIRQHandler
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def_irq_handler DMA2_DriverIRQHandler
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def_irq_handler DMA3_DriverIRQHandler
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def_irq_handler Reserved20_IRQHandler
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def_irq_handler FTFA_IRQHandler
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def_irq_handler LVD_LVW_IRQHandler
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def_irq_handler LLWU_IRQHandler
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def_irq_handler I2C0_DriverIRQHandler
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def_irq_handler I2C1_DriverIRQHandler
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def_irq_handler SPI0_DriverIRQHandler
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def_irq_handler SPI1_DriverIRQHandler
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def_irq_handler UART0_DriverIRQHandler
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def_irq_handler UART1_DriverIRQHandler
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def_irq_handler UART2_DriverIRQHandler
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def_irq_handler ADC0_IRQHandler
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def_irq_handler CMP0_IRQHandler
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def_irq_handler TPM0_IRQHandler
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def_irq_handler TPM1_IRQHandler
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def_irq_handler TPM2_IRQHandler
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def_irq_handler RTC_IRQHandler
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def_irq_handler RTC_Seconds_IRQHandler
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def_irq_handler PIT_IRQHandler
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def_irq_handler Reserved39_IRQHandler
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def_irq_handler USB0_IRQHandler
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def_irq_handler DAC0_IRQHandler
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def_irq_handler TSI0_IRQHandler
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def_irq_handler MCG_IRQHandler
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def_irq_handler LPTMR0_IRQHandler
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def_irq_handler Reserved45_IRQHandler
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def_irq_handler PORTA_IRQHandler
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def_irq_handler PORTD_IRQHandler
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.end
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