add spi lock with interrupt enable/disable
This commit is contained in:
hathach
parent
e6cf125e53
commit
f5ebc1700f
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@ -180,7 +180,6 @@ typedef struct {
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} hcd_ep_t;
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typedef struct {
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bool inited;
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atomic_bool busy; // busy transferring
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// cached register
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@ -194,6 +193,8 @@ typedef struct {
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volatile uint16_t frame_count;
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hcd_ep_t ep[8][2];
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OSAL_MUTEX_DEF(spi_mutex);
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} max2341_data_t;
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static max2341_data_t _hcd_data;
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@ -210,86 +211,106 @@ void tuh_max3421e_int_api(uint8_t rhport, bool enabled);
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//
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//--------------------------------------------------------------------+
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static void fifo_write(uint8_t reg, uint8_t const * buffer, uint16_t len) {
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uint8_t const rhport = 0;
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static void max3421_spi_lock(uint8_t rhport, bool in_isr) {
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// disable interrupt and mutex lock (for pre-emptive RTOS) if not in_isr
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if (!in_isr) {
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tuh_max3421e_int_api(rhport, false);
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}
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// assert CS
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tuh_max3421_spi_cs_api(rhport, true);
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}
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static void max3421_spi_unlock(uint8_t rhport, bool in_isr) {
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// de-assert CS
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tuh_max3421_spi_cs_api(rhport, false);
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// mutex unlock and re-enable interrupt
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if (!in_isr) {
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tuh_max3421e_int_api(rhport, true);
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}
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}
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static void fifo_write(uint8_t rhport, uint8_t reg, uint8_t const * buffer, uint16_t len, bool in_isr) {
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uint8_t hirq;
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reg |= CMDBYTE_WRITE;
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tuh_max3421_spi_cs_api(rhport, true);
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max3421_spi_lock(rhport, in_isr);
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tuh_max3421_spi_xfer_api(rhport, ®, 1, &hirq, 1);
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_hcd_data.hirq = hirq;
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tuh_max3421_spi_xfer_api(rhport, buffer, len, NULL, 0);
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tuh_max3421_spi_cs_api(rhport, false);
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max3421_spi_unlock(rhport, in_isr);
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}
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static void fifo_read(uint8_t * buffer, uint16_t len) {
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uint8_t const rhport = 0;
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static void fifo_read(uint8_t rhport, uint8_t * buffer, uint16_t len, bool in_isr) {
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uint8_t hirq;
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uint8_t const reg = RCVVFIFO_ADDR;
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tuh_max3421_spi_cs_api(rhport, true);
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max3421_spi_lock(rhport, in_isr);
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tuh_max3421_spi_xfer_api(rhport, ®, 1, &hirq, 0);
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_hcd_data.hirq = hirq;
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tuh_max3421_spi_xfer_api(rhport, NULL, 0, buffer, len);
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tuh_max3421_spi_cs_api(rhport, false);
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max3421_spi_unlock(rhport, in_isr);
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}
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static void reg_write(uint8_t reg, uint8_t data) {
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uint8_t const rhport = 0;
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static void reg_write(uint8_t rhport, uint8_t reg, uint8_t data, bool in_isr) {
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uint8_t tx_buf[2] = {reg | CMDBYTE_WRITE, data};
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uint8_t rx_buf[2] = {0, 0};
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tuh_max3421_spi_cs_api(rhport, true);
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max3421_spi_lock(rhport, in_isr);
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tuh_max3421_spi_xfer_api(rhport, tx_buf, 2, rx_buf, 2);
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tuh_max3421_spi_cs_api(rhport, false);
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max3421_spi_unlock(rhport, in_isr);
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// HIRQ register since we are in full-duplex mode
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_hcd_data.hirq = rx_buf[0];
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}
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static uint8_t reg_read(uint8_t reg) {
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uint8_t const rhport = 0;
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static uint8_t reg_read(uint8_t rhport, uint8_t reg, bool in_isr) {
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uint8_t tx_buf[2] = {reg, 0};
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uint8_t rx_buf[2] = {0, 0};
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tuh_max3421_spi_cs_api(rhport, true);
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max3421_spi_lock(rhport, in_isr);
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bool ret = tuh_max3421_spi_xfer_api(rhport, tx_buf, 2, rx_buf, 2);
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tuh_max3421_spi_cs_api(rhport, false);
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max3421_spi_unlock(rhport, in_isr);
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_hcd_data.hirq = rx_buf[0];
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return ret ? rx_buf[1] : 0;
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}
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static inline void hien_write(uint8_t data) {
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static inline void hien_write(uint8_t rhport, uint8_t data, bool in_isr) {
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_hcd_data.hien = data;
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reg_write(HIEN_ADDR, data);
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reg_write(rhport, HIEN_ADDR, data, in_isr);
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}
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static inline void mode_write(uint8_t data) {
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static inline void mode_write(uint8_t rhport, uint8_t data, bool in_isr) {
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_hcd_data.mode = data;
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reg_write(MODE_ADDR, data);
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reg_write(rhport, MODE_ADDR, data, in_isr);
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}
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static inline void peraddr_write(uint8_t data) {
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static inline void peraddr_write(uint8_t rhport, uint8_t data, bool in_isr) {
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if ( _hcd_data.peraddr == data ) return; // no need to change address
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_hcd_data.peraddr = data;
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reg_write(PERADDR_ADDR, data);
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reg_write(rhport, PERADDR_ADDR, data, in_isr);
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}
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static inline void hxfr_write(uint8_t data) {
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static inline void hxfr_write(uint8_t rhport, uint8_t data, bool in_isr) {
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_hcd_data.hxfr = data;
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reg_write(HXFR_ADDR, data);
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reg_write(rhport, HXFR_ADDR, data, in_isr);
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}
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static inline void sndbc_write(uint8_t data) {
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static inline void sndbc_write(uint8_t rhport, uint8_t data, bool in_isr) {
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_hcd_data.sndbc = data;
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reg_write(SNDBC_ADDR, data);
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reg_write(rhport, SNDBC_ADDR, data, in_isr);
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}
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@ -307,9 +328,7 @@ bool hcd_configure(uint8_t rhport, uint32_t cfg_id, const void* cfg_param) {
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}
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tusb_speed_t handle_connect_irq(uint8_t rhport) {
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(void) rhport;
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uint8_t const hrsl = reg_read(HRSL_ADDR);
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uint8_t const hrsl = reg_read(rhport, HRSL_ADDR, true);
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uint8_t const jk = hrsl & (HRSL_JSTATUS | HRSL_KSTATUS);
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tusb_speed_t speed;
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@ -328,7 +347,7 @@ tusb_speed_t handle_connect_irq(uint8_t rhport) {
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default: {
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// Low speed if (LS = 1 and J-state) or (LS = 0 and K-State)
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uint8_t const mode = reg_read(MODE_ADDR);
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uint8_t const mode = reg_read(rhport, MODE_ADDR, true);
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uint8_t const ls_bit = mode & MODE_LOWSPEED;
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if ( (ls_bit && (jk == HRSL_JSTATUS)) || (!ls_bit && (jk == HRSL_KSTATUS)) ) {
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@ -344,7 +363,7 @@ tusb_speed_t handle_connect_irq(uint8_t rhport) {
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}
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}
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mode_write(new_mode);
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mode_write(rhport, new_mode, true);
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TU_LOG2_INT(speed);
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return speed;
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}
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@ -358,32 +377,32 @@ bool hcd_init(uint8_t rhport) {
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tu_memclr(&_hcd_data, sizeof(_hcd_data));
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hcd_int_disable(rhport);
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// full duplex, interrupt negative edge
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reg_write(PINCTL_ADDR, PINCTL_FDUPSPI);
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reg_write(rhport, PINCTL_ADDR, PINCTL_FDUPSPI, false);
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// reset
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reg_write(USBCTL_ADDR, USBCTL_CHIPRES);
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reg_write(USBCTL_ADDR, 0);
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while( !(reg_read(USBIRQ_ADDR) & USBIRQ_OSCOK_IRQ) ) {
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reg_write(rhport, USBCTL_ADDR, USBCTL_CHIPRES, false);
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reg_write(rhport, USBCTL_ADDR, 0, false);
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while( !(reg_read(rhport, USBIRQ_ADDR, false) & USBIRQ_OSCOK_IRQ) ) {
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// wait for oscillator to stabilize
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}
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// Mode: Host and DP/DM pull down
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mode_write(MODE_DPPULLDN | MODE_DMPULLDN | MODE_HOST);
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mode_write(rhport, MODE_DPPULLDN | MODE_DMPULLDN | MODE_HOST, false);
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// frame reset & bus reset, this will trigger CONDET IRQ if device is already connected
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reg_write(HCTL_ADDR, HCTL_BUSRST | HCTL_FRMRST);
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reg_write(rhport, HCTL_ADDR, HCTL_BUSRST | HCTL_FRMRST, false);
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// clear all previously pending IRQ
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reg_write(HIRQ_ADDR, 0xff);
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_hcd_data.inited = true;
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reg_write(rhport, HIRQ_ADDR, 0xff, false);
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// Enable IRQ
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hien_write(DEFAULT_HIEN);
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hien_write(rhport, DEFAULT_HIEN, false);
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// Enable Interrupt pin
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reg_write(CPUCTL_ADDR, CPUCTL_IE);
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reg_write(rhport, CPUCTL_ADDR, CPUCTL_IE, false);
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return true;
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}
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@ -417,22 +436,20 @@ bool hcd_port_connect_status(uint8_t rhport) {
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// Reset USB bus on the port. Return immediately, bus reset sequence may not be complete.
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// Some port would require hcd_port_reset_end() to be invoked after 10ms to complete the reset sequence.
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void hcd_port_reset(uint8_t rhport) {
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(void) rhport;
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// Bus reset will also trigger CONDET IRQ, disable it
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uint8_t const hien = DEFAULT_HIEN & ~HIRQ_CONDET_IRQ;
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hien_write(hien);
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hien_write(rhport, hien, false);
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reg_write(HCTL_ADDR, HCTL_BUSRST);
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reg_write(rhport, HCTL_ADDR, HCTL_BUSRST, false);
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}
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// Complete bus reset sequence, may be required by some controllers
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void hcd_port_reset_end(uint8_t rhport) {
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(void) rhport;
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reg_write(HCTL_ADDR, 0);
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reg_write(rhport, HCTL_ADDR, 0, false);
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// Bus reset will also trigger CONDET IRQ, clear and re-enable it after reset
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reg_write(HIRQ_ADDR, HIRQ_CONDET_IRQ);
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hien_write(DEFAULT_HIEN);
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reg_write(rhport, HIRQ_ADDR, HIRQ_CONDET_IRQ, false);
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hien_write(rhport, DEFAULT_HIEN, false);
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}
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// Get port link speed
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@ -487,7 +504,7 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t daddr, uint8_t ep_addr, uint8_t * buf
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ep->xfer_complete = 0;
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ep->xfer_queued = 1;
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peraddr_write(daddr);
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peraddr_write(rhport, daddr, false);
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uint8_t hctl = 0;
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uint8_t hxfr = ep_num;
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@ -500,7 +517,7 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t daddr, uint8_t ep_addr, uint8_t * buf
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// ZLP for ACK stage, use HS
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hxfr |= HXFR_HS;
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hxfr |= (ep_dir ? 0 : HXFR_OUT_NIN);
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hxfr_write(hxfr);
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hxfr_write(rhport, hxfr, false);
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return true;
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}
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}
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@ -510,8 +527,8 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t daddr, uint8_t ep_addr, uint8_t * buf
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TU_ASSERT(_hcd_data.hirq & HIRQ_SNDBAV_IRQ);
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uint8_t const xact_len = (uint8_t) tu_min16(buflen, ep->packet_size);
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fifo_write(SNDFIFO_ADDR, buffer, xact_len);
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sndbc_write(xact_len);
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fifo_write(rhport, SNDFIFO_ADDR, buffer, xact_len, false);
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sndbc_write(rhport, xact_len, false);
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hctl = (ep->data_toggle ? HCTL_SNDTOG1 : HCTL_SNDTOG0);
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hxfr |= HXFR_OUT_NIN;
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@ -520,8 +537,8 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t daddr, uint8_t ep_addr, uint8_t * buf
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hctl = (ep->data_toggle ? HCTL_RCVTOG1 : HCTL_RCVTOG0);
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}
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reg_write(HCTL_ADDR, hctl);
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hxfr_write(hxfr);
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reg_write(rhport, HCTL_ADDR, hctl, false);
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hxfr_write(rhport, hxfr, false);
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return true;
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}
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@ -544,9 +561,9 @@ bool hcd_setup_send(uint8_t rhport, uint8_t daddr, uint8_t const setup_packet[8]
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ep->total_len = 8;
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ep->xferred_len = 0;
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peraddr_write(daddr);
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fifo_write(SUDFIFO_ADDR, setup_packet, 8);
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hxfr_write(HXFR_SETUP);
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peraddr_write(rhport, daddr, false);
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fifo_write(rhport, SUDFIFO_ADDR, setup_packet, 8, false);
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hxfr_write(rhport, HXFR_SETUP, false);
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return true;
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}
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@ -561,9 +578,7 @@ bool hcd_edpt_clear_stall(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr) {
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}
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static void handle_xfer_done(uint8_t rhport) {
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(void) rhport;
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uint8_t const hrsl = reg_read(HRSL_ADDR);
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uint8_t const hrsl = reg_read(rhport, HRSL_ADDR, true);
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uint8_t const hresult = hrsl & HRSL_RESULT_MASK;
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uint8_t ep_num = _hcd_data.hxfr & HXFR_EPNUM_MASK;
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@ -587,7 +602,7 @@ static void handle_xfer_done(uint8_t rhport) {
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// NAK on control, retry immediately
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//if (ep_num == 0)
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{
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hxfr_write(_hcd_data.hxfr);
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hxfr_write(rhport, _hcd_data.hxfr, true);
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}
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return;
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@ -615,11 +630,8 @@ static void handle_xfer_done(uint8_t rhport) {
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ep->buf += xact_len;
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if ( xact_len < ep->packet_size || ep->xferred_len >= ep->total_len ) {
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if ( ep_num ) {
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// save data toggle for non-control
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ep->data_toggle = (hrsl & HRSL_SNDTOGRD) ? 1 : 0;
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}
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// save data toggle
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ep->data_toggle = (hrsl & HRSL_SNDTOGRD) ? 1 : 0;
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hcd_event_xfer_complete(_hcd_data.peraddr, ep_num, ep->xferred_len, xfer_result, true);
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}else {
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// more to transfer
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@ -634,15 +646,12 @@ static void handle_xfer_done(uint8_t rhport) {
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// short packet or all bytes transferred
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if ( ep->xfer_complete ) {
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if ( ep_num ) {
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// save data toggle for non-control
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ep->data_toggle = (hrsl & HRSL_RCVTOGRD) ? 1 : 0;
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}
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// save data toggle
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ep->data_toggle = (hrsl & HRSL_RCVTOGRD) ? 1 : 0;
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hcd_event_xfer_complete(_hcd_data.peraddr, TUSB_DIR_IN_MASK | ep_num, ep->xferred_len, xfer_result, true);
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}else {
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// more to transfer
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hxfr_write(_hcd_data.hxfr);
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hxfr_write(rhport, _hcd_data.hxfr, true);
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}
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}
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}
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@ -669,10 +678,7 @@ void print_hirq(uint8_t hirq) {
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// Interrupt Handler
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void hcd_int_handler(uint8_t rhport) {
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// not initialized, do nothing
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if ( !_hcd_data.inited ) return;
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uint8_t hirq = reg_read(HIRQ_ADDR) & _hcd_data.hien;
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uint8_t hirq = reg_read(rhport, HIRQ_ADDR, true) & _hcd_data.hien;
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if (!hirq) return;
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// print_hirq(hirq);
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@ -701,17 +707,17 @@ void hcd_int_handler(uint8_t rhport) {
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// RCVDAV_IRQ can trigger 2 times (dual buffered)
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while ( hirq & HIRQ_RCVDAV_IRQ ) {
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uint8_t rcvbc = reg_read(RCVBC_ADDR);
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uint8_t rcvbc = reg_read(rhport, RCVBC_ADDR, true);
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xact_len = (uint8_t) tu_min16(rcvbc, ep->total_len - ep->xferred_len);
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if ( xact_len ) {
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fifo_read(ep->buf, xact_len);
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fifo_read(rhport, ep->buf, xact_len, true);
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ep->buf += xact_len;
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ep->xferred_len += xact_len;
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}
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// ack RCVDVAV IRQ
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reg_write(HIRQ_ADDR, HIRQ_RCVDAV_IRQ);
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hirq = reg_read(HIRQ_ADDR);
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reg_write(rhport, HIRQ_ADDR, HIRQ_RCVDAV_IRQ, true);
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hirq = reg_read(rhport, HIRQ_ADDR, true);
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}
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if ( xact_len < ep->packet_size || ep->xferred_len >= ep->total_len ) {
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@ -720,17 +726,17 @@ void hcd_int_handler(uint8_t rhport) {
|
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}
|
||||
|
||||
if ( hirq & HIRQ_HXFRDN_IRQ ) {
|
||||
reg_write(HIRQ_ADDR, HIRQ_HXFRDN_IRQ);
|
||||
reg_write(rhport, HIRQ_ADDR, HIRQ_HXFRDN_IRQ, true);
|
||||
handle_xfer_done(rhport);
|
||||
}
|
||||
|
||||
hirq = reg_read(HIRQ_ADDR);
|
||||
hirq = reg_read(rhport, HIRQ_ADDR, true);
|
||||
}
|
||||
|
||||
// clear all interrupt except SNDBAV_IRQ (never clear by us). Note RCVDAV_IRQ, HXFRDN_IRQ already clear while processing
|
||||
hirq &= ~HIRQ_SNDBAV_IRQ;
|
||||
if ( hirq ) {
|
||||
reg_write(HIRQ_ADDR, hirq);
|
||||
reg_write(rhport, HIRQ_ADDR, hirq, true);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue