initial ra6m5 ek, board_test led + sw works
This commit is contained in:
hathach
parent
14f1123bbd
commit
ec02ddf986
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@ -4,7 +4,7 @@ set(MCU_VARIANT ra4m1)
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set(JLINK_DEVICE R7FA4M1AB)
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function(update_board TARGET)
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target_compile_definitions(${TARGET} PUBLIC)
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target_sources(${TARGET} PRIVATE)
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target_include_directories(${BOARD_TARGET} PUBLIC)
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# target_compile_definitions(${TARGET} PUBLIC)
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# target_sources(${TARGET} PRIVATE)
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# target_include_directories(${BOARD_TARGET} PUBLIC)
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endfunction()
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@ -4,7 +4,7 @@ set(MCU_VARIANT ra4m3)
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set(JLINK_DEVICE R7FA4M3AF)
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function(update_board TARGET)
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target_compile_definitions(${TARGET} PUBLIC)
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target_sources(${TARGET} PRIVATE)
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target_include_directories(${BOARD_TARGET} PUBLIC)
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# target_compile_definitions(${TARGET} PUBLIC)
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# target_sources(${TARGET} PRIVATE)
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# target_include_directories(${BOARD_TARGET} PUBLIC)
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endfunction()
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@ -4,10 +4,7 @@ set(MCU_VARIANT ra6m1)
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set(JLINK_DEVICE R7FA6M1AD)
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function(update_board TARGET)
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target_compile_definitions(${TARGET} PUBLIC
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)
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target_sources(${TARGET} PRIVATE
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)
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target_include_directories(${BOARD_TARGET} PUBLIC
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)
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# target_compile_definitions(${TARGET} PUBLIC)
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# target_sources(${TARGET} PRIVATE)
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# target_include_directories(${BOARD_TARGET} PUBLIC)
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endfunction()
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@ -1,16 +0,0 @@
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/* generated configuration header file - do not edit */
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#ifndef BSP_PIN_CFG_H_
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#define BSP_PIN_CFG_H_
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#include "r_ioport.h"
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/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
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FSP_HEADER
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extern const ioport_cfg_t g_bsp_pin_cfg; /* RA6M1-EK.pincfg */
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void BSP_PinConfigSecurityInit();
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/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
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FSP_FOOTER
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#endif /* BSP_PIN_CFG_H_ */
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@ -0,0 +1,10 @@
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set(CMAKE_SYSTEM_PROCESSOR cortex-m33 CACHE INTERNAL "System Processor")
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set(MCU_VARIANT ra6m5)
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set(JLINK_DEVICE R7FA6M5BH)
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function(update_board TARGET)
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# target_compile_definitions(${TARGET} PUBLIC)
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# target_sources(${TARGET} PRIVATE)
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# target_include_directories(${BOARD_TARGET} PUBLIC)
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endfunction()
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@ -0,0 +1,52 @@
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/*
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* The MIT License (MIT)
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*
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* Copyright (c) 2023 Ha Thach (tinyusb.org)
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*
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* This file is part of the TinyUSB stack.
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*/
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#ifndef _BOARD_H_
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#define _BOARD_H_
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#ifdef __cplusplus
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extern "C" {
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#endif
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#define LED1 BSP_IO_PORT_00_PIN_08
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#define LED_STATE_ON 1
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#define SW1 BSP_IO_PORT_00_PIN_05
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#define BUTTON_STATE_ACTIVE 0
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const ioport_pin_cfg_t board_pin_cfg[] = {
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{.pin = BSP_IO_PORT_04_PIN_07, .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_USB_FS)},
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{.pin = BSP_IO_PORT_05_PIN_00, .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_USB_FS)},
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{.pin = BSP_IO_PORT_05_PIN_01, .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_USB_FS)},
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{.pin = LED1, .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW)},
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{.pin = SW1, .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_INPUT)},
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};
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#ifdef __cplusplus
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}
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#endif
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#endif
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@ -0,0 +1,7 @@
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CPU_CORE = cortex-m33
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MCU_VARIANT = ra6m5
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# For flash-jlink target
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JLINK_DEVICE = R7FA6M5BH
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flash: flash-jlink
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@ -0,0 +1,65 @@
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/* generated configuration header file - do not edit */
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#ifndef BSP_CFG_H_
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#define BSP_CFG_H_
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#ifdef __cplusplus
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extern "C" {
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#endif
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#include "bsp_clock_cfg.h"
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#include "bsp_mcu_family_cfg.h"
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#define RA_NOT_DEFINED 0
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#ifndef BSP_CFG_RTOS
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#if (RA_NOT_DEFINED) != (2)
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#define BSP_CFG_RTOS (2)
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#elif (RA_NOT_DEFINED) != (RA_NOT_DEFINED)
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#define BSP_CFG_RTOS (1)
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#else
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#define BSP_CFG_RTOS (0)
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#endif
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#endif
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#ifndef BSP_CFG_RTC_USED
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#define BSP_CFG_RTC_USED (RA_NOT_DEFINED)
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#endif
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#undef RA_NOT_DEFINED
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#if defined(_RA_BOOT_IMAGE)
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#define BSP_CFG_BOOT_IMAGE (1)
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#endif
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#define BSP_CFG_MCU_VCC_MV (3300)
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#define BSP_CFG_STACK_MAIN_BYTES (0x400)
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#define BSP_CFG_HEAP_BYTES (0x1000)
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#define BSP_CFG_PARAM_CHECKING_ENABLE (1)
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#define BSP_CFG_ASSERT (0)
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#define BSP_CFG_ERROR_LOG (0)
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#define BSP_CFG_PFS_PROTECT ((1))
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#define BSP_CFG_C_RUNTIME_INIT ((1))
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#define BSP_CFG_EARLY_INIT ((0))
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#define BSP_CFG_STARTUP_CLOCK_REG_NOT_RESET ((0))
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#ifndef BSP_CLOCK_CFG_MAIN_OSC_POPULATED
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#define BSP_CLOCK_CFG_MAIN_OSC_POPULATED (1)
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#endif
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#ifndef BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE
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#define BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE (0)
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#endif
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#ifndef BSP_CLOCK_CFG_SUBCLOCK_DRIVE
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#define BSP_CLOCK_CFG_SUBCLOCK_DRIVE (0)
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#endif
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#ifndef BSP_CLOCK_CFG_SUBCLOCK_POPULATED
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#define BSP_CLOCK_CFG_SUBCLOCK_POPULATED (1)
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#endif
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#ifndef BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS
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#define BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS 1000
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#endif
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// for SystemInit()
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void bsp_init(void * p_args);
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#ifdef __cplusplus
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}
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#endif
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#endif /* BSP_CFG_H_ */
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@ -0,0 +1,5 @@
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/* generated configuration header file - do not edit */
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#ifndef BSP_MCU_DEVICE_CFG_H_
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#define BSP_MCU_DEVICE_CFG_H_
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#define BSP_CFG_MCU_PART_SERIES (6)
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#endif /* BSP_MCU_DEVICE_CFG_H_ */
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@ -0,0 +1,11 @@
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/* generated configuration header file - do not edit */
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#ifndef BSP_MCU_DEVICE_PN_CFG_H_
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#define BSP_MCU_DEVICE_PN_CFG_H_
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#define BSP_MCU_R7FA6M5BH3CFC
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#define BSP_MCU_FEATURE_SET ('B')
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#define BSP_ROM_SIZE_BYTES (2097152)
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#define BSP_RAM_SIZE_BYTES (524288)
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#define BSP_DATA_FLASH_SIZE_BYTES (8192)
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#define BSP_PACKAGE_LQFP
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#define BSP_PACKAGE_PINS (176)
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#endif /* BSP_MCU_DEVICE_PN_CFG_H_ */
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@ -0,0 +1,387 @@
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/* generated configuration header file - do not edit */
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#ifndef BSP_MCU_FAMILY_CFG_H_
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#define BSP_MCU_FAMILY_CFG_H_
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#ifdef __cplusplus
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extern "C" {
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#endif
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#include "bsp_mcu_device_pn_cfg.h"
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#include "bsp_mcu_device_cfg.h"
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#include "../../../ra/fsp/src/bsp/mcu/ra6m5/bsp_mcu_info.h"
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#include "bsp_clock_cfg.h"
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#define BSP_MCU_GROUP_RA6M5 (1)
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#define BSP_LOCO_HZ (32768)
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#define BSP_MOCO_HZ (8000000)
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#define BSP_SUB_CLOCK_HZ (32768)
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#if BSP_CFG_HOCO_FREQUENCY == 0
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#define BSP_HOCO_HZ (16000000)
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#elif BSP_CFG_HOCO_FREQUENCY == 1
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#define BSP_HOCO_HZ (18000000)
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#elif BSP_CFG_HOCO_FREQUENCY == 2
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#define BSP_HOCO_HZ (20000000)
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#else
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#error "Invalid HOCO frequency chosen (BSP_CFG_HOCO_FREQUENCY) in bsp_clock_cfg.h"
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#endif
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#define BSP_CFG_FLL_ENABLE (0)
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#define BSP_CORTEX_VECTOR_TABLE_ENTRIES (16U)
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#define BSP_VECTOR_TABLE_MAX_ENTRIES (112U)
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#if defined(_RA_TZ_SECURE)
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#define BSP_TZ_SECURE_BUILD (1)
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#define BSP_TZ_NONSECURE_BUILD (0)
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#elif defined(_RA_TZ_NONSECURE)
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#define BSP_TZ_SECURE_BUILD (0)
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#define BSP_TZ_NONSECURE_BUILD (1)
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#else
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#define BSP_TZ_SECURE_BUILD (0)
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#define BSP_TZ_NONSECURE_BUILD (0)
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#endif
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/* TrustZone Settings */
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#define BSP_TZ_CFG_INIT_SECURE_ONLY (BSP_CFG_CLOCKS_SECURE || (!BSP_CFG_CLOCKS_OVERRIDE))
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#define BSP_TZ_CFG_SKIP_INIT (BSP_TZ_NONSECURE_BUILD && BSP_TZ_CFG_INIT_SECURE_ONLY)
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#define BSP_TZ_CFG_EXCEPTION_RESPONSE (0)
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/* CMSIS TrustZone Settings */
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#define SCB_CSR_AIRCR_INIT (1)
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#define SCB_AIRCR_BFHFNMINS_VAL (0)
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#define SCB_AIRCR_SYSRESETREQS_VAL (1)
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#define SCB_AIRCR_PRIS_VAL (0)
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#define TZ_FPU_NS_USAGE (1)
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#ifndef SCB_NSACR_CP10_11_VAL
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#define SCB_NSACR_CP10_11_VAL (3U)
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#endif
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#ifndef FPU_FPCCR_TS_VAL
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#define FPU_FPCCR_TS_VAL (1U)
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#endif
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#define FPU_FPCCR_CLRONRETS_VAL (1)
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#ifndef FPU_FPCCR_CLRONRET_VAL
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#define FPU_FPCCR_CLRONRET_VAL (1)
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#endif
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/* The C-Cache line size that is configured during startup. */
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#ifndef BSP_CFG_C_CACHE_LINE_SIZE
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#define BSP_CFG_C_CACHE_LINE_SIZE (1U)
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#endif
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/* Type 1 Peripheral Security Attribution */
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/* Peripheral Security Attribution Register (PSAR) Settings */
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#ifndef BSP_TZ_CFG_PSARB
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#define BSP_TZ_CFG_PSARB (\
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(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* CAN1 */ | \
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(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2) /* CAN0 */ | \
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(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 8) /* IIC1 */ | \
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(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 9) /* IIC0 */ | \
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(((1 > 0) ? 0U : 1U) << 11) /* USBFS */ | \
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(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 18) /* SPI1 */ | \
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(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 19) /* SPI0 */ | \
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(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 22) /* SCI9 */ | \
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(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 23) /* SCI8 */ | \
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(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 24) /* SCI7 */ | \
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(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 25) /* SCI6 */ | \
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(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 26) /* SCI5 */ | \
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(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 27) /* SCI4 */ | \
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(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 28) /* SCI3 */ | \
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(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 29) /* SCI2 */ | \
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(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 30) /* SCI1 */ | \
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(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 31) /* SCI0 */ | \
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0x33f4f9) /* Unused */
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#endif
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#ifndef BSP_TZ_CFG_PSARC
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#define BSP_TZ_CFG_PSARC (\
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(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) /* CAC */ | \
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(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* CRC */ | \
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(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 3) /* CTSU */ | \
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(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 8) /* SSIE0 */ | \
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(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 12) /* SDHI0 */ | \
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(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 13) /* DOC */ | \
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(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 31) /* SCE9 */ | \
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0x7fffcef4) /* Unused */
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#endif
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#ifndef BSP_TZ_CFG_PSARD
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#define BSP_TZ_CFG_PSARD (\
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(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) /* AGT3 */ | \
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(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* AGT2 */ | \
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(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2) /* AGT1 */ | \
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(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 3) /* AGT0 */ | \
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(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 11) /* POEG3 */ | \
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(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 12) /* POEG2 */ | \
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(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 13) /* POEG1 */ | \
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(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 14) /* POEG0 */ | \
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(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 15) /* ADC1 */ | \
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(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 16) /* ADC0 */ | \
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(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 20) /* DAC */ | \
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(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 22) /* TSN */ | \
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0xffae07f0) /* Unused */
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#endif
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#ifndef BSP_TZ_CFG_PSARE
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#define BSP_TZ_CFG_PSARE (\
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(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) /* WDT */ | \
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(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* IWDT */ | \
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(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2) /* RTC */ | \
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(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 14) /* AGT5 */ | \
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(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 15) /* AGT4 */ | \
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(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 22) /* GPT9 */ | \
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(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 23) /* GPT8 */ | \
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(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 24) /* GPT7 */ | \
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(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 25) /* GPT6 */ | \
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(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 26) /* GPT5 */ | \
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(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 27) /* GPT4 */ | \
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(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 28) /* GPT3 */ | \
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(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 29) /* GPT2 */ | \
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(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 30) /* GPT1 */ | \
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(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 31) /* GPT0 */ | \
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0x3f3ff8) /* Unused */
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#endif
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#ifndef BSP_TZ_CFG_MSSAR
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#define BSP_TZ_CFG_MSSAR (\
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(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) /* ELC */ | \
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(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* DTC_DMAC */ | \
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0xfffffffc) /* Unused */
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#endif
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/* Type 2 Peripheral Security Attribution */
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/* Security attribution for Cache registers. */
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#ifndef BSP_TZ_CFG_CSAR
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#define BSP_TZ_CFG_CSAR (0xFFFFFFFFU)
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#endif
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/* Security attribution for RSTSRn registers. */
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#ifndef BSP_TZ_CFG_RSTSAR
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#define BSP_TZ_CFG_RSTSAR (0xFFFFFFFFU)
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#endif
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|
||||
/* Security attribution for registers of LVD channels. */
|
||||
#ifndef BSP_TZ_CFG_LVDSAR
|
||||
#define BSP_TZ_CFG_LVDSAR (\
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) | /* LVD Channel 1 */ \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) | /* LVD Channel 2 */ \
|
||||
0xFFFFFFFCU)
|
||||
#endif
|
||||
|
||||
/* Security attribution for LPM registers. */
|
||||
#ifndef BSP_TZ_CFG_LPMSAR
|
||||
#define BSP_TZ_CFG_LPMSAR ((RA_NOT_DEFINED > 0) ? 0xFFFFFCEAU : 0xFFFFFFFFU)
|
||||
#endif
|
||||
/* Deep Standby Interrupt Factor Security Attribution Register. */
|
||||
#ifndef BSP_TZ_CFG_DPFSAR
|
||||
#define BSP_TZ_CFG_DPFSAR ((RA_NOT_DEFINED > 0) ? 0xF2E00000U : 0xFFFFFFFFU)
|
||||
#endif
|
||||
|
||||
/* Security attribution for CGC registers. */
|
||||
#ifndef BSP_TZ_CFG_CGFSAR
|
||||
#if BSP_CFG_CLOCKS_SECURE
|
||||
/* Protect all CGC registers from Non-secure write access. */
|
||||
#define BSP_TZ_CFG_CGFSAR (0xFFFCE402U)
|
||||
#else
|
||||
/* Allow Secure and Non-secure write access. */
|
||||
#define BSP_TZ_CFG_CGFSAR (0xFFFFFFFFU)
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/* Security attribution for Battery Backup registers. */
|
||||
#ifndef BSP_TZ_CFG_BBFSAR
|
||||
#define BSP_TZ_CFG_BBFSAR (0x00FFFFFF)
|
||||
#endif
|
||||
|
||||
/* Security attribution for registers for IRQ channels. */
|
||||
#ifndef BSP_TZ_CFG_ICUSARA
|
||||
#define BSP_TZ_CFG_ICUSARA (\
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0U) /* External IRQ0 */ | \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1U) /* External IRQ1 */ | \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2U) /* External IRQ2 */ | \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 3U) /* External IRQ3 */ | \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 4U) /* External IRQ4 */ | \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 5U) /* External IRQ5 */ | \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 6U) /* External IRQ6 */ | \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 7U) /* External IRQ7 */ | \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 8U) /* External IRQ8 */ | \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 9U) /* External IRQ9 */ | \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 10U) /* External IRQ10 */ | \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 11U) /* External IRQ11 */ | \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 12U) /* External IRQ12 */ | \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 13U) /* External IRQ13 */ | \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 14U) /* External IRQ14 */ | \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 15U) /* External IRQ15 */ | \
|
||||
0xFFFF0000U)
|
||||
#endif
|
||||
|
||||
/* Security attribution for NMI registers. */
|
||||
#ifndef BSP_TZ_CFG_ICUSARB
|
||||
#define BSP_TZ_CFG_ICUSARB (0 | 0xFFFFFFFEU) /* Should match AIRCR.BFHFNMINS. */
|
||||
#endif
|
||||
|
||||
/* Security attribution for registers for DMAC channels */
|
||||
#ifndef BSP_TZ_CFG_ICUSARC
|
||||
#define BSP_TZ_CFG_ICUSARC (\
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0U) /* DMAC Channel 0 */ | \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1U) /* DMAC Channel 1 */ | \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2U) /* DMAC Channel 2 */ | \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 3U) /* DMAC Channel 3 */ | \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 4U) /* DMAC Channel 4 */ | \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 5U) /* DMAC Channel 5 */ | \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 6U) /* DMAC Channel 6 */ | \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 7U) /* DMAC Channel 7 */ | \
|
||||
0xFFFFFF00U)
|
||||
#endif
|
||||
|
||||
/* Security attribution registers for SELSR0. */
|
||||
#ifndef BSP_TZ_CFG_ICUSARD
|
||||
#define BSP_TZ_CFG_ICUSARD ((RA_NOT_DEFINED > 0) ? 0xFFFFFFFEU : 0xFFFFFFFFU)
|
||||
#endif
|
||||
|
||||
/* Security attribution registers for WUPEN0. */
|
||||
#ifndef BSP_TZ_CFG_ICUSARE
|
||||
#define BSP_TZ_CFG_ICUSARE ((RA_NOT_DEFINED > 0) ? 0x04F2FFFFU : 0xFFFFFFFFU)
|
||||
#endif
|
||||
|
||||
/* Security attribution registers for WUPEN1. */
|
||||
#ifndef BSP_TZ_CFG_ICUSARF
|
||||
#define BSP_TZ_CFG_ICUSARF ((RA_NOT_DEFINED > 0) ? 0xFFFFFFF8U : 0xFFFFFFFFU)
|
||||
#endif
|
||||
|
||||
/* Set DTCSTSAR if the Secure program uses the DTC. */
|
||||
#if RA_NOT_DEFINED == RA_NOT_DEFINED
|
||||
#define BSP_TZ_CFG_DTC_USED (0U)
|
||||
#else
|
||||
#define BSP_TZ_CFG_DTC_USED (1U)
|
||||
#endif
|
||||
|
||||
/* Security attribution of FLWT and FCKMHZ registers. */
|
||||
#ifndef BSP_TZ_CFG_FSAR
|
||||
/* If the CGC registers are only accessible in Secure mode, than there is no
|
||||
* reason for nonsecure applications to access FLWT and FCKMHZ. */
|
||||
#if BSP_CFG_CLOCKS_SECURE
|
||||
/* Protect FLWT and FCKMHZ registers from nonsecure write access. */
|
||||
#define BSP_TZ_CFG_FSAR (0xFEFEU)
|
||||
#else
|
||||
/* Allow Secure and Non-secure write access. */
|
||||
#define BSP_TZ_CFG_FSAR (0xFFFFU)
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/* Security attribution for SRAM registers. */
|
||||
#ifndef BSP_TZ_CFG_SRAMSAR
|
||||
/* If the CGC registers are only accessible in Secure mode, than there is no reason for Non Secure applications to access
|
||||
* SRAM0WTEN and therefore there is no reason to access PRCR2. */
|
||||
#define BSP_TZ_CFG_SRAMSAR (\
|
||||
1 | \
|
||||
((BSP_CFG_CLOCKS_SECURE == 0) ? (1U << 1U) : 0U) | \
|
||||
4 | \
|
||||
0xFFFFFFF8U)
|
||||
#endif
|
||||
|
||||
/* Security attribution for Standby RAM registers. */
|
||||
#ifndef BSP_TZ_CFG_STBRAMSAR
|
||||
#define BSP_TZ_CFG_STBRAMSAR (0 | 0xFFFFFFF0U)
|
||||
#endif
|
||||
|
||||
/* Security attribution for the DMAC Bus Master MPU settings. */
|
||||
#ifndef BSP_TZ_CFG_MMPUSARA
|
||||
/* The DMAC Bus Master MPU settings should align with the DMAC channel settings. */
|
||||
#define BSP_TZ_CFG_MMPUSARA (BSP_TZ_CFG_ICUSARC)
|
||||
#endif
|
||||
|
||||
/* Security Attribution Register A for BUS Control registers. */
|
||||
#ifndef BSP_TZ_CFG_BUSSARA
|
||||
#define BSP_TZ_CFG_BUSSARA (0xFFFFFFFFU)
|
||||
#endif
|
||||
/* Security Attribution Register B for BUS Control registers. */
|
||||
#ifndef BSP_TZ_CFG_BUSSARB
|
||||
#define BSP_TZ_CFG_BUSSARB (0xFFFFFFFFU)
|
||||
#endif
|
||||
|
||||
/* Enable Uninitialized Non-Secure Application Fallback. */
|
||||
#ifndef BSP_TZ_CFG_NON_SECURE_APPLICATION_FALLBACK
|
||||
#define BSP_TZ_CFG_NON_SECURE_APPLICATION_FALLBACK (1U)
|
||||
#endif
|
||||
|
||||
#define OFS_SEQ1 0xA001A001 | (1 << 1) | (3 << 2)
|
||||
#define OFS_SEQ2 (15 << 4) | (3 << 8) | (3 << 10)
|
||||
#define OFS_SEQ3 (1 << 12) | (1 << 14) | (1 << 17)
|
||||
#define OFS_SEQ4 (3 << 18) |(15 << 20) | (3 << 24) | (3 << 26)
|
||||
#define OFS_SEQ5 (1 << 28) | (1 << 30)
|
||||
#define BSP_CFG_ROM_REG_OFS0 (OFS_SEQ1 | OFS_SEQ2 | OFS_SEQ3 | OFS_SEQ4 | OFS_SEQ5)
|
||||
|
||||
/* Option Function Select Register 1 Security Attribution */
|
||||
#ifndef BSP_CFG_ROM_REG_OFS1_SEL
|
||||
#if defined(_RA_TZ_SECURE) || defined(_RA_TZ_NONSECURE)
|
||||
#define BSP_CFG_ROM_REG_OFS1_SEL (0xFFFFF8F8U | ((BSP_CFG_CLOCKS_SECURE == 0) ? 0x700U : 0U) | ((RA_NOT_DEFINED > 0) ? 0U : 0x7U))
|
||||
#else
|
||||
#define BSP_CFG_ROM_REG_OFS1_SEL (0xFFFFF8F8U)
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#define BSP_CFG_ROM_REG_OFS1 (0xFFFFFEF8 | (1 << 2) | (3) | (1 << 8))
|
||||
|
||||
/* Used to create IELS values for the interrupt initialization table g_interrupt_event_link_select. */
|
||||
#define BSP_PRV_IELS_ENUM(vector) (ELC_ ## vector)
|
||||
|
||||
/* Dual Mode Select Register */
|
||||
#ifndef BSP_CFG_ROM_REG_DUALSEL
|
||||
#define BSP_CFG_ROM_REG_DUALSEL (0xFFFFFFF8U | (0x7U))
|
||||
#endif
|
||||
|
||||
/* Block Protection Register 0 */
|
||||
#ifndef BSP_CFG_ROM_REG_BPS0
|
||||
#define BSP_CFG_ROM_REG_BPS0 (~( 0U))
|
||||
#endif
|
||||
/* Block Protection Register 1 */
|
||||
#ifndef BSP_CFG_ROM_REG_BPS1
|
||||
#define BSP_CFG_ROM_REG_BPS1 (~( 0U))
|
||||
#endif
|
||||
/* Block Protection Register 2 */
|
||||
#ifndef BSP_CFG_ROM_REG_BPS2
|
||||
#define BSP_CFG_ROM_REG_BPS2 (~( 0U))
|
||||
#endif
|
||||
/* Block Protection Register 3 */
|
||||
#ifndef BSP_CFG_ROM_REG_BPS3
|
||||
#define BSP_CFG_ROM_REG_BPS3 (0xFFFFFFFFU)
|
||||
#endif
|
||||
/* Permanent Block Protection Register 0 */
|
||||
#ifndef BSP_CFG_ROM_REG_PBPS0
|
||||
#define BSP_CFG_ROM_REG_PBPS0 (~( 0U))
|
||||
#endif
|
||||
/* Permanent Block Protection Register 1 */
|
||||
#ifndef BSP_CFG_ROM_REG_PBPS1
|
||||
#define BSP_CFG_ROM_REG_PBPS1 (~( 0U))
|
||||
#endif
|
||||
/* Permanent Block Protection Register 2 */
|
||||
#ifndef BSP_CFG_ROM_REG_PBPS2
|
||||
#define BSP_CFG_ROM_REG_PBPS2 (~( 0U))
|
||||
#endif
|
||||
/* Permanent Block Protection Register 3 */
|
||||
#ifndef BSP_CFG_ROM_REG_PBPS3
|
||||
#define BSP_CFG_ROM_REG_PBPS3 (0xFFFFFFFFU)
|
||||
#endif
|
||||
/* Security Attribution for Block Protection Register 0 (If any blocks are marked as protected in the secure application, then mark them as secure) */
|
||||
#ifndef BSP_CFG_ROM_REG_BPS_SEL0
|
||||
#define BSP_CFG_ROM_REG_BPS_SEL0 (BSP_CFG_ROM_REG_BPS0 & BSP_CFG_ROM_REG_PBPS0)
|
||||
#endif
|
||||
/* Security Attribution for Block Protection Register 1 (If any blocks are marked as protected in the secure application, then mark them as secure) */
|
||||
#ifndef BSP_CFG_ROM_REG_BPS_SEL1
|
||||
#define BSP_CFG_ROM_REG_BPS_SEL1 (BSP_CFG_ROM_REG_BPS1 & BSP_CFG_ROM_REG_PBPS1)
|
||||
#endif
|
||||
/* Security Attribution for Block Protection Register 2 (If any blocks are marked as protected in the secure application, then mark them as secure) */
|
||||
#ifndef BSP_CFG_ROM_REG_BPS_SEL2
|
||||
#define BSP_CFG_ROM_REG_BPS_SEL2 (BSP_CFG_ROM_REG_BPS2 & BSP_CFG_ROM_REG_PBPS2)
|
||||
#endif
|
||||
/* Security Attribution for Block Protection Register 3 (If any blocks are marked as protected in the secure application, then mark them as secure) */
|
||||
#ifndef BSP_CFG_ROM_REG_BPS_SEL3
|
||||
#define BSP_CFG_ROM_REG_BPS_SEL3 (BSP_CFG_ROM_REG_BPS3 & BSP_CFG_ROM_REG_PBPS3)
|
||||
#endif
|
||||
#ifndef BSP_CLOCK_CFG_MAIN_OSC_WAIT
|
||||
#define BSP_CLOCK_CFG_MAIN_OSC_WAIT (9)
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
#endif /* BSP_MCU_FAMILY_CFG_H_ */
|
||||
|
|
@ -0,0 +1,35 @@
|
|||
/* generated configuration header file - do not edit */
|
||||
#ifndef BSP_CLOCK_CFG_H_
|
||||
#define BSP_CLOCK_CFG_H_
|
||||
#define BSP_CFG_CLOCKS_SECURE (0)
|
||||
#define BSP_CFG_CLOCKS_OVERRIDE (0)
|
||||
#define BSP_CFG_XTAL_HZ (24000000) /* XTAL 24000000Hz */
|
||||
#define BSP_CFG_HOCO_FREQUENCY (2) /* HOCO 20MHz */
|
||||
#define BSP_CFG_PLL_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC) /* PLL Src: XTAL */
|
||||
#define BSP_CFG_PLL_DIV (BSP_CLOCKS_PLL_DIV_3) /* PLL Div /3 */
|
||||
#define BSP_CFG_PLL_MUL BSP_CLOCKS_PLL_MUL_25_0 /* PLL Mul x25.0 */
|
||||
#define BSP_CFG_PLL2_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC) /* PLL2 Src: XTAL */
|
||||
#define BSP_CFG_PLL2_DIV (BSP_CLOCKS_PLL_DIV_2) /* PLL2 Div /2 */
|
||||
#define BSP_CFG_PLL2_MUL BSP_CLOCKS_PLL_MUL_20_0 /* PLL2 Mul x20.0 */
|
||||
#define BSP_CFG_CLOCK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL) /* Clock Src: PLL */
|
||||
#define BSP_CFG_CLKOUT_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* CLKOUT Disabled */
|
||||
#define BSP_CFG_UCK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL2) /* UCLK Src: PLL2 */
|
||||
#define BSP_CFG_U60CK_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* U60CK Disabled */
|
||||
#define BSP_CFG_OCTA_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* OCTASPICLK Disabled */
|
||||
#define BSP_CFG_CANFDCLK_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* CANFDCLK Disabled */
|
||||
#define BSP_CFG_CECCLK_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* CECCLK Disabled */
|
||||
#define BSP_CFG_ICLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* ICLK Div /1 */
|
||||
#define BSP_CFG_PCLKA_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* PCLKA Div /2 */
|
||||
#define BSP_CFG_PCLKB_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_4) /* PCLKB Div /4 */
|
||||
#define BSP_CFG_PCLKC_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_4) /* PCLKC Div /4 */
|
||||
#define BSP_CFG_PCLKD_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* PCLKD Div /2 */
|
||||
#define BSP_CFG_BCLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* BCLK Div /2 */
|
||||
#define BSP_CFG_BCLK_OUTPUT (2) /* EBCLK Div /2 */
|
||||
#define BSP_CFG_FCLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_4) /* FCLK Div /4 */
|
||||
#define BSP_CFG_CLKOUT_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* CLKOUT Div /1 */
|
||||
#define BSP_CFG_UCK_DIV (BSP_CLOCKS_USB_CLOCK_DIV_5) /* UCLK Div /5 */
|
||||
#define BSP_CFG_U60CK_DIV (BSP_CLOCKS_USB60_CLOCK_DIV_1) /* U60CK Div /1 */
|
||||
#define BSP_CFG_OCTA_DIV (BSP_CLOCKS_OCTA_CLOCK_DIV_1) /* OCTASPICLK Div /1 */
|
||||
#define BSP_CFG_CANFDCLK_DIV (BSP_CLOCKS_CANFD_CLOCK_DIV_1) /* CANFDCLK Div /1 */
|
||||
#define BSP_CFG_CECCLK_DIV (BSP_CLOCKS_CEC_CLOCK_DIV_1) /* CECCLK Div /1 */
|
||||
#endif /* BSP_CLOCK_CFG_H_ */
|
||||
|
|
@ -0,0 +1,7 @@
|
|||
/* generated configuration header file - do not edit */
|
||||
#ifndef R_IOPORT_CFG_H_
|
||||
#define R_IOPORT_CFG_H_
|
||||
|
||||
#define IOPORT_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE)
|
||||
|
||||
#endif /* R_IOPORT_CFG_H_ */
|
||||
|
|
@ -0,0 +1,5 @@
|
|||
/* vector numbers are configurable/dynamic, hence this, it will be used inside the port */
|
||||
#define TU_IRQn 0
|
||||
#define USBFS_RESUME_IRQn 1
|
||||
#define USBFS_FIFO_0_IRQn 2
|
||||
#define USBFS_FIFO_1_IRQn 3
|
||||
|
|
@ -55,6 +55,7 @@ function(add_board_target BOARD_TARGET)
|
|||
${FSP_RA}/inc/api
|
||||
${FSP_RA}/inc/instances
|
||||
${FSP_RA}/src/bsp/cmsis/Device/RENESAS/Include
|
||||
${FSP_RA}/src/bsp/mcu/all
|
||||
${FSP_RA}/src/bsp/mcu/${MCU_VARIANT}
|
||||
)
|
||||
|
||||
|
|
|
|||
|
|
@ -0,0 +1,22 @@
|
|||
RAM_START = 0x20000000;
|
||||
RAM_LENGTH = 0x80000;
|
||||
FLASH_START = 0x00000000;
|
||||
FLASH_LENGTH = 0x200000;
|
||||
DATA_FLASH_START = 0x08000000;
|
||||
DATA_FLASH_LENGTH = 0x2000;
|
||||
OPTION_SETTING_START = 0x0100A100;
|
||||
OPTION_SETTING_LENGTH = 0x100;
|
||||
OPTION_SETTING_S_START = 0x0100A200;
|
||||
OPTION_SETTING_S_LENGTH = 0x100;
|
||||
ID_CODE_START = 0x00000000;
|
||||
ID_CODE_LENGTH = 0x0;
|
||||
SDRAM_START = 0x80010000;
|
||||
SDRAM_LENGTH = 0x0;
|
||||
QSPI_FLASH_START = 0x60000000;
|
||||
QSPI_FLASH_LENGTH = 0x4000000;
|
||||
OSPI_DEVICE_0_START = 0x68000000;
|
||||
OSPI_DEVICE_0_LENGTH = 0x8000000;
|
||||
OSPI_DEVICE_1_START = 0x70000000;
|
||||
OSPI_DEVICE_1_LENGTH = 0x10000000;
|
||||
|
||||
INCLUDE fsp.ld
|
||||
Loading…
Reference in New Issue