rt10xx: correct max endpoint count is 8
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hathach
parent
04d8671641
commit
e2f60a5134
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@ -38,23 +38,15 @@
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#if CFG_TUSB_MCU == OPT_MCU_MIMXRT10XX
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#include "fsl_device_registers.h"
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// RT1010 and RT1020 only has 1 USB controller
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#if FSL_FEATURE_SOC_USBHS_COUNT == 1
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#define DCD_REGS_BASE { (dcd_registers_t*) USB_BASE }
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IRQn_Type DCD_IRQn[] = { USB_OTG1_IRQn };
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// RT1050, RT1060 has 2 USB controllers
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#else
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#define DCD_REGS_BASE { (dcd_registers_t*) USB1_BASE, (dcd_registers_t*) USB2_BASE }
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IRQn_Type DCD_IRQn[] = { USB_OTG1_IRQn, USB_OTG2_IRQn };
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#endif
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#else
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// LPCOpen for 18xx & 43xx
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#include "chip.h"
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#define DCD_REGS_BASE { (dcd_registers_t*) LPC_USB0_BASE, (dcd_registers_t*) LPC_USB1_BASE }
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IRQn_Type DCD_IRQn[] = { USB0_IRQn, USB1_IRQn };
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#endif
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#if defined(__CORTEX_M) && __CORTEX_M == 7 && __DCACHE_PRESENT == 1
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#define CleanInvalidateDCache_by_Addr SCB_CleanInvalidateDCache_by_Addr
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#else
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#define CleanInvalidateDCache_by_Addr(_addr, _dsize)
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#endif
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//--------------------------------------------------------------------+
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@ -232,7 +224,7 @@ typedef struct
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/// thus there are 16 bytes padding free that we can make use of.
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//--------------------------------------------------------------------+
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uint8_t reserved[16];
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} dcd_qhd_t;
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} dcd_qhd_t;
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TU_VERIFY_STATIC( sizeof(dcd_qhd_t) == 64, "size is not correct");
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@ -240,23 +232,48 @@ TU_VERIFY_STATIC( sizeof(dcd_qhd_t) == 64, "size is not correct");
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// Variables
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//--------------------------------------------------------------------+
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#define QHD_MAX 12
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typedef struct
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{
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dcd_registers_t* regs; // registers
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const IRQn_Type irqnum; // IRQ number
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const uint8_t ep_count; // Max bi-directional Endpoints
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}dcd_controller_t;
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#if CFG_TUSB_MCU == OPT_MCU_MIMXRT10XX
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// Each endpoint with direction (IN/OUT) occupies a queue head
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// Therefore QHD_MAX is 2 x max endpoint count
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#define QHD_MAX (8*2)
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dcd_controller_t _dcd_controller[] =
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{
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// RT1010 and RT1020 only has 1 USB controller
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#if FSL_FEATURE_SOC_USBHS_COUNT == 1
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{ .regs = (dcd_registers_t*) USB_BASE , .irqnum = USB_OTG1_IRQn, .ep_count = 8 }
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#else
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{ .regs = (dcd_registers_t*) USB1_BASE, .irqnum = USB_OTG1_IRQn, .ep_count = 8 },
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{ .regs = (dcd_registers_t*) USB2_BASE, .irqnum = USB_OTG2_IRQn, .ep_count = 8 }
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#endif
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};
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#else
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#define QHD_MAX (6*2)
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dcd_controller_t _dcd_controller[] =
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{
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{ .regs = (dcd_registers_t*) LPC_USB0_BASE, .irqnum = USB0_IRQn, .ep_count = 6 },
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{ .regs = (dcd_registers_t*) LPC_USB1_BASE, .irqnum = USB1_IRQn, .ep_count = 4 }
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};
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#endif
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#define QTD_NEXT_INVALID 0x01
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typedef struct {
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// Must be at 2K alignment
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dcd_qhd_t qhd[QHD_MAX] TU_ATTR_ALIGNED(64);
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dcd_qtd_t qtd[QHD_MAX] TU_ATTR_ALIGNED(32);
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dcd_qtd_t qtd[QHD_MAX] TU_ATTR_ALIGNED(32); // for portability, TinyUSB only queue 1 TD for each Qhd
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}dcd_data_t;
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static dcd_data_t _dcd_data CFG_TUSB_MEM_SECTION TU_ATTR_ALIGNED(2048);
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static dcd_registers_t* DCD_REGS[] = DCD_REGS_BASE;
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#if defined(__CORTEX_M) && __CORTEX_M == 7 && __DCACHE_PRESENT == 1
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#define CleanInvalidateDCache_by_Addr SCB_CleanInvalidateDCache_by_Addr
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#else
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#define CleanInvalidateDCache_by_Addr(_addr, _dsize)
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#endif
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//--------------------------------------------------------------------+
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// CONTROLLER API
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@ -265,16 +282,14 @@ static dcd_registers_t* DCD_REGS[] = DCD_REGS_BASE;
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/// follows LPC43xx User Manual 23.10.3
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static void bus_reset(uint8_t rhport)
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{
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dcd_registers_t* dcd_reg = DCD_REGS[rhport];
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dcd_registers_t* dcd_reg = _dcd_controller[rhport].regs;
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// The reset value for all endpoint types is the control endpoint. If one endpoint
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// direction is enabled and the paired endpoint of opposite direction is disabled, then the
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// endpoint type of the unused direction must bechanged from the control type to any other
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// type (e.g. bulk). Leaving an unconfigured endpoint control will cause undefined behavior
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// endpoint type of the unused direction must be changed from the control type to any other
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// type (e.g. bulk). Leaving an un-configured endpoint control will cause undefined behavior
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// for the data PID tracking on the active endpoint.
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// USB0 has 5 but USB1 only has 3 non-control endpoints
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for( int i=1; i < (rhport ? 6 : 4); i++)
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for( int i=1; i < _dcd_controller[rhport].ep_count; i++)
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{
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dcd_reg->ENDPTCTRL[i] = (TUSB_XFER_BULK << 2) | (TUSB_XFER_BULK << 18);
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}
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@ -307,7 +322,7 @@ void dcd_init(uint8_t rhport)
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{
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tu_memclr(&_dcd_data, sizeof(dcd_data_t));
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dcd_registers_t* const dcd_reg = DCD_REGS[rhport];
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dcd_registers_t* const dcd_reg = _dcd_controller[rhport].regs;
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// Reset controller
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dcd_reg->USBCMD |= USBCMD_RESET;
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@ -332,12 +347,12 @@ void dcd_init(uint8_t rhport)
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void dcd_int_enable(uint8_t rhport)
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{
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NVIC_EnableIRQ(DCD_IRQn[rhport]);
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NVIC_EnableIRQ(_dcd_controller[rhport].irqnum);
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}
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void dcd_int_disable(uint8_t rhport)
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{
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NVIC_DisableIRQ(DCD_IRQn[rhport]);
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NVIC_DisableIRQ(_dcd_controller[rhport].irqnum);
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}
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void dcd_set_address(uint8_t rhport, uint8_t dev_addr)
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@ -345,7 +360,8 @@ void dcd_set_address(uint8_t rhport, uint8_t dev_addr)
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// Response with status first before changing device address
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dcd_edpt_xfer(rhport, tu_edpt_addr(0, TUSB_DIR_IN), NULL, 0);
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DCD_REGS[rhport]->DEVICEADDR = (dev_addr << 25) | TU_BIT(24);
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dcd_registers_t* dcd_reg = _dcd_controller[rhport].regs;
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dcd_reg->DEVICEADDR = (dev_addr << 25) | TU_BIT(24);
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}
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void dcd_set_config(uint8_t rhport, uint8_t config_num)
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@ -395,7 +411,8 @@ void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr)
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uint8_t const epnum = tu_edpt_number(ep_addr);
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uint8_t const dir = tu_edpt_dir(ep_addr);
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DCD_REGS[rhport]->ENDPTCTRL[epnum] |= ENDPTCTRL_STALL << (dir ? 16 : 0);
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dcd_registers_t* dcd_reg = _dcd_controller[rhport].regs;
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dcd_reg->ENDPTCTRL[epnum] |= ENDPTCTRL_STALL << (dir ? 16 : 0);
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}
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void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr)
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@ -404,8 +421,9 @@ void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr)
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uint8_t const dir = tu_edpt_dir(ep_addr);
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// data toggle also need to be reset
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DCD_REGS[rhport]->ENDPTCTRL[epnum] |= ENDPTCTRL_TOGGLE_RESET << ( dir ? 16 : 0 );
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DCD_REGS[rhport]->ENDPTCTRL[epnum] &= ~(ENDPTCTRL_STALL << ( dir ? 16 : 0));
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dcd_registers_t* dcd_reg = _dcd_controller[rhport].regs;
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dcd_reg->ENDPTCTRL[epnum] |= ENDPTCTRL_TOGGLE_RESET << ( dir ? 16 : 0 );
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dcd_reg->ENDPTCTRL[epnum] &= ~(ENDPTCTRL_STALL << ( dir ? 16 : 0));
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}
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bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc)
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@ -417,8 +435,8 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc)
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uint8_t const dir = tu_edpt_dir(p_endpoint_desc->bEndpointAddress);
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uint8_t const ep_idx = 2*epnum + dir;
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// USB0 has 5, USB1 has 3 non-control endpoints
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TU_ASSERT( epnum <= (rhport ? 3 : 5) );
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// Must not exceed max endpoint number
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TU_ASSERT( epnum < _dcd_controller[rhport].ep_count );
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//------------- Prepare Queue Head -------------//
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dcd_qhd_t * p_qhd = &_dcd_data.qhd[ep_idx];
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@ -431,13 +449,15 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc)
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CleanInvalidateDCache_by_Addr((uint32_t*) &_dcd_data, sizeof(dcd_data_t));
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// Enable EP Control
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DCD_REGS[rhport]->ENDPTCTRL[epnum] |= ((p_endpoint_desc->bmAttributes.xfer << 2) | ENDPTCTRL_ENABLE | ENDPTCTRL_TOGGLE_RESET) << (dir ? 16 : 0);
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dcd_registers_t* dcd_reg = _dcd_controller[rhport].regs;
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dcd_reg->ENDPTCTRL[epnum] |= ((p_endpoint_desc->bmAttributes.xfer << 2) | ENDPTCTRL_ENABLE | ENDPTCTRL_TOGGLE_RESET) << (dir ? 16 : 0);
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return true;
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}
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bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t total_bytes)
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{
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dcd_registers_t* dcd_reg = _dcd_controller[rhport].regs;
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uint8_t const epnum = tu_edpt_number(ep_addr);
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uint8_t const dir = tu_edpt_dir(ep_addr);
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uint8_t const ep_idx = 2*epnum + dir;
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@ -446,7 +466,7 @@ bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t t
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{
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// follows UM 24.10.8.1.1 Setup packet handling using setup lockout mechanism
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// wait until ENDPTSETUPSTAT before priming data/status in response TODO add time out
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while(DCD_REGS[rhport]->ENDPTSETUPSTAT & TU_BIT(0)) {}
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while(dcd_reg->ENDPTSETUPSTAT & TU_BIT(0)) {}
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}
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dcd_qhd_t * p_qhd = &_dcd_data.qhd[ep_idx];
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@ -464,7 +484,7 @@ bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t t
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CleanInvalidateDCache_by_Addr((uint32_t*) &_dcd_data, sizeof(dcd_data_t));
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// start transfer
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DCD_REGS[rhport]->ENDPTPRIME = TU_BIT( ep_idx2bit(ep_idx) ) ;
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dcd_reg->ENDPTPRIME = TU_BIT( ep_idx2bit(ep_idx) ) ;
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return true;
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}
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@ -474,7 +494,7 @@ bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t t
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//--------------------------------------------------------------------+
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void dcd_isr(uint8_t rhport)
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{
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dcd_registers_t* const dcd_reg = DCD_REGS[rhport];
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dcd_registers_t* const dcd_reg = _dcd_controller[rhport].regs;
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uint32_t const int_enable = dcd_reg->USBINTR;
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uint32_t const int_status = dcd_reg->USBSTS & int_enable;
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