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passkey_fw
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Merge branch 'master' into develop

This commit is contained in:
hathach 2020-01-09 21:31:01 +07:00
parent 0268f24227 99f76eaaaa
commit dd96be492f
26 changed files with 2137 additions and 23 deletions
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10
.github/workflows/build.yml vendored
View File

@ -52,12 +52,4 @@ jobs:
- name: Build - name: Build
run: python3 tools/build_all.py ${{ matrix.example }} run: python3 tools/build_all.py ${{ matrix.example }}
trigger-mynewt:
runs-on: ubuntu-latest
needs: build
steps:
- name: Trigger mynewt-tinyusb-example
shell: bash
run: |
curl -X POST -H "Authorization: token ${{ secrets.GH_REPO_TOKEN }}" -H "Accept: application/vnd.github.everest-preview+json" -H "Content-Type: application/json" --data '{"event_type": "rebuild"}' https://api.github.com/repos/hathach/mynewt-tinyusb-example/dispatches

3
.gitmodules vendored
View File

@ -19,3 +19,6 @@
[submodule "hw/mcu/microchip"] [submodule "hw/mcu/microchip"]
path = hw/mcu/microchip path = hw/mcu/microchip
url = https://github.com/hathach/microchip_driver.git url = https://github.com/hathach/microchip_driver.git
[submodule "hw/mcu/nuvoton"]
path = hw/mcu/nuvoton
url = https://github.com/majbthrd/nuc_driver.git

4
CONTRIBUTORS.md
View File

@ -23,6 +23,10 @@
* USBTMC class driver support with example * USBTMC class driver support with example
* Various improvement e.g Zero-length packet, Lint setup * Various improvement e.g Zero-length packet, Lint setup
* Board support for STM32F070RB Nucleo, STM32F303 Discovery * Board support for STM32F070RB Nucleo, STM32F303 Discovery
* **[Peter Lawrence](https://github.com/majbthrd)**
* Nuvoton NUC 121, 125, 126 device driver port
* Board support for NuTiny NUC121s, NUC125s, NUC126V
* **[Scott Shawcroft](https://github.com/tannewt)** * **[Scott Shawcroft](https://github.com/tannewt)**
* SAMD21 and SAMD51 device driver port * SAMD21 and SAMD51 device driver port

1
README.md
View File

@ -38,6 +38,7 @@ The stack supports the following MCUs
- **Sony:** CXD56 - **Sony:** CXD56
- **ST:** STM32 series: L0, F0, F1, F2, F3, F4, F7, H7 (device only) - **ST:** STM32 series: L0, F0, F1, F2, F3, F4, F7, H7 (device only)
- **[ValentyUSB](https://github.com/im-tomu/valentyusb)** eptri - **[ValentyUSB](https://github.com/im-tomu/valentyusb)** eptri
- **Nuvoton:** NUC121/NUC125, NUC126
[Here is the list of supported Boards](docs/boards.md) that can be used with provided examples. [Here is the list of supported Boards](docs/boards.md) that can be used with provided examples.

8
docs/boards.md
View File

@ -7,7 +7,7 @@ The board support code is only used for self-contained examples and testing. It
## Supported Boards ## Supported Boards
This code base already had supported for a handful of following boards This code base already had supported for a handful of following boards (sorted alphabetically)
### MicroChip SAMD ### MicroChip SAMD
@ -26,6 +26,12 @@ This code base already had supported for a handful of following boards
- [Nordic nRF52840 Dongle (aka pca10059)](https://www.nordicsemi.com/Software-and-Tools/Development-Kits/nRF52840-Dongle) - [Nordic nRF52840 Dongle (aka pca10059)](https://www.nordicsemi.com/Software-and-Tools/Development-Kits/nRF52840-Dongle)
- [Nordic nRF52833 Development Kit (aka pca10100)](https://www.nordicsemi.com/Software-and-Tools/Development-Kits/nRF52833-DK) - [Nordic nRF52833 Development Kit (aka pca10100)](https://www.nordicsemi.com/Software-and-Tools/Development-Kits/nRF52833-DK)
### Nuvoton
- [NuTiny NUC121S](https://direct.nuvoton.com/en/nutiny-nuc121s)
- [NuTiny NUC125S](https://direct.nuvoton.com/en/nutiny-nuc125s)
- [NuTiny NUC126V](https://direct.nuvoton.com/en/nutiny-nuc126v)
### NXP iMX RT ### NXP iMX RT
- [MIMX RT1010 Evaluation Kit](https://www.nxp.com/design/development-boards/i.mx-evaluation-and-development-boards/i.mx-rt1010-evaluation-kit:MIMXRT1010-EVK) - [MIMX RT1010 Evaluation Kit](https://www.nxp.com/design/development-boards/i.mx-evaluation-and-development-boards/i.mx-rt1010-evaluation-kit:MIMXRT1010-EVK)

2
examples/readme.md
View File

@ -12,7 +12,7 @@ $ cd tinyusb
TinyUSB examples includes external repos aka submodules to provide low-level MCU peripheral's driver to compile with. Therefore we will firstly fetch those mcu driver repo by running this command in the top folder repo TinyUSB examples includes external repos aka submodules to provide low-level MCU peripheral's driver to compile with. Therefore we will firstly fetch those mcu driver repo by running this command in the top folder repo
``` ```
$ git submodule update --init --rescursive $ git submodule update --init --recursive
``` ```
It will takes a bit of time due to the number of supported MCUs, luckily we only need to do this once. It will takes a bit of time due to the number of supported MCUs, luckily we only need to do this once.

3
hw/bsp/mimxrt1010_evk/board.mk
View File

@ -11,7 +11,8 @@ CFLAGS += \
-DCFG_TUSB_MCU=OPT_MCU_MIMXRT10XX -DCFG_TUSB_MCU=OPT_MCU_MIMXRT10XX
# mcu driver cause following warnings # mcu driver cause following warnings
CFLAGS += -Wno-error=unused-parameter -Wno-error=implicit-fallthrough= # CFLAGS += -Wno-error=unused-parameter -Wno-error=implicit-fallthrough=
CFLAGS += -Wno-error=unused-parameter
MCU_DIR = hw/mcu/nxp/sdk/devices/MIMXRT1011 MCU_DIR = hw/mcu/nxp/sdk/devices/MIMXRT1011

55
hw/bsp/nutiny_nuc121s/board.mk Normal file
View File

@ -0,0 +1,55 @@
CFLAGS += \
-flto \
-mthumb \
-mabi=aapcs-linux \
-mcpu=cortex-m0 \
-D__ARM_FEATURE_DSP=0 \
-DUSE_ASSERT=0 \
-DCFG_EXAMPLE_MSC_READONLY \
-DCFG_TUSB_MCU=OPT_MCU_NUC121
# All source paths should be relative to the top level.
LD_FILE = hw/bsp/nutiny_nuc121s/nuc121_flash.ld
SRC_C += \
hw/mcu/nuvoton/nuc121_125/Device/Nuvoton/NUC121/Source/system_NUC121.c \
hw/mcu/nuvoton/nuc121_125/StdDriver/src/adc.c \
hw/mcu/nuvoton/nuc121_125/StdDriver/src/bpwm.c \
hw/mcu/nuvoton/nuc121_125/StdDriver/src/clk.c \
hw/mcu/nuvoton/nuc121_125/StdDriver/src/fmc.c \
hw/mcu/nuvoton/nuc121_125/StdDriver/src/gpio.c \
hw/mcu/nuvoton/nuc121_125/StdDriver/src/i2c.c \
hw/mcu/nuvoton/nuc121_125/StdDriver/src/pdma.c \
hw/mcu/nuvoton/nuc121_125/StdDriver/src/pwm.c \
hw/mcu/nuvoton/nuc121_125/StdDriver/src/spi_i2s.c \
hw/mcu/nuvoton/nuc121_125/StdDriver/src/sys.c \
hw/mcu/nuvoton/nuc121_125/StdDriver/src/timer.c \
hw/mcu/nuvoton/nuc121_125/StdDriver/src/uart.c \
hw/mcu/nuvoton/nuc121_125/StdDriver/src/usbd.c \
hw/mcu/nuvoton/nuc121_125/StdDriver/src/usci_i2c.c \
hw/mcu/nuvoton/nuc121_125/StdDriver/src/usci_spi.c \
hw/mcu/nuvoton/nuc121_125/StdDriver/src/usci_uart.c \
hw/mcu/nuvoton/nuc121_125/StdDriver/src/wdt.c \
hw/mcu/nuvoton/nuc121_125/StdDriver/src/wwdt.c
SRC_S += \
hw/mcu/nuvoton/nuc121_125/Device/Nuvoton/NUC121/Source/GCC/startup_NUC121.S
INC += \
$(TOP)/hw/mcu/nuvoton/nuc121_125/Device/Nuvoton/NUC121/Include \
$(TOP)/hw/mcu/nuvoton/nuc121_125/StdDriver/inc \
$(TOP)/hw/mcu/nuvoton/nuc121_125/CMSIS/Include
# For TinyUSB port source
VENDOR = nuvoton
CHIP_FAMILY = nuc121
# For freeRTOS port source
FREERTOS_PORT = ARM_CM0
# For flash-jlink target
JLINK_DEVICE = NUC121SC2AE
JLINK_IF = swd
# flash using jlink
flash: flash-jlink

195
hw/bsp/nutiny_nuc121s/nuc121_flash.ld Normal file
View File

@ -0,0 +1,195 @@
/* Linker script to configure memory regions. */
MEMORY
{
FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x8000 /* 32k */
RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x2000 /* 8k */
}
/* Library configurations */
GROUP(libgcc.a libc.a libm.a libnosys.a)
/* Linker script to place sections and symbol values. Should be used together
* with other linker script that defines memory regions FLASH and RAM.
* It references following symbols, which must be defined in code:
* Reset_Handler : Entry of reset handler
*
* It defines following symbols, which code can use without definition:
* __exidx_start
* __exidx_end
* __copy_table_start__
* __copy_table_end__
* __zero_table_start__
* __zero_table_end__
* __etext
* __data_start__
* __preinit_array_start
* __preinit_array_end
* __init_array_start
* __init_array_end
* __fini_array_start
* __fini_array_end
* __data_end__
* __bss_start__
* __bss_end__
* __end__
* end
* __HeapLimit
* __StackLimit
* __StackTop
* __stack
* __Vectors_End
* __Vectors_Size
*/
ENTRY(Reset_Handler)
SECTIONS
{
.text :
{
KEEP(*(.vectors))
__Vectors_End = .;
__Vectors_Size = __Vectors_End - __Vectors;
__end__ = .;
*(.text*)
KEEP(*(.init))
KEEP(*(.fini))
/* .ctors */
*crtbegin.o(.ctors)
*crtbegin?.o(.ctors)
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
*(SORT(.ctors.*))
*(.ctors)
/* .dtors */
*crtbegin.o(.dtors)
*crtbegin?.o(.dtors)
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
*(SORT(.dtors.*))
*(.dtors)
*(.rodata*)
KEEP(*(.eh_frame*))
} > FLASH
.ARM.extab :
{
*(.ARM.extab* .gnu.linkonce.armextab.*)
} > FLASH
__exidx_start = .;
.ARM.exidx :
{
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
} > FLASH
__exidx_end = .;
/* To copy multiple ROM to RAM sections,
* uncomment .copy.table section and,
* define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */
/*
.copy.table :
{
. = ALIGN(4);
__copy_table_start__ = .;
LONG (__etext)
LONG (__data_start__)
LONG (__data_end__ - __data_start__)
LONG (__etext2)
LONG (__data2_start__)
LONG (__data2_end__ - __data2_start__)
__copy_table_end__ = .;
} > FLASH
*/
/* To clear multiple BSS sections,
* uncomment .zero.table section and,
* define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */
/*
.zero.table :
{
. = ALIGN(4);
__zero_table_start__ = .;
LONG (__bss_start__)
LONG (__bss_end__ - __bss_start__)
LONG (__bss2_start__)
LONG (__bss2_end__ - __bss2_start__)
__zero_table_end__ = .;
} > FLASH
*/
__etext = .;
.data : AT (__etext)
{
__data_start__ = .;
*(vtable)
*(.data*)
. = ALIGN(4);
/* preinit data */
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE_HIDDEN (__preinit_array_end = .);
. = ALIGN(4);
/* init data */
PROVIDE_HIDDEN (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
KEEP(*(.init_array))
PROVIDE_HIDDEN (__init_array_end = .);
. = ALIGN(4);
/* finit data */
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
KEEP(*(.fini_array))
PROVIDE_HIDDEN (__fini_array_end = .);
KEEP(*(.jcr*))
. = ALIGN(4);
/* All data end */
__data_end__ = .;
} > RAM
.bss :
{
. = ALIGN(4);
__bss_start__ = .;
*(.bss*)
*(COMMON)
. = ALIGN(4);
__bss_end__ = .;
} > RAM
.heap (COPY):
{
__HeapBase = .;
__end__ = .;
end = __end__;
KEEP(*(.heap*))
__HeapLimit = .;
} > RAM
/* .stack_dummy section doesn't contains any symbols. It is only
* used for linker to calculate size of stack sections, and assign
* values to stack symbols later */
.stack_dummy (COPY):
{
KEEP(*(.stack*))
} > RAM
/* Set stack top to end of RAM, and stack limit move down by
* size of stack_dummy section */
__StackTop = ORIGIN(RAM) + LENGTH(RAM);
__StackLimit = __StackTop - SIZEOF(.stack_dummy);
PROVIDE(__stack = __StackTop);
/* Check if data + heap + stack exceeds RAM limit */
ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
}

102
hw/bsp/nutiny_nuc121s/nutiny_nuc121.c Normal file
View File

@ -0,0 +1,102 @@
/*
* The MIT License (MIT)
*
* Copyright (c) 2019 Ha Thach (tinyusb.org)
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*
* This file is part of the TinyUSB stack.
*/
#include "bsp/board.h"
#include "NuMicro.h"
#include "clk.h"
#include "sys.h"
void board_init(void)
{
/* Unlock protected registers */
SYS_UnlockReg();
/*---------------------------------------------------------------------------------------------------------*/
/* Init System Clock */
/*---------------------------------------------------------------------------------------------------------*/
/* Enable Internal HIRC 48 MHz clock */
CLK_EnableXtalRC(CLK_PWRCTL_HIRCEN);
/* Waiting for Internal RC clock ready */
CLK_WaitClockReady(CLK_STATUS_HIRCSTB_Msk);
/* Switch HCLK clock source to Internal HIRC and HCLK source divide 1 */
CLK_SetHCLK(CLK_CLKSEL0_HCLKSEL_HIRC, CLK_CLKDIV0_HCLK(1));
/* Enable module clock */
CLK_EnableModuleClock(USBD_MODULE);
/* Select module clock source */
CLK_SetModuleClock(USBD_MODULE, CLK_CLKSEL3_USBDSEL_HIRC, CLK_CLKDIV0_USB(1));
/* Enable module clock */
CLK_EnableModuleClock(USBD_MODULE);
#if CFG_TUSB_OS == OPT_OS_NONE
// 1ms tick timer
SysTick_Config(48000000 / 1000);
#endif
}
#if CFG_TUSB_OS == OPT_OS_NONE
volatile uint32_t system_ticks = 0;
void SysTick_Handler (void)
{
system_ticks++;
}
uint32_t board_millis(void)
{
return system_ticks;
}
#endif
//--------------------------------------------------------------------+
// Board porting API
//--------------------------------------------------------------------+
void board_led_write(bool state)
{
(void)(state);
}
uint32_t board_button_read(void)
{
return 0;
}
int board_uart_read(uint8_t* buf, int len)
{
(void) buf; (void) len;
return 0;
}
int board_uart_write(void const * buf, int len)
{
(void) buf; (void) len;
return 0;
}

38
hw/bsp/nutiny_nuc125s/board.mk Normal file
View File

@ -0,0 +1,38 @@
CFLAGS += \
-flto \
-mthumb \
-mabi=aapcs-linux \
-mcpu=cortex-m0 \
-D__ARM_FEATURE_DSP=0 \
-DUSE_ASSERT=0 \
-DCFG_EXAMPLE_MSC_READONLY \
-DCFG_TUSB_MCU=OPT_MCU_NUC121
# All source paths should be relative to the top level.
LD_FILE = hw/bsp/nutiny_nuc125s/nuc125_flash.ld
SRC_C += \
hw/mcu/nuvoton/nuc121_125/Device/Nuvoton/NUC121/Source/system_NUC121.c \
hw/mcu/nuvoton/nuc121_125/StdDriver/src/clk.c
SRC_S += \
hw/mcu/nuvoton/nuc121_125/Device/Nuvoton/NUC121/Source/GCC/startup_NUC121.S
INC += \
$(TOP)/hw/mcu/nuvoton/nuc121_125/Device/Nuvoton/NUC121/Include \
$(TOP)/hw/mcu/nuvoton/nuc121_125/StdDriver/inc \
$(TOP)/hw/mcu/nuvoton/nuc121_125/CMSIS/Include
# For TinyUSB port source
VENDOR = nuvoton
CHIP_FAMILY = nuc121
# For freeRTOS port source
FREERTOS_PORT = ARM_CM0
# For flash-jlink target
JLINK_DEVICE = NUC125SC2AE
JLINK_IF = swd
# flash using jlink
flash: flash-jlink

195
hw/bsp/nutiny_nuc125s/nuc125_flash.ld Normal file
View File

@ -0,0 +1,195 @@
/* Linker script to configure memory regions. */
MEMORY
{
FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x8000 /* 32k */
RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x2000 /* 8k */
}
/* Library configurations */
GROUP(libgcc.a libc.a libm.a libnosys.a)
/* Linker script to place sections and symbol values. Should be used together
* with other linker script that defines memory regions FLASH and RAM.
* It references following symbols, which must be defined in code:
* Reset_Handler : Entry of reset handler
*
* It defines following symbols, which code can use without definition:
* __exidx_start
* __exidx_end
* __copy_table_start__
* __copy_table_end__
* __zero_table_start__
* __zero_table_end__
* __etext
* __data_start__
* __preinit_array_start
* __preinit_array_end
* __init_array_start
* __init_array_end
* __fini_array_start
* __fini_array_end
* __data_end__
* __bss_start__
* __bss_end__
* __end__
* end
* __HeapLimit
* __StackLimit
* __StackTop
* __stack
* __Vectors_End
* __Vectors_Size
*/
ENTRY(Reset_Handler)
SECTIONS
{
.text :
{
KEEP(*(.vectors))
__Vectors_End = .;
__Vectors_Size = __Vectors_End - __Vectors;
__end__ = .;
*(.text*)
KEEP(*(.init))
KEEP(*(.fini))
/* .ctors */
*crtbegin.o(.ctors)
*crtbegin?.o(.ctors)
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
*(SORT(.ctors.*))
*(.ctors)
/* .dtors */
*crtbegin.o(.dtors)
*crtbegin?.o(.dtors)
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
*(SORT(.dtors.*))
*(.dtors)
*(.rodata*)
KEEP(*(.eh_frame*))
} > FLASH
.ARM.extab :
{
*(.ARM.extab* .gnu.linkonce.armextab.*)
} > FLASH
__exidx_start = .;
.ARM.exidx :
{
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
} > FLASH
__exidx_end = .;
/* To copy multiple ROM to RAM sections,
* uncomment .copy.table section and,
* define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */
/*
.copy.table :
{
. = ALIGN(4);
__copy_table_start__ = .;
LONG (__etext)
LONG (__data_start__)
LONG (__data_end__ - __data_start__)
LONG (__etext2)
LONG (__data2_start__)
LONG (__data2_end__ - __data2_start__)
__copy_table_end__ = .;
} > FLASH
*/
/* To clear multiple BSS sections,
* uncomment .zero.table section and,
* define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */
/*
.zero.table :
{
. = ALIGN(4);
__zero_table_start__ = .;
LONG (__bss_start__)
LONG (__bss_end__ - __bss_start__)
LONG (__bss2_start__)
LONG (__bss2_end__ - __bss2_start__)
__zero_table_end__ = .;
} > FLASH
*/
__etext = .;
.data : AT (__etext)
{
__data_start__ = .;
*(vtable)
*(.data*)
. = ALIGN(4);
/* preinit data */
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE_HIDDEN (__preinit_array_end = .);
. = ALIGN(4);
/* init data */
PROVIDE_HIDDEN (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
KEEP(*(.init_array))
PROVIDE_HIDDEN (__init_array_end = .);
. = ALIGN(4);
/* finit data */
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
KEEP(*(.fini_array))
PROVIDE_HIDDEN (__fini_array_end = .);
KEEP(*(.jcr*))
. = ALIGN(4);
/* All data end */
__data_end__ = .;
} > RAM
.bss :
{
. = ALIGN(4);
__bss_start__ = .;
*(.bss*)
*(COMMON)
. = ALIGN(4);
__bss_end__ = .;
} > RAM
.heap (COPY):
{
__HeapBase = .;
__end__ = .;
end = __end__;
KEEP(*(.heap*))
__HeapLimit = .;
} > RAM
/* .stack_dummy section doesn't contains any symbols. It is only
* used for linker to calculate size of stack sections, and assign
* values to stack symbols later */
.stack_dummy (COPY):
{
KEEP(*(.stack*))
} > RAM
/* Set stack top to end of RAM, and stack limit move down by
* size of stack_dummy section */
__StackTop = ORIGIN(RAM) + LENGTH(RAM);
__StackLimit = __StackTop - SIZEOF(.stack_dummy);
PROVIDE(__stack = __StackTop);
/* Check if data + heap + stack exceeds RAM limit */
ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
}

102
hw/bsp/nutiny_nuc125s/nutiny_nuc125.c Normal file
View File

@ -0,0 +1,102 @@
/*
* The MIT License (MIT)
*
* Copyright (c) 2019 Ha Thach (tinyusb.org)
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*
* This file is part of the TinyUSB stack.
*/
#include "bsp/board.h"
#include "NuMicro.h"
#include "clk.h"
#include "sys.h"
void board_init(void)
{
/* Unlock protected registers */
SYS_UnlockReg();
/*---------------------------------------------------------------------------------------------------------*/
/* Init System Clock */
/*---------------------------------------------------------------------------------------------------------*/
/* Enable Internal HIRC 48 MHz clock */
CLK_EnableXtalRC(CLK_PWRCTL_HIRCEN);
/* Waiting for Internal RC clock ready */
CLK_WaitClockReady(CLK_STATUS_HIRCSTB_Msk);
/* Switch HCLK clock source to Internal HIRC and HCLK source divide 1 */
CLK_SetHCLK(CLK_CLKSEL0_HCLKSEL_HIRC, CLK_CLKDIV0_HCLK(1));
/* Enable module clock */
CLK_EnableModuleClock(USBD_MODULE);
/* Select module clock source */
CLK_SetModuleClock(USBD_MODULE, CLK_CLKSEL3_USBDSEL_HIRC, CLK_CLKDIV0_USB(1));
/* Enable module clock */
CLK_EnableModuleClock(USBD_MODULE);
#if CFG_TUSB_OS == OPT_OS_NONE
// 1ms tick timer
SysTick_Config(48000000 / 1000);
#endif
}
#if CFG_TUSB_OS == OPT_OS_NONE
volatile uint32_t system_ticks = 0;
void SysTick_Handler (void)
{
system_ticks++;
}
uint32_t board_millis(void)
{
return system_ticks;
}
#endif
//--------------------------------------------------------------------+
// Board porting API
//--------------------------------------------------------------------+
void board_led_write(bool state)
{
(void)(state);
}
uint32_t board_button_read(void)
{
return 0;
}
int board_uart_read(uint8_t* buf, int len)
{
(void) buf; (void) len;
return 0;
}
int board_uart_write(void const * buf, int len)
{
(void) buf; (void) len;
return 0;
}

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CFLAGS += \
-flto \
-mthumb \
-mabi=aapcs-linux \
-mcpu=cortex-m0 \
-D__ARM_FEATURE_DSP=0 \
-DUSE_ASSERT=0 \
-D__CORTEX_SC=0 \
-DCFG_TUSB_MCU=OPT_MCU_NUC126
# All source paths should be relative to the top level.
LD_FILE = hw/bsp/nutiny_nuc126v/nuc126_flash.ld
SRC_C += \
hw/mcu/nuvoton/nuc126/Device/Nuvoton/NUC126/Source/system_NUC126.c \
hw/mcu/nuvoton/nuc126/StdDriver/src/acmp.c \
hw/mcu/nuvoton/nuc126/StdDriver/src/adc.c \
hw/mcu/nuvoton/nuc126/StdDriver/src/clk.c \
hw/mcu/nuvoton/nuc126/StdDriver/src/crc.c \
hw/mcu/nuvoton/nuc126/StdDriver/src/ebi.c \
hw/mcu/nuvoton/nuc126/StdDriver/src/fmc.c \
hw/mcu/nuvoton/nuc126/StdDriver/src/gpio.c \
hw/mcu/nuvoton/nuc126/StdDriver/src/pdma.c \
hw/mcu/nuvoton/nuc126/StdDriver/src/pwm.c \
hw/mcu/nuvoton/nuc126/StdDriver/src/rtc.c \
hw/mcu/nuvoton/nuc126/StdDriver/src/sc.c \
hw/mcu/nuvoton/nuc126/StdDriver/src/scuart.c \
hw/mcu/nuvoton/nuc126/StdDriver/src/spi.c \
hw/mcu/nuvoton/nuc126/StdDriver/src/sys.c \
hw/mcu/nuvoton/nuc126/StdDriver/src/timer.c \
hw/mcu/nuvoton/nuc126/StdDriver/src/timer_pwm.c \
hw/mcu/nuvoton/nuc126/StdDriver/src/uart.c \
hw/mcu/nuvoton/nuc126/StdDriver/src/usbd.c \
hw/mcu/nuvoton/nuc126/StdDriver/src/usci_spi.c \
hw/mcu/nuvoton/nuc126/StdDriver/src/usci_uart.c \
hw/mcu/nuvoton/nuc126/StdDriver/src/wdt.c \
hw/mcu/nuvoton/nuc126/StdDriver/src/wwdt.c
SRC_S += \
hw/mcu/nuvoton/nuc126/Device/Nuvoton/NUC126/Source/GCC/startup_NUC126.S
INC += \
$(TOP)/hw/mcu/nuvoton/nuc126/Device/Nuvoton/NUC126/Include \
$(TOP)/hw/mcu/nuvoton/nuc126/StdDriver/inc \
$(TOP)/hw/mcu/nuvoton/nuc126/CMSIS/Include
# For TinyUSB port source
VENDOR = nuvoton
CHIP_FAMILY = nuc121
# For freeRTOS port source
FREERTOS_PORT = ARM_CM0
# For flash-jlink target
JLINK_DEVICE = NUC126VG4AE
JLINK_IF = swd
# flash using jlink
flash: flash-jlink

195
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/* Linker script to configure memory regions. */
MEMORY
{
FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x40000 /* 256k */
RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x5000 /* 20k */
}
/* Library configurations */
GROUP(libgcc.a libc.a libm.a libnosys.a)
/* Linker script to place sections and symbol values. Should be used together
* with other linker script that defines memory regions FLASH and RAM.
* It references following symbols, which must be defined in code:
* Reset_Handler : Entry of reset handler
*
* It defines following symbols, which code can use without definition:
* __exidx_start
* __exidx_end
* __copy_table_start__
* __copy_table_end__
* __zero_table_start__
* __zero_table_end__
* __etext
* __data_start__
* __preinit_array_start
* __preinit_array_end
* __init_array_start
* __init_array_end
* __fini_array_start
* __fini_array_end
* __data_end__
* __bss_start__
* __bss_end__
* __end__
* end
* __HeapLimit
* __StackLimit
* __StackTop
* __stack
* __Vectors_End
* __Vectors_Size
*/
ENTRY(Reset_Handler)
SECTIONS
{
.text :
{
KEEP(*(.vectors))
__Vectors_End = .;
__Vectors_Size = __Vectors_End - __Vectors;
__end__ = .;
*(.text*)
KEEP(*(.init))
KEEP(*(.fini))
/* .ctors */
*crtbegin.o(.ctors)
*crtbegin?.o(.ctors)
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
*(SORT(.ctors.*))
*(.ctors)
/* .dtors */
*crtbegin.o(.dtors)
*crtbegin?.o(.dtors)
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
*(SORT(.dtors.*))
*(.dtors)
*(.rodata*)
KEEP(*(.eh_frame*))
} > FLASH
.ARM.extab :
{
*(.ARM.extab* .gnu.linkonce.armextab.*)
} > FLASH
__exidx_start = .;
.ARM.exidx :
{
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
} > FLASH
__exidx_end = .;
/* To copy multiple ROM to RAM sections,
* uncomment .copy.table section and,
* define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */
/*
.copy.table :
{
. = ALIGN(4);
__copy_table_start__ = .;
LONG (__etext)
LONG (__data_start__)
LONG (__data_end__ - __data_start__)
LONG (__etext2)
LONG (__data2_start__)
LONG (__data2_end__ - __data2_start__)
__copy_table_end__ = .;
} > FLASH
*/
/* To clear multiple BSS sections,
* uncomment .zero.table section and,
* define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */
/*
.zero.table :
{
. = ALIGN(4);
__zero_table_start__ = .;
LONG (__bss_start__)
LONG (__bss_end__ - __bss_start__)
LONG (__bss2_start__)
LONG (__bss2_end__ - __bss2_start__)
__zero_table_end__ = .;
} > FLASH
*/
__etext = .;
.data : AT (__etext)
{
__data_start__ = .;
*(vtable)
*(.data*)
. = ALIGN(4);
/* preinit data */
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE_HIDDEN (__preinit_array_end = .);
. = ALIGN(4);
/* init data */
PROVIDE_HIDDEN (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
KEEP(*(.init_array))
PROVIDE_HIDDEN (__init_array_end = .);
. = ALIGN(4);
/* finit data */
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
KEEP(*(.fini_array))
PROVIDE_HIDDEN (__fini_array_end = .);
KEEP(*(.jcr*))
. = ALIGN(4);
/* All data end */
__data_end__ = .;
} > RAM
.bss :
{
. = ALIGN(4);
__bss_start__ = .;
*(.bss*)
*(COMMON)
. = ALIGN(4);
__bss_end__ = .;
} > RAM
.heap (COPY):
{
__HeapBase = .;
__end__ = .;
end = __end__;
KEEP(*(.heap*))
__HeapLimit = .;
} > RAM
/* .stack_dummy section doesn't contains any symbols. It is only
* used for linker to calculate size of stack sections, and assign
* values to stack symbols later */
.stack_dummy (COPY):
{
KEEP(*(.stack*))
} > RAM
/* Set stack top to end of RAM, and stack limit move down by
* size of stack_dummy section */
__StackTop = ORIGIN(RAM) + LENGTH(RAM);
__StackLimit = __StackTop - SIZEOF(.stack_dummy);
PROVIDE(__stack = __StackTop);
/* Check if data + heap + stack exceeds RAM limit */
ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
}

133
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/*
* The MIT License (MIT)
*
* Copyright (c) 2019 Ha Thach (tinyusb.org)
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*
* This file is part of the TinyUSB stack.
*/
#include "bsp/board.h"
#include "NuMicro.h"
#include "clk.h"
#include "sys.h"
#define CRYSTAL_LESS /* system will be 48MHz when defined, otherwise, system is 72MHz */
#define HIRC48_AUTO_TRIM SYS_IRCTCTL1_REFCKSEL_Msk | (1UL << SYS_IRCTCTL1_LOOPSEL_Pos) | (2UL << SYS_IRCTCTL1_FREQSEL_Pos)
#define TRIM_INIT (SYS_BASE+0x118)
void board_init(void)
{
/* Unlock protected registers */
SYS_UnlockReg();
/*---------------------------------------------------------------------------------------------------------*/
/* Init System Clock */
/*---------------------------------------------------------------------------------------------------------*/
/* Enable Internal RC 22.1184 MHz clock */
CLK_EnableXtalRC(CLK_PWRCTL_HIRCEN_Msk);
/* Waiting for Internal RC clock ready */
CLK_WaitClockReady(CLK_STATUS_HIRCSTB_Msk);
/* Switch HCLK clock source to Internal RC and HCLK source divide 1 */
CLK_SetHCLK(CLK_CLKSEL0_HCLKSEL_HIRC, CLK_CLKDIV0_HCLK(1));
#ifndef CRYSTAL_LESS
/* Enable external XTAL 12 MHz clock */
CLK_EnableXtalRC(CLK_PWRCTL_HXTEN_Msk);
/* Waiting for external XTAL clock ready */
CLK_WaitClockReady(CLK_STATUS_HXTSTB_Msk);
/* Set core clock */
CLK_SetCoreClock(72000000);
/* Use HIRC as UART clock source */
CLK_SetModuleClock(UART0_MODULE, CLK_CLKSEL1_UARTSEL_HIRC, CLK_CLKDIV0_UART(1));
/* Use PLL as USB clock source */
CLK_SetModuleClock(USBD_MODULE, CLK_CLKSEL3_USBDSEL_PLL, CLK_CLKDIV0_USB(3));
#else
/* Enable Internal RC 48MHz clock */
CLK_EnableXtalRC(CLK_PWRCTL_HIRC48EN_Msk);
/* Waiting for Internal RC clock ready */
CLK_WaitClockReady(CLK_STATUS_HIRC48STB_Msk);
/* Switch HCLK clock source to Internal RC and HCLK source divide 1 */
CLK_SetHCLK(CLK_CLKSEL0_HCLKSEL_HIRC48, CLK_CLKDIV0_HCLK(1));
/* Use HIRC as UART clock source */
CLK_SetModuleClock(UART0_MODULE, CLK_CLKSEL1_UARTSEL_HIRC, CLK_CLKDIV0_UART(1));
/* Use HIRC48 as USB clock source */
CLK_SetModuleClock(USBD_MODULE, CLK_CLKSEL3_USBDSEL_HIRC48, CLK_CLKDIV0_USB(1));
#endif
/* Enable module clock */
CLK_EnableModuleClock(USBD_MODULE);
#if CFG_TUSB_OS == OPT_OS_NONE
// 1ms tick timer
SysTick_Config(48000000 / 1000);
#endif
}
#if CFG_TUSB_OS == OPT_OS_NONE
volatile uint32_t system_ticks = 0;
void SysTick_Handler (void)
{
system_ticks++;
}
uint32_t board_millis(void)
{
return system_ticks;
}
#endif
//--------------------------------------------------------------------+
// Board porting API
//--------------------------------------------------------------------+
void board_led_write(bool state)
{
(void)(state);
}
uint32_t board_button_read(void)
{
return 0;
}
int board_uart_read(uint8_t* buf, int len)
{
(void) buf; (void) len;
return 0;
}
int board_uart_write(void const * buf, int len)
{
(void) buf; (void) len;
return 0;
}

36
hw/bsp/teensy_40/board.h Normal file
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/*
* The MIT License (MIT)
*
* Copyright (c) 2019, Ha Thach (tinyusb.org)
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*
* This file is part of the TinyUSB stack.
*/
#ifndef BOARD_H_
#define BOARD_H_
// required since iMX RT10xx SDK include this file for board size
#define BOARD_FLASH_SIZE (2 * 1024 * 1024)
#endif /* BOARD_H_ */

53
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CFLAGS += \
-mthumb \
-mabi=aapcs \
-mcpu=cortex-m7 \
-mfloat-abi=hard \
-mfpu=fpv5-d16 \
-D__ARMVFP__=0 -D__ARMFPV5__=0\
-DCPU_MIMXRT1062DVL6A \
-DXIP_EXTERNAL_FLASH=1 \
-DXIP_BOOT_HEADER_ENABLE=1 \
-DCFG_TUSB_MCU=OPT_MCU_MIMXRT10XX
# mcu driver cause following warnings
#CFLAGS += -Wno-error=float-equal -Wno-error=nested-externs
CFLAGS += -Wno-error=unused-parameter
MCU_DIR = hw/mcu/nxp/sdk/devices/MIMXRT1062
# All source paths should be relative to the top level.
LD_FILE = $(MCU_DIR)/gcc/MIMXRT1062xxxxx_flexspi_nor.ld
SRC_C += \
$(MCU_DIR)/system_MIMXRT1062.c \
$(MCU_DIR)/xip/fsl_flexspi_nor_boot.c \
$(MCU_DIR)/project_template/clock_config.c \
$(MCU_DIR)/drivers/fsl_clock.c \
$(MCU_DIR)/drivers/fsl_gpio.c \
$(MCU_DIR)/drivers/fsl_common.c \
$(MCU_DIR)/drivers/fsl_lpuart.c
INC += \
$(TOP)/hw/bsp/$(BOARD) \
$(TOP)/$(MCU_DIR)/../../CMSIS/Include \
$(TOP)/$(MCU_DIR) \
$(TOP)/$(MCU_DIR)/drivers \
$(TOP)/$(MCU_DIR)/project_template \
SRC_S += $(MCU_DIR)/gcc/startup_MIMXRT1062.S
# For TinyUSB port source
VENDOR = nxp
CHIP_FAMILY = transdimension
# For freeRTOS port source
FREERTOS_PORT = ARM_CM7
# For flash-jlink target
JLINK_DEVICE = MIMXRT1062xxx6A
JLINK_IF = swd
# flash by copying bin file to DAP Mass Storage
flash: $(BUILD)/$(BOARD)-firmware.bin
cp $< /media/$(USER)/RT1060-EVK/

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/*
* The MIT License (MIT)
*
* Copyright (c) 2018, hathach (tinyusb.org)
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*
* This file is part of the TinyUSB stack.
*/
#include "../board.h"
#include "fsl_device_registers.h"
#include "fsl_gpio.h"
#include "fsl_iomuxc.h"
#include "fsl_clock.h"
#include "fsl_lpuart.h"
#include "clock_config.h"
#define LED_PINMUX IOMUXC_GPIO_B0_03_GPIO2_IO03 // D13
#define LED_PORT GPIO2
#define LED_PIN 3
#define LED_STATE_ON 0
// no button
#define BUTTON_PINMUX IOMUXC_GPIO_B0_01_GPIO2_IO01 // D12
#define BUTTON_PORT GPIO2
#define BUTTON_PIN 1
#define BUTTON_STATE_ACTIVE 0
// UART
#define UART_PORT LPUART6
#define UART_RX_PINMUX IOMUXC_GPIO_AD_B0_03_LPUART6_RX // D0
#define UART_TX_PINMUX IOMUXC_GPIO_AD_B0_02_LPUART6_TX // D1
const uint8_t dcd_data[] = { 0x00 };
void board_init(void)
{
// Init clock
BOARD_BootClockRUN();
SystemCoreClockUpdate();
// Enable IOCON clock
CLOCK_EnableClock(kCLOCK_Iomuxc);
#if CFG_TUSB_OS == OPT_OS_NONE
// 1ms tick timer
SysTick_Config(SystemCoreClock / 1000);
#elif CFG_TUSB_OS == OPT_OS_FREERTOS
// If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher )
// NVIC_SetPriority(USB0_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY );
#endif
// LED
IOMUXC_SetPinMux( LED_PINMUX, 0U);
IOMUXC_SetPinConfig( LED_PINMUX, 0x10B0U);
gpio_pin_config_t led_config = { kGPIO_DigitalOutput, 0, kGPIO_NoIntmode };
GPIO_PinInit(LED_PORT, LED_PIN, &led_config);
board_led_write(true);
// Button
IOMUXC_SetPinMux( BUTTON_PINMUX, 0U);
gpio_pin_config_t button_config = { kGPIO_DigitalInput, 0, kGPIO_IntRisingEdge, };
GPIO_PinInit(BUTTON_PORT, BUTTON_PIN, &button_config);
// UART
IOMUXC_SetPinMux( UART_TX_PINMUX, 0U);
IOMUXC_SetPinMux( UART_RX_PINMUX, 0U);
IOMUXC_SetPinConfig( UART_TX_PINMUX, 0x10B0u);
IOMUXC_SetPinConfig( UART_RX_PINMUX, 0x10B0u);
lpuart_config_t uart_config;
LPUART_GetDefaultConfig(&uart_config);
uart_config.baudRate_Bps = CFG_BOARD_UART_BAUDRATE;
uart_config.enableTx = true;
uart_config.enableRx = true;
LPUART_Init(UART_PORT, &uart_config, (CLOCK_GetPllFreq(kCLOCK_PllUsb1) / 6U) / (CLOCK_GetDiv(kCLOCK_UartDiv) + 1U));
//------------- USB0 -------------//
// Clock
CLOCK_EnableUsbhs0PhyPllClock(kCLOCK_Usbphy480M, 480000000U);
CLOCK_EnableUsbhs0Clock(kCLOCK_Usb480M, 480000000U);
USBPHY_Type* usb_phy = USBPHY1;
// Enable PHY support for Low speed device + LS via FS Hub
usb_phy->CTRL |= USBPHY_CTRL_SET_ENUTMILEVEL2_MASK | USBPHY_CTRL_SET_ENUTMILEVEL3_MASK;
// Enable all power for normal operation
usb_phy->PWD = 0;
// TX Timing
uint32_t phytx = usb_phy->TX;
phytx &= ~(USBPHY_TX_D_CAL_MASK | USBPHY_TX_TXCAL45DM_MASK | USBPHY_TX_TXCAL45DP_MASK);
phytx |= USBPHY_TX_D_CAL(0x0C) | USBPHY_TX_TXCAL45DP(0x06) | USBPHY_TX_TXCAL45DM(0x06);
usb_phy->TX = phytx;
// USB1
// CLOCK_EnableUsbhs1PhyPllClock(kCLOCK_Usbphy480M, 480000000U);
// CLOCK_EnableUsbhs1Clock(kCLOCK_Usb480M, 480000000U);
}
//--------------------------------------------------------------------+
// USB Interrupt Handler
//--------------------------------------------------------------------+
void USB_OTG1_IRQHandler(void)
{
#if CFG_TUSB_RHPORT0_MODE & OPT_MODE_HOST
tuh_isr(0);
#endif
#if CFG_TUSB_RHPORT0_MODE & OPT_MODE_DEVICE
tud_isr(0);
#endif
}
void USB_OTG2_IRQHandler(void)
{
#if CFG_TUSB_RHPORT1_MODE & OPT_MODE_HOST
tuh_isr(1);
#endif
#if CFG_TUSB_RHPORT1_MODE & OPT_MODE_DEVICE
tud_isr(1);
#endif
}
//--------------------------------------------------------------------+
// Board porting API
//--------------------------------------------------------------------+
void board_led_write(bool state)
{
GPIO_PinWrite(LED_PORT, LED_PIN, state ? LED_STATE_ON : (1-LED_STATE_ON));
}
uint32_t board_button_read(void)
{
// active low
return BUTTON_STATE_ACTIVE == GPIO_PinRead(BUTTON_PORT, BUTTON_PIN);
}
int board_uart_read(uint8_t* buf, int len)
{
LPUART_ReadBlocking(UART_PORT, buf, len);
return len;
}
int board_uart_write(void const * buf, int len)
{
LPUART_WriteBlocking(UART_PORT, (uint8_t*)buf, len);
return len;
}
#if CFG_TUSB_OS == OPT_OS_NONE
volatile uint32_t system_ticks = 0;
void SysTick_Handler(void)
{
system_ticks++;
}
uint32_t board_millis(void)
{
return system_ticks;
}
#endif

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hw/bsp/teensy_40/teensy40_flexspi_nor_config.c Normal file
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/*
* Copyright 2018 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include "teensy40_flexspi_nor_config.h"
/* Component ID definition, used by tools. */
#ifndef FSL_COMPONENT_ID
#define FSL_COMPONENT_ID "platform.drivers.xip_board"
#endif
/*******************************************************************************
* Code
******************************************************************************/
#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1)
#if defined(__CC_ARM) || defined(__ARMCC_VERSION) || defined(__GNUC__)
__attribute__((section(".boot_hdr.conf")))
#elif defined(__ICCARM__)
#pragma location = ".boot_hdr.conf"
#endif
const flexspi_nor_config_t qspiflash_config = {
.memConfig =
{
.tag = FLEXSPI_CFG_BLK_TAG,
.version = FLEXSPI_CFG_BLK_VERSION,
.readSampleClkSrc = kFlexSPIReadSampleClk_LoopbackFromDqsPad,
.csHoldTime = 3u,
.csSetupTime = 3u,
// Enable DDR mode, Wordaddassable, Safe configuration, Differential clock
.sflashPadType = kSerialFlash_4Pads,
.serialClkFreq = kFlexSpiSerialClk_100MHz,
.sflashA1Size = 2u * 1024u * 1024u,
.lookupTable =
{
// Read LUTs
FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB, RADDR_SDR, FLEXSPI_4PAD, 0x18),
FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 0x06, READ_SDR, FLEXSPI_4PAD, 0x04),
},
},
.pageSize = 256u,
.sectorSize = 4u * 1024u,
.blockSize = 256u * 1024u,
.isUniformBlockSize = false,
};
#endif /* XIP_BOOT_HEADER_ENABLE */

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hw/bsp/teensy_40/teensy40_flexspi_nor_config.h Normal file
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/*
* Copyright 2018 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef __TEENSY40_FLEXSPI_NOR_CONFIG__
#define __TEENSY40_FLEXSPI_NOR_CONFIG__
#include <stdint.h>
#include <stdbool.h>
#include "fsl_common.h"
/*! @name Driver version */
/*@{*/
/*! @brief XIP_BOARD driver version 2.0.0. */
#define FSL_XIP_BOARD_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
/*@}*/
/* FLEXSPI memory config block related defintions */
#define FLEXSPI_CFG_BLK_TAG (0x42464346UL) // ascii "FCFB" Big Endian
#define FLEXSPI_CFG_BLK_VERSION (0x56010400UL) // V1.4.0
#define FLEXSPI_CFG_BLK_SIZE (512)
/* FLEXSPI Feature related definitions */
#define FLEXSPI_FEATURE_HAS_PARALLEL_MODE 1
/* Lookup table related defintions */
#define CMD_INDEX_READ 0
#define CMD_INDEX_READSTATUS 1
#define CMD_INDEX_WRITEENABLE 2
#define CMD_INDEX_WRITE 4
#define CMD_LUT_SEQ_IDX_READ 0
#define CMD_LUT_SEQ_IDX_READSTATUS 1
#define CMD_LUT_SEQ_IDX_WRITEENABLE 3
#define CMD_LUT_SEQ_IDX_WRITE 9
#define CMD_SDR 0x01
#define CMD_DDR 0x21
#define RADDR_SDR 0x02
#define RADDR_DDR 0x22
#define CADDR_SDR 0x03
#define CADDR_DDR 0x23
#define MODE1_SDR 0x04
#define MODE1_DDR 0x24
#define MODE2_SDR 0x05
#define MODE2_DDR 0x25
#define MODE4_SDR 0x06
#define MODE4_DDR 0x26
#define MODE8_SDR 0x07
#define MODE8_DDR 0x27
#define WRITE_SDR 0x08
#define WRITE_DDR 0x28
#define READ_SDR 0x09
#define READ_DDR 0x29
#define LEARN_SDR 0x0A
#define LEARN_DDR 0x2A
#define DATSZ_SDR 0x0B
#define DATSZ_DDR 0x2B
#define DUMMY_SDR 0x0C
#define DUMMY_DDR 0x2C
#define DUMMY_RWDS_SDR 0x0D
#define DUMMY_RWDS_DDR 0x2D
#define JMP_ON_CS 0x1F
#define STOP 0
#define FLEXSPI_1PAD 0
#define FLEXSPI_2PAD 1
#define FLEXSPI_4PAD 2
#define FLEXSPI_8PAD 3
#define FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) \
(FLEXSPI_LUT_OPERAND0(op0) | FLEXSPI_LUT_NUM_PADS0(pad0) | FLEXSPI_LUT_OPCODE0(cmd0) | FLEXSPI_LUT_OPERAND1(op1) | \
FLEXSPI_LUT_NUM_PADS1(pad1) | FLEXSPI_LUT_OPCODE1(cmd1))
//!@brief Definitions for FlexSPI Serial Clock Frequency
typedef enum _FlexSpiSerialClockFreq
{
kFlexSpiSerialClk_30MHz = 1,
kFlexSpiSerialClk_50MHz = 2,
kFlexSpiSerialClk_60MHz = 3,
kFlexSpiSerialClk_75MHz = 4,
kFlexSpiSerialClk_80MHz = 5,
kFlexSpiSerialClk_100MHz = 6,
kFlexSpiSerialClk_120MHz = 7,
kFlexSpiSerialClk_133MHz = 8,
kFlexSpiSerialClk_166MHz = 9,
} flexspi_serial_clk_freq_t;
//!@brief FlexSPI clock configuration type
enum
{
kFlexSpiClk_SDR, //!< Clock configure for SDR mode
kFlexSpiClk_DDR, //!< Clock configurat for DDR mode
};
//!@brief FlexSPI Read Sample Clock Source definition
typedef enum _FlashReadSampleClkSource
{
kFlexSPIReadSampleClk_LoopbackInternally = 0,
kFlexSPIReadSampleClk_LoopbackFromDqsPad = 1,
kFlexSPIReadSampleClk_LoopbackFromSckPad = 2,
kFlexSPIReadSampleClk_ExternalInputFromDqsPad = 3,
} flexspi_read_sample_clk_t;
//!@brief Misc feature bit definitions
enum
{
kFlexSpiMiscOffset_DiffClkEnable = 0, //!< Bit for Differential clock enable
kFlexSpiMiscOffset_Ck2Enable = 1, //!< Bit for CK2 enable
kFlexSpiMiscOffset_ParallelEnable = 2, //!< Bit for Parallel mode enable
kFlexSpiMiscOffset_WordAddressableEnable = 3, //!< Bit for Word Addressable enable
kFlexSpiMiscOffset_SafeConfigFreqEnable = 4, //!< Bit for Safe Configuration Frequency enable
kFlexSpiMiscOffset_PadSettingOverrideEnable = 5, //!< Bit for Pad setting override enable
kFlexSpiMiscOffset_DdrModeEnable = 6, //!< Bit for DDR clock confiuration indication.
};
//!@brief Flash Type Definition
enum
{
kFlexSpiDeviceType_SerialNOR = 1, //!< Flash devices are Serial NOR
kFlexSpiDeviceType_SerialNAND = 2, //!< Flash devices are Serial NAND
kFlexSpiDeviceType_SerialRAM = 3, //!< Flash devices are Serial RAM/HyperFLASH
kFlexSpiDeviceType_MCP_NOR_NAND = 0x12, //!< Flash device is MCP device, A1 is Serial NOR, A2 is Serial NAND
kFlexSpiDeviceType_MCP_NOR_RAM = 0x13, //!< Flash deivce is MCP device, A1 is Serial NOR, A2 is Serial RAMs
};
//!@brief Flash Pad Definitions
enum
{
kSerialFlash_1Pad = 1,
kSerialFlash_2Pads = 2,
kSerialFlash_4Pads = 4,
kSerialFlash_8Pads = 8,
};
//!@brief FlexSPI LUT Sequence structure
typedef struct _lut_sequence
{
uint8_t seqNum; //!< Sequence Number, valid number: 1-16
uint8_t seqId; //!< Sequence Index, valid number: 0-15
uint16_t reserved;
} flexspi_lut_seq_t;
//!@brief Flash Configuration Command Type
enum
{
kDeviceConfigCmdType_Generic, //!< Generic command, for example: configure dummy cycles, drive strength, etc
kDeviceConfigCmdType_QuadEnable, //!< Quad Enable command
kDeviceConfigCmdType_Spi2Xpi, //!< Switch from SPI to DPI/QPI/OPI mode
kDeviceConfigCmdType_Xpi2Spi, //!< Switch from DPI/QPI/OPI to SPI mode
kDeviceConfigCmdType_Spi2NoCmd, //!< Switch to 0-4-4/0-8-8 mode
kDeviceConfigCmdType_Reset, //!< Reset device command
};
//!@brief FlexSPI Memory Configuration Block
typedef struct _FlexSPIConfig
{
uint32_t tag; //!< [0x000-0x003] Tag, fixed value 0x42464346UL
uint32_t version; //!< [0x004-0x007] Version,[31:24] -'V', [23:16] - Major, [15:8] - Minor, [7:0] - bugfix
uint32_t reserved0; //!< [0x008-0x00b] Reserved for future use
uint8_t readSampleClkSrc; //!< [0x00c-0x00c] Read Sample Clock Source, valid value: 0/1/3
uint8_t csHoldTime; //!< [0x00d-0x00d] CS hold time, default value: 3
uint8_t csSetupTime; //!< [0x00e-0x00e] CS setup time, default value: 3
uint8_t columnAddressWidth; //!< [0x00f-0x00f] Column Address with, for HyperBus protocol, it is fixed to 3, For
//! Serial NAND, need to refer to datasheet
uint8_t deviceModeCfgEnable; //!< [0x010-0x010] Device Mode Configure enable flag, 1 - Enable, 0 - Disable
uint8_t deviceModeType; //!< [0x011-0x011] Specify the configuration command type:Quad Enable, DPI/QPI/OPI switch,
//! Generic configuration, etc.
uint16_t waitTimeCfgCommands; //!< [0x012-0x013] Wait time for all configuration commands, unit: 100us, Used for
//! DPI/QPI/OPI switch or reset command
flexspi_lut_seq_t deviceModeSeq; //!< [0x014-0x017] Device mode sequence info, [7:0] - LUT sequence id, [15:8] - LUt
//! sequence number, [31:16] Reserved
uint32_t deviceModeArg; //!< [0x018-0x01b] Argument/Parameter for device configuration
uint8_t configCmdEnable; //!< [0x01c-0x01c] Configure command Enable Flag, 1 - Enable, 0 - Disable
uint8_t configModeType[3]; //!< [0x01d-0x01f] Configure Mode Type, similar as deviceModeTpe
flexspi_lut_seq_t
configCmdSeqs[3]; //!< [0x020-0x02b] Sequence info for Device Configuration command, similar as deviceModeSeq
uint32_t reserved1; //!< [0x02c-0x02f] Reserved for future use
uint32_t configCmdArgs[3]; //!< [0x030-0x03b] Arguments/Parameters for device Configuration commands
uint32_t reserved2; //!< [0x03c-0x03f] Reserved for future use
uint32_t controllerMiscOption; //!< [0x040-0x043] Controller Misc Options, see Misc feature bit definitions for more
//! details
uint8_t deviceType; //!< [0x044-0x044] Device Type: See Flash Type Definition for more details
uint8_t sflashPadType; //!< [0x045-0x045] Serial Flash Pad Type: 1 - Single, 2 - Dual, 4 - Quad, 8 - Octal
uint8_t serialClkFreq; //!< [0x046-0x046] Serial Flash Frequencey, device specific definitions, See System Boot
//! Chapter for more details
uint8_t lutCustomSeqEnable; //!< [0x047-0x047] LUT customization Enable, it is required if the program/erase cannot
//! be done using 1 LUT sequence, currently, only applicable to HyperFLASH
uint32_t reserved3[2]; //!< [0x048-0x04f] Reserved for future use
uint32_t sflashA1Size; //!< [0x050-0x053] Size of Flash connected to A1
uint32_t sflashA2Size; //!< [0x054-0x057] Size of Flash connected to A2
uint32_t sflashB1Size; //!< [0x058-0x05b] Size of Flash connected to B1
uint32_t sflashB2Size; //!< [0x05c-0x05f] Size of Flash connected to B2
uint32_t csPadSettingOverride; //!< [0x060-0x063] CS pad setting override value
uint32_t sclkPadSettingOverride; //!< [0x064-0x067] SCK pad setting override value
uint32_t dataPadSettingOverride; //!< [0x068-0x06b] data pad setting override value
uint32_t dqsPadSettingOverride; //!< [0x06c-0x06f] DQS pad setting override value
uint32_t timeoutInMs; //!< [0x070-0x073] Timeout threshold for read status command
uint32_t commandInterval; //!< [0x074-0x077] CS deselect interval between two commands
uint16_t dataValidTime[2]; //!< [0x078-0x07b] CLK edge to data valid time for PORT A and PORT B, in terms of 0.1ns
uint16_t busyOffset; //!< [0x07c-0x07d] Busy offset, valid value: 0-31
uint16_t busyBitPolarity; //!< [0x07e-0x07f] Busy flag polarity, 0 - busy flag is 1 when flash device is busy, 1 -
//! busy flag is 0 when flash device is busy
uint32_t lookupTable[64]; //!< [0x080-0x17f] Lookup table holds Flash command sequences
flexspi_lut_seq_t lutCustomSeq[12]; //!< [0x180-0x1af] Customizable LUT Sequences
uint32_t reserved4[4]; //!< [0x1b0-0x1bf] Reserved for future use
} flexspi_mem_config_t;
/* */
#define NOR_CMD_INDEX_READ CMD_INDEX_READ //!< 0
#define NOR_CMD_INDEX_READSTATUS CMD_INDEX_READSTATUS //!< 1
#define NOR_CMD_INDEX_WRITEENABLE CMD_INDEX_WRITEENABLE //!< 2
#define NOR_CMD_INDEX_ERASESECTOR 3 //!< 3
#define NOR_CMD_INDEX_PAGEPROGRAM CMD_INDEX_WRITE //!< 4
#define NOR_CMD_INDEX_CHIPERASE 5 //!< 5
#define NOR_CMD_INDEX_DUMMY 6 //!< 6
#define NOR_CMD_INDEX_ERASEBLOCK 7 //!< 7
#define NOR_CMD_LUT_SEQ_IDX_READ CMD_LUT_SEQ_IDX_READ //!< 0 READ LUT sequence id in lookupTable stored in config block
#define NOR_CMD_LUT_SEQ_IDX_READSTATUS \
CMD_LUT_SEQ_IDX_READSTATUS //!< 1 Read Status LUT sequence id in lookupTable stored in config block
#define NOR_CMD_LUT_SEQ_IDX_READSTATUS_XPI \
2 //!< 2 Read status DPI/QPI/OPI sequence id in lookupTable stored in config block
#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE \
CMD_LUT_SEQ_IDX_WRITEENABLE //!< 3 Write Enable sequence id in lookupTable stored in config block
#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE_XPI \
4 //!< 4 Write Enable DPI/QPI/OPI sequence id in lookupTable stored in config block
#define NOR_CMD_LUT_SEQ_IDX_ERASESECTOR 5 //!< 5 Erase Sector sequence id in lookupTable stored in config block
#define NOR_CMD_LUT_SEQ_IDX_ERASEBLOCK 8 //!< 8 Erase Block sequence id in lookupTable stored in config block
#define NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM \
CMD_LUT_SEQ_IDX_WRITE //!< 9 Program sequence id in lookupTable stored in config block
#define NOR_CMD_LUT_SEQ_IDX_CHIPERASE 11 //!< 11 Chip Erase sequence in lookupTable id stored in config block
#define NOR_CMD_LUT_SEQ_IDX_READ_SFDP 13 //!< 13 Read SFDP sequence in lookupTable id stored in config block
#define NOR_CMD_LUT_SEQ_IDX_RESTORE_NOCMD \
14 //!< 14 Restore 0-4-4/0-8-8 mode sequence id in lookupTable stored in config block
#define NOR_CMD_LUT_SEQ_IDX_EXIT_NOCMD \
15 //!< 15 Exit 0-4-4/0-8-8 mode sequence id in lookupTable stored in config blobk
/*
* Serial NOR configuration block
*/
typedef struct _flexspi_nor_config
{
flexspi_mem_config_t memConfig; //!< Common memory configuration info via FlexSPI
uint32_t pageSize; //!< Page size of Serial NOR
uint32_t sectorSize; //!< Sector size of Serial NOR
uint8_t ipcmdSerialClkFreq; //!< Clock frequency for IP command
uint8_t isUniformBlockSize; //!< Sector/Block size is the same
uint8_t reserved0[2]; //!< Reserved for future use
uint8_t serialNorType; //!< Serial NOR Flash type: 0/1/2/3
uint8_t needExitNoCmdMode; //!< Need to exit NoCmd mode before other IP command
uint8_t halfClkForNonReadCmd; //!< Half the Serial Clock for non-read command: true/false
uint8_t needRestoreNoCmdMode; //!< Need to Restore NoCmd mode after IP commmand execution
uint32_t blockSize; //!< Block size
uint32_t reserve2[11]; //!< Reserved for future use
} flexspi_nor_config_t;
#ifdef __cplusplus
extern "C" {
#endif
#ifdef __cplusplus
}
#endif
#endif /* __EVKMIMXRT1060_FLEXSPI_NOR_CONFIG__ */

1
hw/mcu/nuvoton Submodule

@ -0,0 +1 @@
Subproject commit dc96fff794d14818c93ea1d4d760d51a014d70c5

4
src/common/tusb_common.h
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@ -39,8 +39,8 @@
// Macros Helper // Macros Helper
//--------------------------------------------------------------------+ //--------------------------------------------------------------------+
#define TU_ARRAY_SIZE(_arr) ( sizeof(_arr) / sizeof(_arr[0]) ) #define TU_ARRAY_SIZE(_arr) ( sizeof(_arr) / sizeof(_arr[0]) )
#define TU_MIN(_x, _y) ( (_x) < (_y) ) ? (_x) : (_y) ) #define TU_MIN(_x, _y) ( ( (_x) < (_y) ) ? (_x) : (_y) )
#define TU_MAX(_x, _y) ( (_x) > (_y) ) ? (_x) : (_y) ) #define TU_MAX(_x, _y) ( ( (_x) > (_y) ) ? (_x) : (_y) )
#define TU_U16_HIGH(u16) ((uint8_t) (((u16) >> 8) & 0x00ff)) #define TU_U16_HIGH(u16) ((uint8_t) (((u16) >> 8) & 0x00ff))
#define TU_U16_LOW(u16) ((uint8_t) ((u16) & 0x00ff)) #define TU_U16_LOW(u16) ((uint8_t) ((u16) & 0x00ff))

23
src/device/usbd.c
View File

@ -519,9 +519,11 @@ static bool process_control_request(uint8_t rhport, tusb_control_request_t const
uint8_t const cfg_num = (uint8_t) p_request->wValue; uint8_t const cfg_num = (uint8_t) p_request->wValue;
dcd_set_config(rhport, cfg_num); dcd_set_config(rhport, cfg_num);
if ( !_usbd_dev.configured && cfg_num ) TU_ASSERT( process_set_config(rhport, cfg_num) );
_usbd_dev.configured = cfg_num ? 1 : 0; _usbd_dev.configured = cfg_num ? 1 : 0;
if ( cfg_num ) TU_ASSERT( process_set_config(rhport, cfg_num) );
tud_control_status(rhport, p_request); tud_control_status(rhport, p_request);
} }
break; break;
@ -618,7 +620,6 @@ static bool process_control_request(uint8_t rhport, tusb_control_request_t const
TU_ASSERT(ep_num < TU_ARRAY_SIZE(_usbd_dev.ep2drv) ); TU_ASSERT(ep_num < TU_ARRAY_SIZE(_usbd_dev.ep2drv) );
uint8_t const drvid = _usbd_dev.ep2drv[ep_num][ep_dir]; uint8_t const drvid = _usbd_dev.ep2drv[ep_num][ep_dir];
TU_ASSERT(drvid < USBD_CLASS_DRIVER_COUNT);
bool ret = false; bool ret = false;
@ -658,13 +659,17 @@ static bool process_control_request(uint8_t rhport, tusb_control_request_t const
} }
} }
// Some classes such as USBTMC needs to clear/re-init its buffer when receiving CLEAR_FEATURE request if (drvid < 0xFF) {
// We will forward all request targeted endpoint to class drivers after TU_ASSERT(drvid < USBD_CLASS_DRIVER_COUNT);
// - For class-type requests: driver is fully responsible to reply to host
// - For std-type requests : driver init/re-init internal variable/buffer only, and // Some classes such as USBTMC needs to clear/re-init its buffer when receiving CLEAR_FEATURE request
// must not call tud_control_status(), driver's return value will have no effect. // We will forward all request targeted endpoint to class drivers after
// EP state has already affected (stalled/cleared) // - For class-type requests: driver is fully responsible to reply to host
if ( invoke_class_control(rhport, drvid, p_request) ) ret = true; // - For std-type requests : driver init/re-init internal variable/buffer only, and
// must not call tud_control_status(), driver's return value will have no effect.
// EP state has already affected (stalled/cleared)
if ( invoke_class_control(rhport, drvid, p_request) ) ret = true;
}
if ( TUSB_REQ_TYPE_STANDARD == p_request->bmRequestType_bit.type ) if ( TUSB_REQ_TYPE_STANDARD == p_request->bmRequestType_bit.type )
{ {

434
src/portable/nuvoton/nuc121/dcd_nuc121.c Normal file
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@ -0,0 +1,434 @@
/*
* The MIT License (MIT)
*
* Copyright (c) 2019 Peter Lawrence
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*
* This file is part of the TinyUSB stack.
*/
/*
Theory of operation:
The NUC121/NUC125/NUC126 USBD peripheral has eight "EP"s, but each is simplex,
so two collectively (peripheral nomenclature of "EP0" and "EP1") are needed to
implement USB EP0. PERIPH_EP0 and PERIPH_EP1 are used by this driver for
EP0_IN and EP0_OUT respectively. This leaves up to six for user usage.
*/
#include "tusb_option.h"
#if TUSB_OPT_DEVICE_ENABLED && ( (CFG_TUSB_MCU == OPT_MCU_NUC121) || (CFG_TUSB_MCU == OPT_MCU_NUC126) )
#include "device/dcd.h"
#include "NuMicro.h"
/* allocation of USBD RAM for Setup, EP0_IN, and and EP_OUT */
#define PERIPH_SETUP_BUF_BASE 0
#define PERIPH_SETUP_BUF_LEN 8
#define PERIPH_EP0_BUF_BASE (PERIPH_SETUP_BUF_BASE + PERIPH_SETUP_BUF_LEN)
#define PERIPH_EP0_BUF_LEN CFG_TUD_ENDPOINT0_SIZE
#define PERIPH_EP1_BUF_BASE (PERIPH_EP0_BUF_BASE + PERIPH_EP0_BUF_LEN)
#define PERIPH_EP1_BUF_LEN CFG_TUD_ENDPOINT0_SIZE
#define PERIPH_EP2_BUF_BASE (PERIPH_EP1_BUF_BASE + PERIPH_EP1_BUF_LEN)
/* rather important info unfortunately not provided by device include files: how much there is */
#define USBD_BUF_SIZE ((CFG_TUSB_MCU == OPT_MCU_NUC121) ? 768 : 512)
enum ep_enum
{
PERIPH_EP0 = 0,
PERIPH_EP1 = 1,
PERIPH_EP2 = 2,
PERIPH_EP3 = 3,
PERIPH_EP4 = 4,
PERIPH_EP5 = 5,
PERIPH_EP6 = 6,
PERIPH_EP7 = 7,
PERIPH_MAX_EP,
};
/* set by dcd_set_address() */
static volatile uint8_t assigned_address;
/* reset by dcd_init(), this is used by dcd_edpt_open() to assign USBD peripheral buffer addresses */
static uint32_t bufseg_addr;
/* used by dcd_edpt_xfer() and the ISR to reset the data sync (DATA0/DATA1) in an EP0_IN transfer */
static bool active_ep0_xfer;
/* RAM table needed to track ongoing transfers performed by dcd_edpt_xfer(), dcd_in_xfer(), and the ISR */
static struct xfer_ctl_t
{
uint8_t *data_ptr; /* collectively, data_ptr and remaining_bytes track progress of endpoint transfers */
uint16_t remaining_bytes;
uint16_t max_packet_size; /* needed since device driver only finds out this at runtime */
uint16_t total_bytes; /* quantity needed to pass as argument to dcd_event_xfer_complete() (for IN endpoints) */
} xfer_table[PERIPH_MAX_EP];
/*
local helper functions
*/
static void usb_attach(void)
{
USBD->SE0 &= ~USBD_SE0_SE0_Msk;
}
static void usb_detach(void)
{
USBD->SE0 |= USBD_SE0_SE0_Msk;
}
static void usb_control_send_zlp(void)
{
USBD->EP[PERIPH_EP0].CFG |= USBD_CFG_DSQSYNC_Msk;
USBD->EP[PERIPH_EP0].MXPLD = 0;
}
/* reconstruct ep_addr from particular USB Configuration Register */
static uint8_t decode_ep_addr(USBD_EP_T *ep)
{
uint8_t ep_addr = ep->CFG & USBD_CFG_EPNUM_Msk;
if ( USBD_CFG_EPMODE_IN == (ep->CFG & USBD_CFG_STATE_Msk) )
ep_addr |= TUSB_DIR_IN_MASK;
return ep_addr;
}
/* map 8-bit ep_addr into peripheral endpoint index (PERIPH_EP0...) */
static USBD_EP_T *ep_entry(uint8_t ep_addr, bool add)
{
USBD_EP_T *ep;
enum ep_enum ep_index;
for (ep_index = PERIPH_EP0, ep = USBD->EP; ep_index < PERIPH_MAX_EP; ep_index++, ep++)
{
if (add)
{
/* take first peripheral endpoint that is unused */
if (0 == (ep->CFG & USBD_CFG_STATE_Msk)) return ep;
}
else
{
/* find a peripheral endpoint that matches ep_addr */
uint8_t candidate_ep_addr = decode_ep_addr(ep);
if (candidate_ep_addr == ep_addr) return ep;
}
}
return NULL;
}
/* perform an IN endpoint transfer; this is called by dcd_edpt_xfer() and the ISR */
static void dcd_in_xfer(struct xfer_ctl_t *xfer, USBD_EP_T *ep)
{
uint16_t bytes_now = tu_min16(xfer->remaining_bytes, xfer->max_packet_size);
memcpy((uint8_t *)(USBD_BUF_BASE + ep->BUFSEG), xfer->data_ptr, bytes_now);
ep->MXPLD = bytes_now;
}
/* centralized location for USBD interrupt enable bit mask */
static const uint32_t enabled_irqs = USBD_INTSTS_VBDETIF_Msk | USBD_INTSTS_BUSIF_Msk | USBD_INTSTS_SETUP_Msk | USBD_INTSTS_USBIF_Msk | USBD_INTSTS_SOFIF_Msk;
/*
NUC121/NUC125/NUC126 TinyUSB API driver implementation
*/
void dcd_init(uint8_t rhport)
{
(void) rhport;
#ifdef SUPPORT_LPM
USBD->ATTR = 0x7D0 | USBD_LPMACK;
#else
USBD->ATTR = 0x7D0;
#endif
usb_detach();
USBD->STBUFSEG = PERIPH_SETUP_BUF_BASE;
for (enum ep_enum ep_index = PERIPH_EP0; ep_index < PERIPH_MAX_EP; ep_index++)
{
USBD->EP[ep_index].CFGP &= ~USBD_CFG_STATE_Msk;
}
/* allocate the default EP0 endpoints */
USBD->EP[PERIPH_EP0].CFG = USBD_CFG_CSTALL_Msk | USBD_CFG_EPMODE_IN;
USBD->EP[PERIPH_EP0].BUFSEG = PERIPH_EP0_BUF_BASE;
xfer_table[PERIPH_EP0].max_packet_size = PERIPH_EP0_BUF_LEN;
USBD->EP[PERIPH_EP1].CFG = USBD_CFG_CSTALL_Msk | USBD_CFG_EPMODE_OUT;
USBD->EP[PERIPH_EP1].BUFSEG = PERIPH_EP1_BUF_BASE;
xfer_table[PERIPH_EP1].max_packet_size = PERIPH_EP1_BUF_LEN;
/* USB RAM beyond what we've allocated above is available to the user */
bufseg_addr = PERIPH_EP2_BUF_BASE;
usb_attach();
USBD->INTSTS = enabled_irqs;
USBD->INTEN = enabled_irqs;
}
void dcd_int_enable(uint8_t rhport)
{
(void) rhport;
NVIC_EnableIRQ(USBD_IRQn);
}
void dcd_int_disable(uint8_t rhport)
{
(void) rhport;
NVIC_DisableIRQ(USBD_IRQn);
}
void dcd_set_address(uint8_t rhport, uint8_t dev_addr)
{
(void) rhport;
usb_control_send_zlp(); /* SET_ADDRESS is the one exception where TinyUSB doesn't use dcd_edpt_xfer() to generate a ZLP */
assigned_address = dev_addr;
}
void dcd_set_config(uint8_t rhport, uint8_t config_num)
{
(void) rhport;
(void) config_num;
}
void dcd_remote_wakeup(uint8_t rhport)
{
(void) rhport;
USBD->ATTR = USBD_ATTR_RWAKEUP_Msk;
}
bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc)
{
(void) rhport;
USBD_EP_T *ep = ep_entry(p_endpoint_desc->bEndpointAddress, true);
TU_ASSERT(ep);
/* mine the data for the information we need */
int const dir = tu_edpt_dir(p_endpoint_desc->bEndpointAddress);
int const size = p_endpoint_desc->wMaxPacketSize.size;
tusb_xfer_type_t const type = p_endpoint_desc->bmAttributes.xfer;
struct xfer_ctl_t *xfer = &xfer_table[ep - USBD->EP];
/* allocate buffer from USB RAM */
ep->BUFSEG = bufseg_addr;
bufseg_addr += size;
TU_ASSERT(bufseg_addr <= USBD_BUF_SIZE);
/* construct USB Configuration Register value and then write it */
uint32_t cfg = tu_edpt_number(p_endpoint_desc->bEndpointAddress);
cfg |= (TUSB_DIR_IN == dir) ? USBD_CFG_EPMODE_IN : USBD_CFG_EPMODE_OUT;
if (TUSB_XFER_ISOCHRONOUS == type)
cfg |= USBD_CFG_TYPE_ISO;
ep->CFG = cfg;
/* make a note of the endpoint size */
xfer->max_packet_size = size;
return true;
}
bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t *buffer, uint16_t total_bytes)
{
(void) rhport;
/* mine the data for the information we need */
tusb_dir_t dir = tu_edpt_dir(ep_addr);
USBD_EP_T *ep = ep_entry(ep_addr, false);
struct xfer_ctl_t *xfer = &xfer_table[ep - USBD->EP];
/* store away the information we'll needing now and later */
xfer->data_ptr = buffer;
xfer->remaining_bytes = total_bytes;
xfer->total_bytes = total_bytes;
/* for the first of one or more EP0_IN packets in a message, the first must be DATA1 */
if ( (0x80 == ep_addr) && !active_ep0_xfer ) ep->CFG |= USBD_CFG_DSQSYNC_Msk;
if (TUSB_DIR_IN == dir)
dcd_in_xfer(xfer, ep);
else
ep->MXPLD = xfer->max_packet_size;
return true;
}
void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr)
{
(void) rhport;
USBD_EP_T *ep = ep_entry(ep_addr, false);
ep->CFGP |= USBD_CFGP_SSTALL_Msk;
}
void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr)
{
(void) rhport;
USBD_EP_T *ep = ep_entry(ep_addr, false);
ep->CFG |= USBD_CFG_CSTALL_Msk;
}
void USBD_IRQHandler(void)
{
uint32_t status = USBD->INTSTS;
#ifdef SUPPORT_LPM
uint32_t state = USBD->ATTR & 0x300f;
#else
uint32_t state = USBD->ATTR & 0xf;
#endif
if(status & USBD_INTSTS_VBDETIF_Msk)
{
if(USBD->VBUSDET & USBD_VBUSDET_VBUSDET_Msk)
{
/* USB connect */
USBD->ATTR |= USBD_ATTR_USBEN_Msk | USBD_ATTR_PHYEN_Msk;
}
else
{
/* USB disconnect */
USBD->ATTR &= ~USBD_ATTR_USBEN_Msk;
}
}
if(status & USBD_INTSTS_BUSIF_Msk)
{
if(state & USBD_ATTR_USBRST_Msk)
{
/* USB bus reset */
USBD->ATTR |= USBD_ATTR_USBEN_Msk | USBD_ATTR_PHYEN_Msk;
/* Reset all endpoints to DATA0 */
for(enum ep_enum ep_index = PERIPH_EP0; ep_index < PERIPH_MAX_EP; ep_index++)
USBD->EP[ep_index].CFG &= ~USBD_CFG_DSQSYNC_Msk;
/* Reset USB device address */
USBD->FADDR = 0;
/* reset EP0_IN flag */
active_ep0_xfer = false;
dcd_event_bus_signal(0, DCD_EVENT_BUS_RESET, true);
}
if(state & USBD_ATTR_SUSPEND_Msk)
{
/* Enable USB but disable PHY */
USBD->ATTR &= ~USBD_ATTR_PHYEN_Msk;
dcd_event_bus_signal(0, DCD_EVENT_SUSPEND, true);
}
if(state & USBD_ATTR_RESUME_Msk)
{
/* Enable USB and enable PHY */
USBD->ATTR |= USBD_ATTR_USBEN_Msk | USBD_ATTR_PHYEN_Msk;
dcd_event_bus_signal(0, DCD_EVENT_RESUME, true);
}
}
if(status & USBD_INTSTS_SETUP_Msk)
{
/* clear the data ready flag of control endpoints */
USBD->EP[PERIPH_EP0].CFGP |= USBD_CFGP_CLRRDY_Msk;
USBD->EP[PERIPH_EP1].CFGP |= USBD_CFGP_CLRRDY_Msk;
/* get SETUP packet from USB buffer */
dcd_event_setup_received(0, (uint8_t *)USBD_BUF_BASE, true);
}
if(status & USBD_INTSTS_USBIF_Msk)
{
if (status & USBD_INTSTS_EPEVT0_Msk) /* PERIPH_EP0 (EP0_IN) event: this is treated separately from the rest */
{
/* given ACK from host has happened, we can now set the address (if not already done) */
if((USBD->FADDR != assigned_address) && (USBD->FADDR == 0)) USBD->FADDR = assigned_address;
uint16_t const available_bytes = USBD->EP[PERIPH_EP0].MXPLD;
active_ep0_xfer = (available_bytes == xfer_table[PERIPH_EP0].max_packet_size);
dcd_event_xfer_complete(0, 0x80, available_bytes, XFER_RESULT_SUCCESS, true);
}
/* service PERIPH_EP1 through PERIPH_EP7 */
enum ep_enum ep_index;
uint32_t mask;
struct xfer_ctl_t *xfer;
USBD_EP_T *ep;
for (ep_index = PERIPH_EP1, mask = USBD_INTSTS_EPEVT1_Msk, xfer = &xfer_table[PERIPH_EP1], ep = &USBD->EP[PERIPH_EP1]; ep_index <= PERIPH_EP7; ep_index++, mask <<= 1, xfer++, ep++)
{
if(status & mask)
{
USBD->INTSTS = mask;
uint16_t const available_bytes = ep->MXPLD;
uint8_t const ep_addr = decode_ep_addr(ep);
bool const out_ep = !(ep_addr & TUSB_DIR_IN_MASK);
if (out_ep)
{
/* copy the data from the PC to the previously provided buffer */
memcpy(xfer->data_ptr, (uint8_t *)(USBD_BUF_BASE + ep->BUFSEG), available_bytes);
xfer->remaining_bytes -= available_bytes;
xfer->data_ptr += available_bytes;
/* when the transfer is finished, alert TinyUSB */
if ( (0 == xfer->remaining_bytes) || (available_bytes < xfer->max_packet_size) )
dcd_event_xfer_complete(0, ep_addr, available_bytes, XFER_RESULT_SUCCESS, true);
}
else
{
/* update the bookkeeping to reflect the data that has now been sent to the PC */
xfer->remaining_bytes -= available_bytes;
xfer->data_ptr += available_bytes;
/* if more data to send, send it; otherwise, alert TinyUSB that we've finished */
if (xfer->remaining_bytes)
dcd_in_xfer(xfer, ep);
else
dcd_event_xfer_complete(0, ep_addr, xfer->total_bytes, XFER_RESULT_SUCCESS, true);
}
}
}
}
if(status & USBD_INTSTS_SOFIF_Msk)
{
/* Start-Of-Frame event */
dcd_event_bus_signal(0, DCD_EVENT_SOF, true);
}
/* acknowledge all interrupts */
USBD->INTSTS = status & enabled_irqs;
}
void dcd_isr(uint8_t rhport)
{
(void) rhport;
USBD_IRQHandler();
}
#endif

3
src/tusb_option.h
View File

@ -77,6 +77,9 @@
#define OPT_MCU_MIMXRT10XX 700 ///< NXP iMX RT10xx #define OPT_MCU_MIMXRT10XX 700 ///< NXP iMX RT10xx
#define OPT_MCU_NUC121 800
#define OPT_MCU_NUC126 801
/** @} */ /** @} */
/** \defgroup group_supported_os Supported RTOS /** \defgroup group_supported_os Supported RTOS