usb on u5a5 hs work well with correct VBVALEXTOEN/VBVALOVAL set
This commit is contained in:
hathach
parent
9f0223dccd
commit
db3ff4b352
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@ -217,7 +217,7 @@ function(family_configure_common TARGET RTOS)
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if (NOT TARGET segger_rtt)
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add_library(segger_rtt STATIC ${TOP}/lib/SEGGER_RTT/RTT/SEGGER_RTT.c)
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target_include_directories(segger_rtt PUBLIC ${TOP}/lib/SEGGER_RTT/RTT)
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target_compile_definitions(segger_rtt PUBLIC SEGGER_RTT_MODE_DEFAULT=SEGGER_RTT_MODE_BLOCK_IF_FIFO_FULL)
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#target_compile_definitions(segger_rtt PUBLIC SEGGER_RTT_MODE_DEFAULT=SEGGER_RTT_MODE_BLOCK_IF_FIFO_FULL)
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endif()
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target_link_libraries(${TARGET} PUBLIC segger_rtt)
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endif ()
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@ -6,5 +6,6 @@ set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/STM32U5A5ZJTXQ_FLASH.ld)
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function(update_board TARGET)
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target_compile_definitions(${TARGET} PUBLIC
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STM32U5A5xx
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HSE_VALUE=16000000UL
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)
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endfunction()
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@ -38,8 +38,8 @@ extern "C"
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#define LED_STATE_ON 1
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// BUTTON
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#define BUTTON_PORT GPIOA
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#define BUTTON_PIN GPIO_PIN_0
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#define BUTTON_PORT GPIOC
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#define BUTTON_PIN GPIO_PIN_13
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#define BUTTON_STATE_ACTIVE 1
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// UART Enable for STLink VCOM
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@ -101,6 +101,8 @@ static void SystemClock_Config(void) {
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HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4);
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// USB Clock
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__HAL_RCC_SYSCFG_CLK_ENABLE();
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RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
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PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USBPHY;
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PeriphClkInit.UsbPhyClockSelection = RCC_USBPHYCLKSOURCE_HSE;
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@ -1,5 +1,6 @@
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CFLAGS += \
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-DSTM32U5A5xx \
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-DHSE_VALUE=16000000UL \
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# All source paths should be relative to the top level.
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LD_FILE = ${BOARD_PATH}/STM32U5A5ZJTXQ_FLASH.ld
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@ -124,7 +124,7 @@ void board_init(void) {
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HAL_UART_Init(&UartHandle);
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/* Configure USB FS GPIOs */
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/* Configure USB GPIOs */
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/* Configure DM DP Pins */
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GPIO_InitStruct.Pin = (GPIO_PIN_11 | GPIO_PIN_12);
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GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
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@ -153,6 +153,12 @@ void board_init(void) {
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GPIO_InitStruct.Pull = GPIO_NOPULL;
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HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
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/* Enable USB power on Pwrctrl CR2 register */
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HAL_PWREx_EnableVddUSB();
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/* USB clock enable */
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__HAL_RCC_USB_OTG_FS_CLK_ENABLE();
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// Enable VBUS sense (B device) via pin PA9
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USB_OTG_FS->GCCFG |= USB_OTG_GCCFG_VBDEN;
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#else
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@ -164,11 +170,6 @@ void board_init(void) {
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USB_OTG_FS->GOTGCTL |= USB_OTG_GOTGCTL_BVALOVAL;
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#endif // vbus sense
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/* Enable USB power on Pwrctrl CR2 register */
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HAL_PWREx_EnableVddUSB();
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/* USB clock enable */
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__HAL_RCC_USB_OTG_FS_CLK_ENABLE();
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#else
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// STM59x/Ax/Fx/Gx only have 1 USB HS port
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@ -177,15 +178,7 @@ void board_init(void) {
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NVIC_SetPriority(OTG_HS_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
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#endif
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// Disable VBUS sense (B device)
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USB_OTG_HS->GCCFG &= ~USB_OTG_GCCFG_VBDEN;
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// B-peripheral session valid override enable
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USB_OTG_HS->GOTGCTL |= USB_OTG_GOTGCTL_BVALOEN;
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USB_OTG_HS->GOTGCTL |= USB_OTG_GOTGCTL_BVALOVAL;
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/* USB clock enable */
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__HAL_RCC_SYSCFG_CLK_ENABLE();
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__HAL_RCC_USB_OTG_HS_CLK_ENABLE();
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__HAL_RCC_USBPHYC_CLK_ENABLE();
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@ -195,6 +188,13 @@ void board_init(void) {
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/*Configuring the SYSCFG registers OTG_HS PHY*/
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HAL_SYSCFG_EnableOTGPHY(SYSCFG_OTG_HS_PHY_ENABLE);
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// Disable VBUS sense (B device)
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USB_OTG_HS->GCCFG &= ~USB_OTG_GCCFG_VBDEN;
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// B-peripheral session valid override enable
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USB_OTG_HS->GCCFG |= USB_OTG_GCCFG_VBVALEXTOEN;
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USB_OTG_HS->GCCFG |= USB_OTG_GCCFG_VBVALOVAL;
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#endif // USB_OTG_FS
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@ -1074,7 +1074,6 @@ void dcd_int_handler(uint8_t rhport) {
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if (int_status & GINTSTS_ENUMDNE) {
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// ENUMDNE is the end of reset where speed of the link is detected
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dwc2->gintsts = GINTSTS_ENUMDNE;
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tusb_speed_t speed;
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@ -1094,6 +1093,8 @@ void dcd_int_handler(uint8_t rhport) {
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break;
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}
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// TODO must update GUSBCFG_TRDT according to link speed
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dcd_event_bus_reset(rhport, speed, true);
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}
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@ -24,8 +24,8 @@
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* This file is part of the TinyUSB stack.
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*/
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#ifndef _DWC2_STM32_H_
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#define _DWC2_STM32_H_
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#ifndef DWC2_STM32_H_
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#define DWC2_STM32_H_
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#ifdef __cplusplus
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extern "C" {
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@ -124,35 +124,36 @@ static const dwc2_controller_t _dwc2_controller[] = {
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// SystemCoreClock is already included by family header
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// extern uint32_t SystemCoreClock;
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TU_ATTR_ALWAYS_INLINE
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static inline void dwc2_dcd_int_enable(uint8_t rhport) {
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TU_ATTR_ALWAYS_INLINE static inline void dwc2_dcd_int_enable(uint8_t rhport) {
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NVIC_EnableIRQ((IRQn_Type) _dwc2_controller[rhport].irqnum);
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}
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TU_ATTR_ALWAYS_INLINE
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static inline void dwc2_dcd_int_disable(uint8_t rhport) {
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TU_ATTR_ALWAYS_INLINE static inline void dwc2_dcd_int_disable(uint8_t rhport) {
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NVIC_DisableIRQ((IRQn_Type) _dwc2_controller[rhport].irqnum);
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}
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TU_ATTR_ALWAYS_INLINE
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static inline void dwc2_remote_wakeup_delay(void) {
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TU_ATTR_ALWAYS_INLINE static inline void dwc2_remote_wakeup_delay(void) {
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// try to delay for 1 ms
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uint32_t count = SystemCoreClock / 1000;
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while (count--) __NOP();
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}
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// MCU specific PHY init, called BEFORE core reset
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// - dwc2 3.30a (H5) use USB_HS_PHYC
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// - dwc2 4.11a (U5) use femtoPHY
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static inline void dwc2_phy_init(dwc2_regs_t* dwc2, uint8_t hs_phy_type) {
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if (hs_phy_type == HS_PHY_TYPE_NONE) {
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// Enable on-chip FS PHY
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dwc2->stm32_gccfg |= STM32_GCCFG_PWRDWN;
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} else {
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#if CFG_TUSB_MCU != OPT_MCU_STM32U5
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// Disable FS PHY, TODO on U5A5 (dwc2 4.11a) 16th bit is 'Host CDP behavior enable'
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dwc2->stm32_gccfg &= ~STM32_GCCFG_PWRDWN;
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#endif
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// Enable on-chip HS PHY
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if (hs_phy_type == HS_PHY_TYPE_UTMI || hs_phy_type == HS_PHY_TYPE_UTMI_ULPI) {
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#ifdef USB_HS_PHYC
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#ifdef USB_HS_PHYC
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// Enable UTMI HS PHY
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dwc2->stm32_gccfg |= STM32_GCCFG_PHYHSEN;
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@ -184,7 +185,9 @@ static inline void dwc2_phy_init(dwc2_regs_t* dwc2, uint8_t hs_phy_type) {
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// Enable PLL internal PHY
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USB_HS_PHYC->USB_HS_PHYC_PLL |= USB_HS_PHYC_PLL_PLLEN;
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#endif
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#else
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#endif
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}
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}
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}
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@ -232,4 +235,4 @@ static inline void dwc2_phy_update(dwc2_regs_t* dwc2, uint8_t hs_phy_type) {
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}
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#endif
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#endif /* _DWC2_STM32_H_ */
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#endif
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