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hardcoded configPRIO_BITS for IAR build to pass CI

This commit is contained in:
hathach 2023-01-30 16:42:56 +07:00
parent df2ebe5d1a
commit cc18784479
3 changed files with 35 additions and 17 deletions
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23
examples/device/cdc_msc_freertos/src/FreeRTOSConfig/FreeRTOSConfig.h
View File

@ -42,8 +42,8 @@
* See http://www.freertos.org/a00110.html.
*----------------------------------------------------------*/
// skip if is compiled with assembler
#if !defined(__ASSEMBLER__) && !defined(__IASMARM__)
// skip if included from IAR assembler
#ifndef __IASMARM__
// Include MCU header
#include "bsp/board_mcu.h"
@ -149,10 +149,10 @@
#ifdef __RX__
/* Renesas RX series */
#define vSoftwareInterruptISR INT_Excep_ICU_SWINT
#define vTickISR INT_Excep_CMT0_CMI0
#define configPERIPHERAL_CLOCK_HZ (configCPU_CLOCK_HZ/2)
#define configKERNEL_INTERRUPT_PRIORITY 1
#define vSoftwareInterruptISR INT_Excep_ICU_SWINT
#define vTickISR INT_Excep_CMT0_CMI0
#define configPERIPHERAL_CLOCK_HZ (configCPU_CLOCK_HZ/2)
#define configKERNEL_INTERRUPT_PRIORITY 1
#define configMAX_SYSCALL_INTERRUPT_PRIORITY 4
#else
@ -168,10 +168,19 @@
#if defined(__NVIC_PRIO_BITS)
// For Cortex-M specific: __NVIC_PRIO_BITS is defined in core_cmx.h
#define configPRIO_BITS __NVIC_PRIO_BITS
#elif defined(__ECLIC_INTCTLBITS)
// RISC-V Bumblebee core from nuclei
#define configPRIO_BITS __ECLIC_INTCTLBITS
#elif !defined(__ASSEMBLER__) && !defined(__IASMARM__)
#elif defined(__IASMARM__)
// FIXME: IAR Assembler cannot include mcu header directly to get __NVIC_PRIO_BITS.
// Therefore we will hard coded it to minimum value of 2 to get pass ci build.
// IAR user must update this to correct value of the target MCU
#message "configPRIO_BITS is hard coded to 2 to pass IAR build only. User should update it per MCU"
#define configPRIO_BITS 2
#else
#error "FreeRTOS configPRIO_BITS to be defined"
#endif

23
examples/device/hid_composite_freertos/src/FreeRTOSConfig/FreeRTOSConfig.h
View File

@ -42,8 +42,8 @@
* See http://www.freertos.org/a00110.html.
*----------------------------------------------------------*/
// skip if is compiled with assembler
#if !defined(__ASSEMBLER__) && !defined(__IASMARM__)
// skip if included from IAR assembler
#ifndef __IASMARM__
// Include MCU header
#include "bsp/board_mcu.h"
@ -149,10 +149,10 @@
#ifdef __RX__
/* Renesas RX series */
#define vSoftwareInterruptISR INT_Excep_ICU_SWINT
#define vTickISR INT_Excep_CMT0_CMI0
#define configPERIPHERAL_CLOCK_HZ (configCPU_CLOCK_HZ/2)
#define configKERNEL_INTERRUPT_PRIORITY 1
#define vSoftwareInterruptISR INT_Excep_ICU_SWINT
#define vTickISR INT_Excep_CMT0_CMI0
#define configPERIPHERAL_CLOCK_HZ (configCPU_CLOCK_HZ/2)
#define configKERNEL_INTERRUPT_PRIORITY 1
#define configMAX_SYSCALL_INTERRUPT_PRIORITY 4
#else
@ -168,10 +168,19 @@
#if defined(__NVIC_PRIO_BITS)
// For Cortex-M specific: __NVIC_PRIO_BITS is defined in core_cmx.h
#define configPRIO_BITS __NVIC_PRIO_BITS
#elif defined(__ECLIC_INTCTLBITS)
// RISC-V Bumblebee core from nuclei
#define configPRIO_BITS __ECLIC_INTCTLBITS
#elif !defined(__ASSEMBLER__) && !defined(__IASMARM__)
#elif defined(__IASMARM__)
// FIXME: IAR Assembler cannot include mcu header directly to get __NVIC_PRIO_BITS.
// Therefore we will hard coded it to minimum value of 2 to get pass ci build.
// IAR user must update this to correct value of the target MCU
#message "configPRIO_BITS is hard coded to 2 to pass IAR build only. User should update it per MCU"
#define configPRIO_BITS 2
#else
#error "FreeRTOS configPRIO_BITS to be defined"
#endif

6
src/tusb_option.h
View File

@ -27,9 +27,6 @@
#ifndef _TUSB_OPTION_H_
#define _TUSB_OPTION_H_
// To avoid GCC compiler warnings when -pedantic option is used (strict ISO C)
typedef int make_iso_compilers_happy;
#include "common/tusb_compiler.h"
#define TUSB_VERSION_MAJOR 0
@ -435,6 +432,9 @@ typedef int make_iso_compilers_happy;
#error Control Endpoint Max Packet Size cannot be larger than 64
#endif
// To avoid GCC compiler warnings when -pedantic option is used (strict ISO C)
typedef int make_iso_compilers_happy;
#endif /* _TUSB_OPTION_H_ */
/** @} */