add ra6m1 board
This commit is contained in:
hathach
parent
50381f7b4c
commit
c5d958d104
|
|
@ -31,7 +31,11 @@
|
|||
#define BSP_CLOCK_CFG_SUBCLOCK_POPULATED (1)
|
||||
#define BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS 1000
|
||||
|
||||
#define BSP_FEATURE_BSP_HAS_SCISPI_CLOCK 0
|
||||
|
||||
#define BSP_FEATURE_TFU_SUPPORTED 0
|
||||
#define BSP_TZ_SECURE_BUILD (0)
|
||||
#define BSP_TZ_NONSECURE_BUILD (0)
|
||||
|
||||
// for SystemInit()
|
||||
void bsp_init(void * p_args);
|
||||
|
|
|
|||
|
|
@ -25,11 +25,6 @@
|
|||
#define BSP_CORTEX_VECTOR_TABLE_ENTRIES (16U)
|
||||
#define BSP_VECTOR_TABLE_MAX_ENTRIES (48U)
|
||||
|
||||
#define BSP_TZ_SECURE_BUILD (0)
|
||||
#define BSP_TZ_NONSECURE_BUILD (0)
|
||||
|
||||
#define BSP_FEATURE_BSP_HAS_SCISPI_CLOCK 0
|
||||
|
||||
#define OFS_SEQ1 0xA001A001 | (1 << 1) | (3 << 2)
|
||||
#define OFS_SEQ2 (15 << 4) | (3 << 8) | (3 << 10)
|
||||
#define OFS_SEQ3 (1 << 12) | (1 << 14) | (1 << 17)
|
||||
|
|
|
|||
|
|
@ -0,0 +1,53 @@
|
|||
/*
|
||||
* The MIT License (MIT)
|
||||
*
|
||||
* Copyright (c) 2023 Ha Thach (tinyusb.org)
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
* of this software and associated documentation files (the "Software"), to deal
|
||||
* in the Software without restriction, including without limitation the rights
|
||||
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
* copies of the Software, and to permit persons to whom the Software is
|
||||
* furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
||||
* THE SOFTWARE.
|
||||
*
|
||||
* This file is part of the TinyUSB stack.
|
||||
*/
|
||||
|
||||
#ifndef _BOARD_H_
|
||||
#define _BOARD_H_
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define LED1 BSP_IO_PORT_01_PIN_12
|
||||
#define LED_STATE_ON 1
|
||||
|
||||
#define SW1 BSP_IO_PORT_04_PIN_15
|
||||
#define BUTTON_STATE_ACTIVE 0
|
||||
|
||||
const ioport_pin_cfg_t board_pin_cfg[] = {
|
||||
{.pin = LED1, .pin_cfg = IOPORT_CFG_PORT_DIRECTION_OUTPUT},
|
||||
{.pin = SW1, .pin_cfg = IOPORT_CFG_PORT_DIRECTION_INPUT},
|
||||
// USB D+, D-, VBus
|
||||
{.pin = BSP_IO_PORT_04_PIN_07, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_USB_FS},
|
||||
{.pin = BSP_IO_PORT_09_PIN_14, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_USB_FS},
|
||||
{.pin = BSP_IO_PORT_09_PIN_15, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_USB_FS},
|
||||
};
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,77 @@
|
|||
/* generated configuration header file - do not edit */
|
||||
#ifndef BSP_CFG_H_
|
||||
#define BSP_CFG_H_
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include "bsp_clock_cfg.h"
|
||||
#include "bsp_mcu_family_cfg.h"
|
||||
|
||||
#define RA_NOT_DEFINED 0
|
||||
#ifndef BSP_CFG_RTOS
|
||||
#if (RA_NOT_DEFINED) != (2)
|
||||
#define BSP_CFG_RTOS (2)
|
||||
#elif (RA_NOT_DEFINED) != (RA_NOT_DEFINED)
|
||||
#define BSP_CFG_RTOS (1)
|
||||
#else
|
||||
#define BSP_CFG_RTOS (0)
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifndef BSP_CFG_RTC_USED
|
||||
#define BSP_CFG_RTC_USED (RA_NOT_DEFINED)
|
||||
#endif
|
||||
|
||||
#undef RA_NOT_DEFINED
|
||||
#if defined(_RA_BOOT_IMAGE)
|
||||
#define BSP_CFG_BOOT_IMAGE (1)
|
||||
#endif
|
||||
|
||||
#define BSP_CFG_MCU_VCC_MV (3300)
|
||||
#define BSP_CFG_STACK_MAIN_BYTES (0x400)
|
||||
#define BSP_CFG_HEAP_BYTES (0x1000)
|
||||
#define BSP_CFG_PARAM_CHECKING_ENABLE (1)
|
||||
#define BSP_CFG_ASSERT (0)
|
||||
#define BSP_CFG_ERROR_LOG (0)
|
||||
|
||||
#define BSP_CFG_PFS_PROTECT ((1))
|
||||
|
||||
#define BSP_CFG_C_RUNTIME_INIT ((1))
|
||||
#define BSP_CFG_EARLY_INIT ((0))
|
||||
|
||||
#define BSP_CFG_STARTUP_CLOCK_REG_NOT_RESET ((0))
|
||||
|
||||
#ifndef BSP_CLOCK_CFG_MAIN_OSC_POPULATED
|
||||
#define BSP_CLOCK_CFG_MAIN_OSC_POPULATED (1)
|
||||
#endif
|
||||
|
||||
#ifndef BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE
|
||||
#define BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE (0)
|
||||
#endif
|
||||
#ifndef BSP_CLOCK_CFG_SUBCLOCK_DRIVE
|
||||
#define BSP_CLOCK_CFG_SUBCLOCK_DRIVE (0)
|
||||
#endif
|
||||
#ifndef BSP_CLOCK_CFG_SUBCLOCK_POPULATED
|
||||
#define BSP_CLOCK_CFG_SUBCLOCK_POPULATED (1)
|
||||
#endif
|
||||
#ifndef BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS
|
||||
#define BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS 1000
|
||||
#endif
|
||||
|
||||
#define BSP_FEATURE_BSP_HAS_SCISPI_CLOCK 0
|
||||
#define BSP_FEATURE_TFU_SUPPORTED 0
|
||||
#define BSP_TZ_SECURE_BUILD (0)
|
||||
#define BSP_TZ_NONSECURE_BUILD (0)
|
||||
|
||||
#define BSP_CFG_USE_LOW_VOLTAGE_MODE 0
|
||||
|
||||
// for SystemInit()
|
||||
void bsp_init(void * p_args);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* BSP_CFG_H_ */
|
||||
|
|
@ -0,0 +1,23 @@
|
|||
/* generated configuration header file - do not edit */
|
||||
#ifndef BSP_CLOCK_CFG_H_
|
||||
#define BSP_CLOCK_CFG_H_
|
||||
#define BSP_CFG_CLOCKS_SECURE (0)
|
||||
#define BSP_CFG_CLOCKS_OVERRIDE (0)
|
||||
#define BSP_CFG_XTAL_HZ (12000000) /* XTAL 12000000Hz */
|
||||
#define BSP_CFG_PLL_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC) /* PLL Src: XTAL */
|
||||
#define BSP_CFG_HOCO_FREQUENCY (2) /* HOCO 20MHz */
|
||||
#define BSP_CFG_PLL_DIV (BSP_CLOCKS_PLL_DIV_1) /* PLL Div /1 */
|
||||
#define BSP_CFG_PLL_MUL BSP_CLOCKS_PLL_MUL_20_0 /* PLL Mul x20.0 */
|
||||
#define BSP_CFG_CLOCK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL) /* Clock Src: PLL */
|
||||
#define BSP_CFG_ICLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* ICLK Div /2 */
|
||||
#define BSP_CFG_PCLKA_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* PCLKA Div /2 */
|
||||
#define BSP_CFG_PCLKB_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_4) /* PCLKB Div /4 */
|
||||
#define BSP_CFG_PCLKC_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_4) /* PCLKC Div /4 */
|
||||
#define BSP_CFG_PCLKD_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* PCLKD Div /2 */
|
||||
#define BSP_CFG_BCLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* BCLK Div /2 */
|
||||
#define BSP_CFG_BCLK_OUTPUT (2) /* EBCLK Div /2 */
|
||||
#define BSP_CFG_UCK_DIV (BSP_CLOCKS_USB_CLOCK_DIV_5) /* UCLK Div /5 */
|
||||
#define BSP_CFG_FCLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_4) /* FCLK Div /4 */
|
||||
#define BSP_CFG_CLKOUT_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* CLKOUT Disabled */
|
||||
#define BSP_CFG_CLKOUT_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* CLKOUT Div /1 */
|
||||
#endif /* BSP_CLOCK_CFG_H_ */
|
||||
|
|
@ -0,0 +1,5 @@
|
|||
/* generated configuration header file - do not edit */
|
||||
#ifndef BSP_MCU_DEVICE_CFG_H_
|
||||
#define BSP_MCU_DEVICE_CFG_H_
|
||||
#define BSP_CFG_MCU_PART_SERIES (6)
|
||||
#endif /* BSP_MCU_DEVICE_CFG_H_ */
|
||||
|
|
@ -0,0 +1,11 @@
|
|||
/* generated configuration header file - do not edit */
|
||||
#ifndef BSP_MCU_DEVICE_PN_CFG_H_
|
||||
#define BSP_MCU_DEVICE_PN_CFG_H_
|
||||
#define BSP_MCU_R7FA6M1AD3CFP
|
||||
#define BSP_MCU_FEATURE_SET ('A')
|
||||
#define BSP_ROM_SIZE_BYTES (524288)
|
||||
#define BSP_RAM_SIZE_BYTES (262144)
|
||||
#define BSP_DATA_FLASH_SIZE_BYTES (8192)
|
||||
#define BSP_PACKAGE_LQFP
|
||||
#define BSP_PACKAGE_PINS (100)
|
||||
#endif /* BSP_MCU_DEVICE_PN_CFG_H_ */
|
||||
|
|
@ -0,0 +1,84 @@
|
|||
/* generated configuration header file - do not edit */
|
||||
#ifndef BSP_MCU_FAMILY_CFG_H_
|
||||
#define BSP_MCU_FAMILY_CFG_H_
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include "bsp_mcu_device_pn_cfg.h"
|
||||
#include "bsp_mcu_device_cfg.h"
|
||||
#include "../../../ra/fsp/src/bsp/mcu/ra6m1/bsp_mcu_info.h"
|
||||
#include "bsp_clock_cfg.h"
|
||||
|
||||
#define BSP_MCU_GROUP_RA6M1 (1)
|
||||
#define BSP_LOCO_HZ (32768)
|
||||
#define BSP_MOCO_HZ (8000000)
|
||||
#define BSP_SUB_CLOCK_HZ (32768)
|
||||
#if BSP_CFG_HOCO_FREQUENCY == 0
|
||||
#define BSP_HOCO_HZ (16000000)
|
||||
#elif BSP_CFG_HOCO_FREQUENCY == 1
|
||||
#define BSP_HOCO_HZ (18000000)
|
||||
#elif BSP_CFG_HOCO_FREQUENCY == 2
|
||||
#define BSP_HOCO_HZ (20000000)
|
||||
#else
|
||||
#error "Invalid HOCO frequency chosen (BSP_CFG_HOCO_FREQUENCY) in bsp_clock_cfg.h"
|
||||
#endif
|
||||
|
||||
#define BSP_CFG_FLL_ENABLE (0)
|
||||
|
||||
#define BSP_CORTEX_VECTOR_TABLE_ENTRIES (16U)
|
||||
#define BSP_VECTOR_TABLE_MAX_ENTRIES (112U)
|
||||
|
||||
#define OFS_SEQ1 0xA001A001 | (1 << 1) | (3 << 2)
|
||||
#define OFS_SEQ2 (15 << 4) | (3 << 8) | (3 << 10)
|
||||
#define OFS_SEQ3 (1 << 12) | (1 << 14) | (1 << 17)
|
||||
#define OFS_SEQ4 (3 << 18) |(15 << 20) | (3 << 24) | (3 << 26)
|
||||
#define OFS_SEQ5 (1 << 28) | (1 << 30)
|
||||
#define BSP_CFG_ROM_REG_OFS0 (OFS_SEQ1 | OFS_SEQ2 | OFS_SEQ3 | OFS_SEQ4 | OFS_SEQ5)
|
||||
#define BSP_CFG_ROM_REG_OFS1 (0xFFFFFEF8 | (1 << 2) | (3) | (1 << 8))
|
||||
#define BSP_CFG_ROM_REG_MPU_PC0_ENABLE (1)
|
||||
#define BSP_CFG_ROM_REG_MPU_PC0_START (0xFFFFFFFC)
|
||||
#define BSP_CFG_ROM_REG_MPU_PC0_END (0xFFFFFFFF)
|
||||
#define BSP_CFG_ROM_REG_MPU_PC1_ENABLE (1)
|
||||
#define BSP_CFG_ROM_REG_MPU_PC1_START (0xFFFFFFFC)
|
||||
#define BSP_CFG_ROM_REG_MPU_PC1_END (0xFFFFFFFF)
|
||||
#define BSP_CFG_ROM_REG_MPU_REGION0_ENABLE (1)
|
||||
#define BSP_CFG_ROM_REG_MPU_REGION0_START (0x00FFFFFC)
|
||||
#define BSP_CFG_ROM_REG_MPU_REGION0_END (0x00FFFFFF)
|
||||
#define BSP_CFG_ROM_REG_MPU_REGION1_ENABLE (1)
|
||||
#define BSP_CFG_ROM_REG_MPU_REGION1_START (0x200FFFFC)
|
||||
#define BSP_CFG_ROM_REG_MPU_REGION1_END (0x200FFFFF)
|
||||
#define BSP_CFG_ROM_REG_MPU_REGION2_ENABLE (1)
|
||||
#define BSP_CFG_ROM_REG_MPU_REGION2_START (0x407FFFFC)
|
||||
#define BSP_CFG_ROM_REG_MPU_REGION2_END (0x407FFFFF)
|
||||
#define BSP_CFG_ROM_REG_MPU_REGION3_ENABLE (1)
|
||||
#define BSP_CFG_ROM_REG_MPU_REGION3_START (0x400DFFFC)
|
||||
#define BSP_CFG_ROM_REG_MPU_REGION3_END (0x400DFFFF)
|
||||
#ifndef BSP_CLOCK_CFG_MAIN_OSC_WAIT
|
||||
#define BSP_CLOCK_CFG_MAIN_OSC_WAIT (9)
|
||||
#endif
|
||||
/* Used to create IELS values for the interrupt initialization table g_interrupt_event_link_select. */
|
||||
#define BSP_PRV_IELS_ENUM(vector) (ELC_ ## vector)
|
||||
|
||||
/*
|
||||
ID Code
|
||||
Note: To permanently lock and disable the debug interface define the BSP_ID_CODE_PERMANENTLY_LOCKED in the compiler settings.
|
||||
WARNING: This will disable debug access to the part and cannot be reversed by a debug probe.
|
||||
*/
|
||||
#if defined(BSP_ID_CODE_PERMANENTLY_LOCKED)
|
||||
#define BSP_CFG_ID_CODE_LONG_1 (0x00000000)
|
||||
#define BSP_CFG_ID_CODE_LONG_2 (0x00000000)
|
||||
#define BSP_CFG_ID_CODE_LONG_3 (0x00000000)
|
||||
#define BSP_CFG_ID_CODE_LONG_4 (0x00000000)
|
||||
#else
|
||||
/* ID CODE: FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF */
|
||||
#define BSP_CFG_ID_CODE_LONG_1 (0xFFFFFFFF)
|
||||
#define BSP_CFG_ID_CODE_LONG_2 (0xFFFFFFFF)
|
||||
#define BSP_CFG_ID_CODE_LONG_3 (0xFFFFFFFF)
|
||||
#define BSP_CFG_ID_CODE_LONG_4 (0xffFFFFFF)
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
#endif /* BSP_MCU_FAMILY_CFG_H_ */
|
||||
|
|
@ -0,0 +1,16 @@
|
|||
/* generated configuration header file - do not edit */
|
||||
#ifndef BSP_PIN_CFG_H_
|
||||
#define BSP_PIN_CFG_H_
|
||||
#include "r_ioport.h"
|
||||
|
||||
/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
|
||||
FSP_HEADER
|
||||
|
||||
extern const ioport_cfg_t g_bsp_pin_cfg; /* RA6M1-EK.pincfg */
|
||||
|
||||
void BSP_PinConfigSecurityInit();
|
||||
|
||||
/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
|
||||
FSP_FOOTER
|
||||
|
||||
#endif /* BSP_PIN_CFG_H_ */
|
||||
|
|
@ -0,0 +1,7 @@
|
|||
/* generated configuration header file - do not edit */
|
||||
#ifndef R_IOPORT_CFG_H_
|
||||
#define R_IOPORT_CFG_H_
|
||||
|
||||
#define IOPORT_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE)
|
||||
|
||||
#endif /* R_IOPORT_CFG_H_ */
|
||||
|
|
@ -0,0 +1,5 @@
|
|||
/* vector numbers are configurable/dynamic, hence this, it will be used inside the port */
|
||||
#define TU_IRQn 0
|
||||
#define USBFS_RESUME_IRQn 1
|
||||
#define USBFS_FIFO_0_IRQn 2
|
||||
#define USBFS_FIFO_1_IRQn 3
|
||||
Loading…
Reference in New Issue