Initial PIC32MM/MX & PIC24 support
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ReimuNotMoe
parent
b624664f52
commit
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/*
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* The MIT License (MIT)
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*
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* Copyright (c) 2020 Koji Kitayama
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* Copyright (c) 2022 Reimu NotMoe <reimu@sudomaker.com>
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*
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* This file is part of the TinyUSB stack.
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*/
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#include "tusb_option.h"
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#if CFG_TUD_ENABLED && \
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(CFG_TUSB_MCU == OPT_MCU_PIC32MX || CFG_TUSB_MCU == OPT_MCU_PIC32MM || \
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CFG_TUSB_MCU == OPT_MCU_PIC32MK || CFG_TUSB_MCU == OPT_MCU_PIC24 || \
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CFG_TUSB_MCU == OPT_MCU_DSPIC33)
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#include <xc.h>
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#include "device/dcd.h"
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#if (CFG_TUSB_MCU == OPT_MCU_PIC32MX || CFG_TUSB_MCU == OPT_MCU_PIC32MM || CFG_TUSB_MCU == OPT_MCU_PIC32MK)
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#define TU_PIC_HAS_MMU 1
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#define TU_PIC_HAS_HW_RMW 1
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#define TU_PIC_INT_SIZE 4
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#elif (CFG_TUSB_MCU == OPT_MCU_PIC24 || CFG_TUSB_MCU == OPT_MCU_DSPIC33)
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#define TU_PIC_HAS_MMU 0
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#define TU_PIC_HAS_HW_RMW 0
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#define TU_PIC_INT_SIZE 2
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#else
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#error Unsupportd PIC MCU
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#endif
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#if TU_PIC_HAS_MMU
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#ifndef KVA_TO_PA
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#define KVA_TO_PA(kva) ((uint32_t)(kva) & 0x1fffffff)
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#endif
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#ifndef PA_TO_KVA1
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#define PA_TO_KVA1(pa) ((uint32_t)(pa) | 0xA0000000)
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#endif
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#else
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#ifndef KVA_TO_PA
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#define KVA_TO_PA(kva) (kva)
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#endif
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#ifndef PA_TO_KVA1
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#define PA_TO_KVA1(pa) (pa)
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#endif
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#endif
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//--------------------------------------------------------------------+
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// MACRO TYPEDEF CONSTANT ENUM DECLARATION
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//--------------------------------------------------------------------+
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enum {
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TOK_PID_OUT = 0x1u,
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TOK_PID_IN = 0x9u,
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TOK_PID_SETUP = 0xDu,
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};
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typedef struct TU_ATTR_PACKED
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{
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union {
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uint32_t head;
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struct {
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union {
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struct {
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uint16_t : 2;
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uint16_t tok_pid : 4;
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uint16_t data : 1;
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uint16_t own : 1;
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uint16_t : 8;
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};
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struct {
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uint16_t : 2;
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uint16_t bdt_stall : 1;
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uint16_t dts : 1;
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uint16_t ninc : 1;
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uint16_t keep : 1;
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uint16_t : 10;
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};
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};
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uint16_t bc : 10;
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uint16_t : 6;
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};
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};
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uint8_t *addr;
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} buffer_descriptor_t;
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TU_VERIFY_STATIC( sizeof(buffer_descriptor_t) == 8, "size is not correct" );
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typedef struct TU_ATTR_PACKED
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{
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union {
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uint32_t state;
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struct {
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uint32_t max_packet_size :11;
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uint32_t : 5;
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uint32_t odd : 1;
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uint32_t :15;
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};
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};
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uint16_t length;
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uint16_t remaining;
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} endpoint_state_t;
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TU_VERIFY_STATIC( sizeof(endpoint_state_t) == 8, "size is not correct" );
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typedef struct
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{
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union {
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/* [#EP][OUT,IN][EVEN,ODD] */
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buffer_descriptor_t bdt[16][2][2];
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uint16_t bda[512];
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};
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TU_ATTR_ALIGNED(4) union {
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endpoint_state_t endpoint[16][2];
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endpoint_state_t endpoint_unified[16 * 2];
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};
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uint8_t setup_packet[8];
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uint8_t addr;
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} dcd_data_t;
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//--------------------------------------------------------------------+
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// INTERNAL OBJECT & FUNCTION DECLARATION
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//--------------------------------------------------------------------+
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// BDT(Buffer Descriptor Table) must be 256-byte aligned
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CFG_TUSB_MEM_SECTION TU_ATTR_ALIGNED(512) volatile static dcd_data_t _dcd;
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TU_VERIFY_STATIC( sizeof(_dcd.bdt) == 512, "size is not correct" );
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#if TU_PIC_INT_SIZE == 4
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typedef uint32_t ep_reg_t;
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#elif TU_PIC_INT_SIZE == 2
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typedef uint16_t ep_reg_t;
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#endif
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static inline volatile void *ep_addr(uint8_t rhport, uint8_t ep_num) {
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#if CFG_TUSB_MCU == OPT_MCU_PIC32MK
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volatile void *ep_reg_base = rhport ? (&U2EP0) : (&U1EP0);
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#else
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volatile void *ep_reg_base = &U1EP0;
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#endif
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return ep_reg_base + 0x10 * ep_num;
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}
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static inline ep_reg_t ep_read(uint8_t rhport, uint8_t ep_num) {
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volatile ep_reg_t *ep = ep_addr(rhport, ep_num);
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return *ep;
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}
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static inline void ep_write(uint8_t rhport, uint8_t ep_num, ep_reg_t val) {
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volatile ep_reg_t *ep = ep_addr(rhport, ep_num);
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*ep = val;
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}
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static inline void ep_clear(uint8_t rhport, uint8_t ep_num, ep_reg_t val) {
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#if TU_PIC_HAS_HW_RMW
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volatile ep_reg_t *ep_clr = (ep_addr(rhport, ep_num) + 0x4);
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*ep_clr = val;
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#else
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ep_reg_t v = ep_read(rhport, ep_num);
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v &= ~val;
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ep_write(rhport, ep_num, v);
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#endif
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}
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static inline void ep_set(uint8_t rhport, uint8_t ep_num, ep_reg_t val) {
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#if TU_PIC_HAS_HW_RMW
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volatile ep_reg_t *ep_s = (ep_addr(rhport, ep_num) + 0x8);
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*ep_s = val;
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#else
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ep_reg_t v = ep_read(rhport, ep_num);
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v |= val;
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ep_write(rhport, ep_num, v);
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#endif
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}
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static inline void intr_enable(uint8_t rhport) {
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#if CFG_TUSB_MCU == OPT_MCU_PIC32MM
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IEC0SET = _IEC0_USBIE_MASK;
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#elif CFG_TUSB_MCU == OPT_MCU_PIC32MX
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IEC1SET = _IEC1_USBIE_MASK;
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#elif CFG_TUSB_MCU == OPT_MCU_PIC32MK
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if (rhport == 0)
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IEC1SET = _IEC1_USB1IE_MASK;
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else
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IEC7SET = _IEC7_USB2IE_MASK;
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#elif (CFG_TUSB_MCU == OPT_MCU_PIC24) || (CFG_TUSB_MCU == OPT_MCU_DSPIC33)
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IEC5bits.USB1IE = 1;
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#endif
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}
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static inline void intr_disable(uint8_t rhport) {
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#if CFG_TUSB_MCU == OPT_MCU_PIC32MM
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IEC0CLR = _IEC0_USBIE_MASK;
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#elif CFG_TUSB_MCU == OPT_MCU_PIC32MX
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IEC1CLR = _IEC1_USBIE_MASK;
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#elif CFG_TUSB_MCU == OPT_MCU_PIC32MK
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if (rhport == 0)
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IEC1CLR = _IEC1_USB1IE_MASK;
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else
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IEC7CLR = _IEC7_USB2IE_MASK;
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#elif (CFG_TUSB_MCU == OPT_MCU_PIC24) || (CFG_TUSB_MCU == OPT_MCU_DSPIC33)
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IEC5bits.USB1IE = 0;
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#endif
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}
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static inline int intr_is_enabled(uint8_t rhport) {
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#if CFG_TUSB_MCU == OPT_MCU_PIC32MM
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return IEC0bits.USBIE;
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#elif CFG_TUSB_MCU == OPT_MCU_PIC32MX
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return IEC1bits.USBIE;
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#elif CFG_TUSB_MCU == OPT_MCU_PIC32MK
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if (rhport == 0)
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return IEC1bits.USB1IE;
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else
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return IEC7bits.USB2IE;
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#elif (CFG_TUSB_MCU == OPT_MCU_PIC24) || (CFG_TUSB_MCU == OPT_MCU_DSPIC33)
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return IEC5bits.USB1IE;
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#endif
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}
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static inline void intr_clear(uint8_t rhport) {
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#if CFG_TUSB_MCU == OPT_MCU_PIC32MM
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IFS0CLR = _IFS0_USBIF_MASK;
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#elif CFG_TUSB_MCU == OPT_MCU_PIC32MX
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IFS1CLR = _IFS1_USBIF_MASK;
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#elif CFG_TUSB_MCU == OPT_MCU_PIC32MK
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if (rhport == 0)
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IFS1CLR = _IFS1_USB1IF_MASK;
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else
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IFS7CLR = _IFS7_USB2IF_MASK;
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#elif (CFG_TUSB_MCU == OPT_MCU_PIC24) || (CFG_TUSB_MCU == OPT_MCU_DSPIC33)
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IFS5bits.USB1IF = 0;
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#endif
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}
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static void prepare_next_setup_packet(uint8_t rhport)
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{
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const unsigned out_odd = _dcd.endpoint[0][0].odd;
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const unsigned in_odd = _dcd.endpoint[0][1].odd;
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TU_ASSERT(0 == _dcd.bdt[0][0][out_odd].own, );
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_dcd.bdt[0][0][out_odd].data = 0;
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_dcd.bdt[0][0][out_odd ^ 1].data = 1;
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_dcd.bdt[0][1][in_odd].data = 1;
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_dcd.bdt[0][1][in_odd ^ 1].data = 0;
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dcd_edpt_xfer(rhport, tu_edpt_addr(0, TUSB_DIR_OUT),
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_dcd.setup_packet, sizeof(_dcd.setup_packet));
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}
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static void process_stall(uint8_t rhport)
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{
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for (int i = 0; i < 16; ++i) {
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unsigned const endpt = ep_read(rhport, i);
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if (endpt & _U1EP0_EPSTALL_MASK) {
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// prepare next setup if endpoint0
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if ( i == 0 ) prepare_next_setup_packet(rhport);
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// clear stall bit
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ep_clear(rhport, i, _U1EP0_EPSTALL_MASK);
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}
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}
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}
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static void process_tokdne(uint8_t rhport)
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{
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uint32_t s = U1STAT;
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U1IR = _U1IR_TRNIF_MASK;
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uint8_t epnum = (s >> _U1STAT_ENDPT0_POSITION);
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uint8_t dir = (s & _U1STAT_DIR_MASK) >> _U1STAT_DIR_POSITION;
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unsigned odd = (s & _U1STAT_PPBI_MASK) ? 1 : 0;
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buffer_descriptor_t *bd = (buffer_descriptor_t *)&_dcd.bda[s];
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endpoint_state_t *ep = &_dcd.endpoint_unified[s >> 3];
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/* fetch pid before discarded by the next steps */
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const unsigned pid = bd->tok_pid;
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/* reset values for a next transfer */
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bd->bdt_stall = 0;
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bd->dts = 1;
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bd->ninc = 0;
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bd->keep = 0;
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/* update the odd variable to prepare for the next transfer */
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ep->odd = odd ^ 1;
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if (pid == TOK_PID_SETUP) {
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dcd_event_setup_received(rhport, (uint8_t *)PA_TO_KVA1(bd->addr), true);
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U1CONCLR = _U1CON_PKTDIS_TOKBUSY_MASK;
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return;
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}
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const unsigned bc = bd->bc;
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const unsigned remaining = ep->remaining - bc;
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if (remaining && bc == ep->max_packet_size) {
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/* continue the transferring consecutive data */
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ep->remaining = remaining;
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const int next_remaining = remaining - ep->max_packet_size;
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if (next_remaining > 0) {
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/* prepare to the after next transfer */
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bd->addr += ep->max_packet_size * 2;
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bd->bc = next_remaining > ep->max_packet_size ? ep->max_packet_size: next_remaining;
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bd->own = 1; /* the own bit must set after addr */
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}
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return;
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}
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const unsigned length = ep->length;
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dcd_event_xfer_complete(rhport,
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tu_edpt_addr(epnum, dir),
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length - remaining, XFER_RESULT_SUCCESS, true);
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if (0 == epnum && 0 == length) {
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/* After completion a ZLP of control transfer,
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* it prepares for the next steup transfer. */
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if (_dcd.addr) {
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/* When the transfer was the SetAddress,
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* the device address should be updated here. */
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U1ADDR = _dcd.addr;
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_dcd.addr = 0;
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}
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prepare_next_setup_packet(rhport);
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}
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}
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static void process_bus_reset(uint8_t rhport)
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{
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U1PWRCCLR = _U1PWRC_USUSPEND_MASK;
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U1CONSET = _U1CON_PPBRST_MASK;
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U1ADDR = 0;
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U1IE = _U1IE_URSTIE_DETACHIE_MASK | _U1IE_TRNIE_MASK | _U1IE_IDLEIE_MASK |
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_U1IE_UERRIE_MASK | _U1IE_STALLIE_MASK;
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U1EP0 = _U1EP0_EPHSHK_MASK | _U1EP0_EPRXEN_MASK | _U1EP0_EPTXEN_MASK;
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for (unsigned i = 1; i < 16; ++i) {
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ep_write(rhport, i, 0);
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}
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buffer_descriptor_t *bd = _dcd.bdt[0][0];
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for (unsigned i = 0; i < sizeof(_dcd.bdt)/sizeof(*bd); ++i, ++bd) {
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bd->head = 0;
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}
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const endpoint_state_t ep0 = {
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.max_packet_size = CFG_TUD_ENDPOINT0_SIZE,
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.odd = 0,
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.length = 0,
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.remaining = 0,
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};
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_dcd.endpoint[0][0] = ep0;
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_dcd.endpoint[0][1] = ep0;
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tu_memclr(_dcd.endpoint[1], sizeof(_dcd.endpoint) - sizeof(_dcd.endpoint[0]));
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_dcd.addr = 0;
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prepare_next_setup_packet(rhport);
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U1CONCLR = _U1CON_PPBRST_MASK;
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dcd_event_bus_reset(rhport, TUSB_SPEED_FULL, true);
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}
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static void process_bus_sleep(uint8_t rhport)
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{
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// Enable resume & disable suspend interrupt
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dcd_event_bus_signal(rhport, DCD_EVENT_SUSPEND, true);
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}
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static void process_bus_resume(uint8_t rhport)
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{
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// Enable suspend & disable resume interrupt
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U1PWRCCLR = _U1PWRC_USUSPEND_MASK;
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U1IECLR = _U1IE_RESUMEIE_MASK;
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U1IESET = _U1IE_IDLEIE_MASK;
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dcd_event_bus_signal(rhport, DCD_EVENT_RESUME, true);
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}
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/*------------------------------------------------------------------*/
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/* Device API
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*------------------------------------------------------------------*/
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void dcd_init(uint8_t rhport)
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{
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intr_disable(rhport);
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intr_clear(rhport);
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#if CFG_TUSB_MCU == OPT_MCU_PIC32MM
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TRISBbits.TRISB6 = 1;
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#endif
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#if (CFG_TUSB_MCU == OPT_MCU_PIC32MX) || (CFG_TUSB_MCU == OPT_MCU_PIC32MM)
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U1PWRCSET = _U1PWRC_USBPWR_MASK;
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#elif CFG_TUSB_MCU == OPT_MCU_PIC32MK
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// TODO
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#elif (CFG_TUSB_MCU == OPT_MCU_PIC24) || (CFG_TUSB_MCU == OPT_MCU_DSPIC33)
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U1PWRCbits.USBPWR = 1;
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#endif
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tu_memclr(&_dcd, sizeof(_dcd));
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uint32_t bdt_phys = KVA_TO_PA((uintptr_t)_dcd.bdt);
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U1BDTP1 = (uint8_t)(bdt_phys >> 8);
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U1BDTP2 = (uint8_t)(bdt_phys >> 16);
|
||||
U1BDTP3 = (uint8_t)(bdt_phys >> 24);
|
||||
|
||||
U1IE = _U1IE_URSTIE_DETACHIE_MASK;
|
||||
|
||||
dcd_connect(rhport);
|
||||
|
||||
}
|
||||
|
||||
void dcd_int_enable(uint8_t rhport)
|
||||
{
|
||||
intr_enable(rhport);
|
||||
}
|
||||
|
||||
void dcd_int_disable(uint8_t rhport)
|
||||
{
|
||||
intr_disable(rhport);
|
||||
}
|
||||
|
||||
void dcd_set_address(uint8_t rhport, uint8_t dev_addr)
|
||||
{
|
||||
_dcd.addr = dev_addr & 0x7F;
|
||||
/* Response with status first before changing device address */
|
||||
dcd_edpt_xfer(rhport, tu_edpt_addr(0, TUSB_DIR_IN), NULL, 0);
|
||||
}
|
||||
|
||||
void dcd_remote_wakeup(uint8_t rhport)
|
||||
{
|
||||
U1CONSET = _U1CON_RESUME_MASK;
|
||||
|
||||
unsigned cnt = 25000000 / 1000;
|
||||
while (cnt--) asm volatile("nop");
|
||||
|
||||
U1CONCLR = _U1CON_RESUME_MASK;
|
||||
}
|
||||
|
||||
void dcd_connect(uint8_t rhport)
|
||||
{
|
||||
while (!U1CONbits.USBEN)
|
||||
U1CONSET = _U1CON_USBEN_SOFEN_MASK;
|
||||
}
|
||||
|
||||
void dcd_disconnect(uint8_t rhport)
|
||||
{
|
||||
U1CON = 0;
|
||||
}
|
||||
|
||||
void dcd_sof_enable(uint8_t rhport, bool en)
|
||||
{
|
||||
(void) rhport;
|
||||
(void) en;
|
||||
}
|
||||
|
||||
//--------------------------------------------------------------------+
|
||||
// Endpoint API
|
||||
//--------------------------------------------------------------------+
|
||||
bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * ep_desc)
|
||||
{
|
||||
const unsigned ep_addr = ep_desc->bEndpointAddress;
|
||||
const unsigned epn = tu_edpt_number(ep_addr);
|
||||
const unsigned dir = tu_edpt_dir(ep_addr);
|
||||
const unsigned xfer = ep_desc->bmAttributes.xfer;
|
||||
endpoint_state_t *ep = &_dcd.endpoint[epn][dir];
|
||||
const unsigned odd = ep->odd;
|
||||
buffer_descriptor_t *bd = _dcd.bdt[epn][dir];
|
||||
|
||||
/* No support for control transfer */
|
||||
TU_ASSERT(epn && (xfer != TUSB_XFER_CONTROL));
|
||||
|
||||
ep->max_packet_size = tu_edpt_packet_size(ep_desc);
|
||||
|
||||
unsigned val = _U1EP0_EPCONDIS_MASK;
|
||||
val |= (xfer != TUSB_XFER_ISOCHRONOUS) ? _U1EP0_EPHSHK_MASK : 0;
|
||||
val |= dir ? _U1EP0_EPTXEN_MASK : _U1EP0_EPRXEN_MASK;
|
||||
|
||||
volatile void *ep_reg_base = &U1EP0;
|
||||
volatile uint32_t *reg_ep = (ep_reg_base + 0x10 * epn);
|
||||
|
||||
*reg_ep |= val;
|
||||
|
||||
if (xfer != TUSB_XFER_ISOCHRONOUS) {
|
||||
bd[odd].dts = 1;
|
||||
bd[odd].data = 0;
|
||||
bd[odd ^ 1].dts = 1;
|
||||
bd[odd ^ 1].data = 1;
|
||||
}
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
void dcd_edpt_close_all(uint8_t rhport)
|
||||
{
|
||||
const unsigned ie = intr_is_enabled(rhport);
|
||||
intr_disable(rhport);
|
||||
|
||||
for (unsigned i = 1; i < 16; ++i) {
|
||||
ep_write(rhport, i, 0);
|
||||
}
|
||||
|
||||
if (ie) intr_enable(rhport);
|
||||
|
||||
buffer_descriptor_t *bd = _dcd.bdt[1][0];
|
||||
for (unsigned i = 2; i < sizeof(_dcd.bdt)/sizeof(*bd); ++i, ++bd) {
|
||||
bd->head = 0;
|
||||
}
|
||||
endpoint_state_t *ep = &_dcd.endpoint[1][0];
|
||||
for (unsigned i = 2; i < sizeof(_dcd.endpoint)/sizeof(*ep); ++i, ++ep) {
|
||||
/* Clear except the odd */
|
||||
ep->max_packet_size = 0;
|
||||
ep->length = 0;
|
||||
ep->remaining = 0;
|
||||
}
|
||||
}
|
||||
|
||||
void dcd_edpt_close(uint8_t rhport, uint8_t ep_addr)
|
||||
{
|
||||
const unsigned epn = tu_edpt_number(ep_addr);
|
||||
const unsigned dir = tu_edpt_dir(ep_addr);
|
||||
endpoint_state_t *ep = &_dcd.endpoint[epn][dir];
|
||||
buffer_descriptor_t *bd = _dcd.bdt[epn][dir];
|
||||
const unsigned msk = dir ? _U1EP0_EPTXEN_MASK : _U1EP0_EPRXEN_MASK;
|
||||
const unsigned ie = intr_is_enabled(rhport);
|
||||
|
||||
intr_disable(rhport);
|
||||
|
||||
ep_clear(rhport, epn, msk);
|
||||
|
||||
ep->max_packet_size = 0;
|
||||
ep->length = 0;
|
||||
ep->remaining = 0;
|
||||
bd[0].head = 0;
|
||||
bd[1].head = 0;
|
||||
|
||||
if (ie) intr_enable(rhport);
|
||||
}
|
||||
|
||||
bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t* buffer, uint16_t total_bytes)
|
||||
{
|
||||
const unsigned epn = tu_edpt_number(ep_addr);
|
||||
const unsigned dir = tu_edpt_dir(ep_addr);
|
||||
endpoint_state_t *ep = &_dcd.endpoint[epn][dir];
|
||||
buffer_descriptor_t *bd = &_dcd.bdt[epn][dir][ep->odd];
|
||||
TU_ASSERT(0 == bd->own);
|
||||
|
||||
const unsigned ie = intr_is_enabled(rhport);
|
||||
|
||||
intr_disable(rhport);
|
||||
|
||||
ep->length = total_bytes;
|
||||
ep->remaining = total_bytes;
|
||||
|
||||
const unsigned mps = ep->max_packet_size;
|
||||
if (total_bytes > mps) {
|
||||
buffer_descriptor_t *next = ep->odd ? bd - 1: bd + 1;
|
||||
/* When total_bytes is greater than the max packet size,
|
||||
* it prepares to the next transfer to avoid NAK in advance. */
|
||||
next->bc = total_bytes >= 2 * mps ? mps: total_bytes - mps;
|
||||
next->addr = (uint8_t *)KVA_TO_PA(buffer + mps);
|
||||
next->own = 1;
|
||||
}
|
||||
bd->bc = total_bytes >= mps ? mps: total_bytes;
|
||||
bd->addr = (uint8_t *)KVA_TO_PA(buffer);
|
||||
// __DSB();
|
||||
bd->own = 1; /* This bit must be set last */
|
||||
|
||||
if (ie) intr_enable(rhport);
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr)
|
||||
{
|
||||
(void) rhport;
|
||||
const unsigned epn = tu_edpt_number(ep_addr);
|
||||
|
||||
if (0 == epn) {
|
||||
ep_set(rhport, epn, _U1EP0_EPSTALL_MASK);
|
||||
} else {
|
||||
const unsigned dir = tu_edpt_dir(ep_addr);
|
||||
const unsigned odd = _dcd.endpoint[epn][dir].odd;
|
||||
buffer_descriptor_t *bd = &_dcd.bdt[epn][dir][odd];
|
||||
TU_ASSERT(0 == bd->own,);
|
||||
|
||||
const unsigned ie = intr_is_enabled(rhport);
|
||||
|
||||
intr_disable(rhport);
|
||||
|
||||
bd->bdt_stall = 1;
|
||||
bd->own = 1; /* This bit must be set last */
|
||||
|
||||
if (ie) intr_enable(rhport);
|
||||
}
|
||||
}
|
||||
|
||||
void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr)
|
||||
{
|
||||
const unsigned epn = tu_edpt_number(ep_addr);
|
||||
TU_VERIFY(epn,);
|
||||
const unsigned dir = tu_edpt_dir(ep_addr);
|
||||
const unsigned odd = _dcd.endpoint[epn][dir].odd;
|
||||
buffer_descriptor_t *bd = _dcd.bdt[epn][dir];
|
||||
TU_VERIFY(bd[odd].own,);
|
||||
|
||||
const unsigned ie = intr_is_enabled(rhport);
|
||||
|
||||
intr_disable(rhport);
|
||||
|
||||
bd[odd].own = 0;
|
||||
|
||||
// clear stall
|
||||
bd[odd].bdt_stall = 0;
|
||||
|
||||
// Reset data toggle
|
||||
bd[odd ].data = 0;
|
||||
bd[odd ^ 1].data = 1;
|
||||
|
||||
// We already cleared this in ISR, but just clear it here to be safe
|
||||
const unsigned endpt = ep_read(rhport, epn);
|
||||
if (endpt & _U1EP0_EPSTALL_MASK) {
|
||||
ep_clear(rhport, endpt, _U1EP0_EPSTALL_MASK);
|
||||
}
|
||||
|
||||
if (ie) intr_enable(rhport);
|
||||
}
|
||||
|
||||
//--------------------------------------------------------------------+
|
||||
// ISR
|
||||
//--------------------------------------------------------------------+
|
||||
void dcd_int_handler(uint8_t rhport)
|
||||
{
|
||||
uint32_t is = U1IR;
|
||||
uint32_t msk = U1IE;
|
||||
|
||||
U1IR = is & ~msk;
|
||||
is &= msk;
|
||||
|
||||
if (is & _U1IR_UERRIF_MASK) {
|
||||
uint32_t es = U1EIR;
|
||||
U1EIR = es;
|
||||
U1IR = is; /* discard any pending events */
|
||||
}
|
||||
|
||||
if (is & _U1IR_URSTIF_DETACHIF_MASK) {
|
||||
U1IR = is; /* discard any pending events */
|
||||
process_bus_reset(rhport);
|
||||
}
|
||||
|
||||
if (is & _U1IR_IDLEIF_MASK) {
|
||||
// Note Host usually has extra delay after bus reset (without SOF), which could falsely
|
||||
// detected as Sleep event. Though usbd has debouncing logic so we are good
|
||||
U1IR = _U1IR_IDLEIF_MASK;
|
||||
process_bus_sleep(rhport);
|
||||
}
|
||||
|
||||
if (is & _U1IR_RESUMEIF_MASK) {
|
||||
U1IR = _U1IR_RESUMEIF_MASK;
|
||||
process_bus_resume(rhport);
|
||||
}
|
||||
|
||||
if (is & _U1IR_SOFIF_MASK) {
|
||||
U1IR = _U1IR_SOFIF_MASK;
|
||||
dcd_event_bus_signal(rhport, DCD_EVENT_SOF, true);
|
||||
}
|
||||
|
||||
if (is & _U1IR_STALLIF_MASK) {
|
||||
U1IR = _U1IR_STALLIF_MASK;
|
||||
process_stall(rhport);
|
||||
}
|
||||
|
||||
if (is & _U1IR_TRNIF_MASK) {
|
||||
process_tokdne(rhport);
|
||||
}
|
||||
|
||||
intr_clear(rhport);
|
||||
|
||||
}
|
||||
|
||||
#endif
|
||||
|
|
@ -146,6 +146,11 @@ typedef int make_iso_compilers_happy;
|
|||
|
||||
// PIC
|
||||
#define OPT_MCU_PIC32MZ 1900 ///< MicroChip PIC32MZ family
|
||||
#define OPT_MCU_PIC32MM 1901 ///< MicroChip PIC32MM family
|
||||
#define OPT_MCU_PIC32MX 1902 ///< MicroChip PIC32MX family
|
||||
#define OPT_MCU_PIC32MK 1903 ///< MicroChip PIC32MK family
|
||||
#define OPT_MCU_PIC24 1910 ///< MicroChip PIC24 family
|
||||
#define OPT_MCU_DSPIC33 1911 ///< MicroChip DSPIC33 family
|
||||
|
||||
// BridgeTek
|
||||
#define OPT_MCU_FT90X 2000 ///< BridgeTek FT90x
|
||||
|
|
|
|||
Loading…
Reference in New Issue