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passkey_fw
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minor rename

This commit is contained in:
hathach 2023-09-09 12:20:16 +07:00
parent 1d68f2a328
commit c074488f75
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GPG Key ID: F5D50C6D51D17CBA
7 changed files with 131 additions and 130 deletions
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10
hw/bsp/nrf/boards/feather_nrf52840_express/board.h
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@ -46,11 +46,11 @@
#define UART_TX_PIN 25
// SPI for USB host shield
#define MAX3421E_SCK_PIN 14
#define MAX3421E_MOSI_PIN 13
#define MAX3421E_MISO_PIN 15
#define MAX3421E_CS_PIN 27
#define MAX3241E_INTR_PIN 26
#define MAX3421_SCK_PIN 14
#define MAX3421_MOSI_PIN 13
#define MAX3421_MISO_PIN 15
#define MAX3421_CS_PIN 27
#define MAX3421_INTR_PIN 26
#ifdef __cplusplus
}

10
hw/bsp/nrf/boards/pca10056/board.h
View File

@ -46,11 +46,11 @@
#define UART_TX_PIN 6
// SPI for USB host shield
#define MAX3421E_SCK_PIN _PINNUM(1, 15)
#define MAX3421E_MOSI_PIN _PINNUM(1, 13)
#define MAX3421E_MISO_PIN _PINNUM(1, 14)
#define MAX3421E_CS_PIN _PINNUM(1, 12)
#define MAX3241E_INTR_PIN _PINNUM(1, 11)
#define MAX3421_SCK_PIN _PINNUM(1, 15)
#define MAX3421_MOSI_PIN _PINNUM(1, 13)
#define MAX3421_MISO_PIN _PINNUM(1, 14)
#define MAX3421_CS_PIN _PINNUM(1, 12)
#define MAX3421_INTR_PIN _PINNUM(1, 11)
#ifdef __cplusplus
}

10
hw/bsp/nrf/boards/pca10095/board.h
View File

@ -46,11 +46,11 @@
#define UART_TX_PIN 33
// SPI for USB host shield
#define MAX3421E_SCK_PIN _PINNUM(1, 15)
#define MAX3421E_MOSI_PIN _PINNUM(1, 13)
#define MAX3421E_MISO_PIN _PINNUM(1, 14)
#define MAX3421E_CS_PIN _PINNUM(1, 12)
#define MAX3241E_INTR_PIN _PINNUM(1, 11)
#define MAX3421_SCK_PIN _PINNUM(1, 15)
#define MAX3421_MOSI_PIN _PINNUM(1, 13)
#define MAX3421_MISO_PIN _PINNUM(1, 14)
#define MAX3421_CS_PIN _PINNUM(1, 12)
#define MAX3421_INTR_PIN _PINNUM(1, 11)
#ifdef __cplusplus
}

22
hw/bsp/nrf/family.c
View File

@ -97,8 +97,8 @@ TU_ATTR_UNUSED static void power_event_handler(nrfx_power_usb_evt_t event) {
#if CFG_TUH_ENABLED && defined(CFG_TUH_MAX3421) && CFG_TUH_MAX3421
static nrfx_spim_t _spi = NRFX_SPIM_INSTANCE(1);
void max3421e_int_handler(nrfx_gpiote_pin_t pin, nrf_gpiote_polarity_t action) {
if (!(pin == MAX3241E_INTR_PIN && action == NRF_GPIOTE_POLARITY_HITOLO)) return;
void max3421_int_handler(nrfx_gpiote_pin_t pin, nrf_gpiote_polarity_t action) {
if (!(pin == MAX3421_INTR_PIN && action == NRF_GPIOTE_POLARITY_HITOLO)) return;
tuh_int_handler(1);
}
@ -207,14 +207,14 @@ void board_init(void) {
#endif
// manually manage CS
nrf_gpio_cfg_output(MAX3421E_CS_PIN);
nrf_gpio_pin_write(MAX3421E_CS_PIN, 1);
nrf_gpio_cfg_output(MAX3421_CS_PIN);
nrf_gpio_pin_write(MAX3421_CS_PIN, 1);
// USB host using max3421e usb controller via SPI
nrfx_spim_config_t cfg = {
.sck_pin = MAX3421E_SCK_PIN,
.mosi_pin = MAX3421E_MOSI_PIN,
.miso_pin = MAX3421E_MISO_PIN,
.sck_pin = MAX3421_SCK_PIN,
.mosi_pin = MAX3421_MOSI_PIN,
.miso_pin = MAX3421_MISO_PIN,
.ss_pin = NRFX_SPIM_PIN_NOT_USED,
.ss_active_high = false,
.irq_priority = 3,
@ -233,8 +233,8 @@ void board_init(void) {
nrfx_gpiote_in_config_t in_config = NRFX_GPIOTE_CONFIG_IN_SENSE_HITOLO(true);
in_config.pull = NRF_GPIO_PIN_PULLUP;
nrfx_gpiote_in_init(MAX3241E_INTR_PIN, &in_config, max3421e_int_handler);
nrfx_gpiote_trigger_enable(MAX3241E_INTR_PIN, true);
nrfx_gpiote_in_init(MAX3421_INTR_PIN, &in_config, max3421_int_handler);
nrfx_gpiote_trigger_enable(MAX3421_INTR_PIN, true);
#endif
}
@ -317,7 +317,7 @@ void nrf_error_cb(uint32_t id, uint32_t pc, uint32_t info) {
//--------------------------------------------------------------------+
#if CFG_TUH_ENABLED && defined(CFG_TUH_MAX3421) && CFG_TUH_MAX3421
void tuh_max3421e_int_api(uint8_t rhport, bool enabled) {
void tuh_max3421_int_api(uint8_t rhport, bool enabled) {
(void) rhport;
// use NVIC_Enable/Disable instead since nrfx_gpiote_trigger_enable/disable clear pending and can miss interrupt
@ -331,7 +331,7 @@ void tuh_max3421e_int_api(uint8_t rhport, bool enabled) {
void tuh_max3421_spi_cs_api(uint8_t rhport, bool active) {
(void) rhport;
nrf_gpio_pin_write(MAX3421E_CS_PIN, active ? 0 : 1);
nrf_gpio_pin_write(MAX3421_CS_PIN, active ? 0 : 1);
}
bool tuh_max3421_spi_xfer_api(uint8_t rhport, uint8_t const *tx_buf, size_t tx_len, uint8_t *rx_buf, size_t rx_len) {

12
hw/bsp/samd51/boards/metro_m4_express/board.h
View File

@ -44,12 +44,12 @@
#define UART_RX_PIN 22
// SPI for USB host shield
#define MAX3421E_SERCOM SERCOM2
#define MAX3421E_SCK_PIN 13
#define MAX3421E_MOSI_PIN 12
#define MAX3421E_MISO_PIN 14
#define MAX3421E_CS_PIN 18 // D10
#define MAX3241E_INTR_PIN 20 // D9
#define MAX3421_SERCOM 2 // SERCOM2
#define MAX3421_SCK_PIN 13
#define MAX3421_MOSI_PIN 12
#define MAX3421_MISO_PIN 14
#define MAX3421_CS_PIN 18 // D10
#define MAX3421_INTR_PIN 20 // D9
#ifdef __cplusplus

183
hw/bsp/samd51/family.c
View File

@ -73,58 +73,14 @@ void USB_3_Handler(void) {
}
//--------------------------------------------------------------------+
//
// Implementation
//--------------------------------------------------------------------+
#if CFG_TUH_ENABLED && defined(CFG_TUH_MAX3421) && CFG_TUH_MAX3421
void max3421_init(void)
{
//------------- SPI Init -------------//
static void max3421_init(void);
// Enable the APB clock for SERCOM2
MCLK->APBBMASK.reg |= MCLK_APBBMASK_SERCOM2;
//#define
// Configure GCLK for SERCOM2, initClockNVIC()
GCLK->PCHCTRL[SERCOM2_GCLK_ID_CORE].reg = GCLK_PCHCTRL_GEN_GCLK0_Val | (1 << GCLK_PCHCTRL_CHEN_Pos);
GCLK->PCHCTRL[SERCOM2_GCLK_ID_SLOW].reg = GCLK_PCHCTRL_GEN_GCLK3_Val | (1 << GCLK_PCHCTRL_CHEN_Pos);
// Disable the SPI module
SERCOM2->SPI.CTRLA.bit.ENABLE = 0;
// Reset the SPI module
SERCOM2->SPI.CTRLA.bit.SWRST = 1;
while (SERCOM2->SPI.SYNCBUSY.bit.SWRST);
// Set up SPI in master mode, MSB first, SPI mode 0
uint8_t const mosi_pad = 0;
uint8_t const miso_pad = 2;
SERCOM2->SPI.CTRLA.reg = SERCOM_SPI_CTRLA_MODE(3) | SERCOM_SPI_CTRLA_DOPO(mosi_pad) | SERCOM_SPI_CTRLA_DIPO(miso_pad);
SERCOM2->SPI.CTRLB.reg = SERCOM_SPI_CTRLB_CHSIZE(0) | SERCOM_SPI_CTRLB_RXEN;
while( SERCOM2->SPI.SYNCBUSY.bit.CTRLB == 1 );
// Set the baud rate
uint32_t baudrate = 4000000u;
SERCOM2->SPI.BAUD.reg = (uint8_t)(SystemCoreClock / (2 * baudrate) - 1); // Replace 1000000 with your desired baud rate
// Configure PA12 as MOSI (PAD0), PA13 as SCK (PAD1), PA14 as MISO (PAD2)
// 2 function C: PIO_SERCOM
gpio_set_pin_direction(MAX3421E_SCK_PIN, GPIO_DIRECTION_OUT);
gpio_set_pin_pull_mode(MAX3421E_SCK_PIN, GPIO_PULL_OFF);
gpio_set_pin_function(MAX3421E_SCK_PIN, 2);
gpio_set_pin_direction(MAX3421E_MOSI_PIN, GPIO_DIRECTION_OUT);
gpio_set_pin_pull_mode(MAX3421E_MOSI_PIN, GPIO_PULL_OFF);
gpio_set_pin_function(MAX3421E_MOSI_PIN, 2);
gpio_set_pin_direction(MAX3421E_MISO_PIN, GPIO_DIRECTION_IN);
gpio_set_pin_pull_mode(MAX3421E_MISO_PIN, GPIO_PULL_OFF);
gpio_set_pin_function(MAX3421E_MISO_PIN, 2);
// Enable the SPI module
SERCOM2->SPI.CTRLA.bit.ENABLE = 1;
while (SERCOM2->SPI.SYNCBUSY.bit.ENABLE);
}
#endif
void board_init(void) {
@ -180,46 +136,7 @@ void board_init(void) {
gpio_set_pin_function(PIN_PA25, PINMUX_PA25H_USB_DP);
#if CFG_TUH_ENABLED && defined(CFG_TUH_MAX3421) && CFG_TUH_MAX3421
// CS pin
gpio_set_pin_direction(MAX3421E_CS_PIN, GPIO_DIRECTION_OUT);
gpio_set_pin_level(MAX3421E_CS_PIN, 1);
// SPI
max3421_init();
// INT pin with external interrupt
gpio_set_pin_direction(MAX3241E_INTR_PIN, GPIO_DIRECTION_IN);
gpio_set_pin_pull_mode(MAX3241E_INTR_PIN, GPIO_PULL_UP);
// Enable the APB clock for EIC (External Interrupt Controller)
MCLK->APBAMASK.reg |= MCLK_APBAMASK_EIC;
// Configure GCLK for EIC
GCLK->PCHCTRL[EIC_GCLK_ID].reg = GCLK_PCHCTRL_GEN_GCLK0_Val | (1 << GCLK_PCHCTRL_CHEN_Pos);
// Configure PA20 as an input
PORT->Group[0].DIRCLR.reg = PORT_PA20;
PORT->Group[0].PINCFG[20].reg = PORT_PINCFG_INEN | PORT_PINCFG_PULLEN;
PORT->Group[0].OUTSET.reg = PORT_PA20; // Enable pull-up
// Configure PA20 to use EIC
PORT->Group[0].PMUX[10].bit.PMUXE = MUX_PA20A_EIC_EXTINT4;
PORT->Group[0].PINCFG[20].bit.PMUXEN = 1;
// Disable EIC
EIC->CTRLA.bit.ENABLE = 0;
while (EIC->SYNCBUSY.bit.ENABLE);
// Configure EXTINT4 (PA20) to trigger on falling edge
EIC->CONFIG[0].reg |= EIC_CONFIG_SENSE4_FALL;
// Enable EXTINT4
EIC->INTENSET.reg = EIC_INTENSET_EXTINT(1 << 4);
// Enable EIC
EIC->CTRLA.bit.ENABLE = 1;
while (EIC->SYNCBUSY.bit.ENABLE);
#endif
}
@ -264,8 +181,91 @@ uint32_t board_millis(void) {
//--------------------------------------------------------------------+
#if CFG_TUH_ENABLED && defined(CFG_TUH_MAX3421) && CFG_TUH_MAX3421
void EIC_4_Handler(void)
{
static void max3421_init(void) {
// CS pin
gpio_set_pin_direction(MAX3421_CS_PIN, GPIO_DIRECTION_OUT);
gpio_set_pin_level(MAX3421_CS_PIN, 1);
//------------- SPI Init -------------//
// Enable the APB clock for SERCOM2
MCLK->APBBMASK.reg |= MCLK_APBBMASK_SERCOM2;
// Configure GCLK for SERCOM2, initClockNVIC()
GCLK->PCHCTRL[SERCOM2_GCLK_ID_CORE].reg = GCLK_PCHCTRL_GEN_GCLK0_Val | (1 << GCLK_PCHCTRL_CHEN_Pos);
GCLK->PCHCTRL[SERCOM2_GCLK_ID_SLOW].reg = GCLK_PCHCTRL_GEN_GCLK3_Val | (1 << GCLK_PCHCTRL_CHEN_Pos);
// Disable the SPI module
SERCOM2->SPI.CTRLA.bit.ENABLE = 0;
// Reset the SPI module
SERCOM2->SPI.CTRLA.bit.SWRST = 1;
while (SERCOM2->SPI.SYNCBUSY.bit.SWRST);
// Set up SPI in master mode, MSB first, SPI mode 0
uint8_t const mosi_pad = 0;
uint8_t const miso_pad = 2;
SERCOM2->SPI.CTRLA.reg = SERCOM_SPI_CTRLA_MODE(3) | SERCOM_SPI_CTRLA_DOPO(mosi_pad) | SERCOM_SPI_CTRLA_DIPO(miso_pad);
SERCOM2->SPI.CTRLB.reg = SERCOM_SPI_CTRLB_CHSIZE(0) | SERCOM_SPI_CTRLB_RXEN;
while (SERCOM2->SPI.SYNCBUSY.bit.CTRLB == 1);
// Set the baud rate
uint32_t baudrate = 4000000u;
SERCOM2->SPI.BAUD.reg = (uint8_t) (SystemCoreClock / (2 * baudrate) -
1); // Replace 1000000 with your desired baud rate
// Configure PA12 as MOSI (PAD0), PA13 as SCK (PAD1), PA14 as MISO (PAD2)
// 2 function C: PIO_SERCOM
gpio_set_pin_direction(MAX3421_SCK_PIN, GPIO_DIRECTION_OUT);
gpio_set_pin_pull_mode(MAX3421_SCK_PIN, GPIO_PULL_OFF);
gpio_set_pin_function(MAX3421_SCK_PIN, 2);
gpio_set_pin_direction(MAX3421_MOSI_PIN, GPIO_DIRECTION_OUT);
gpio_set_pin_pull_mode(MAX3421_MOSI_PIN, GPIO_PULL_OFF);
gpio_set_pin_function(MAX3421_MOSI_PIN, 2);
gpio_set_pin_direction(MAX3421_MISO_PIN, GPIO_DIRECTION_IN);
gpio_set_pin_pull_mode(MAX3421_MISO_PIN, GPIO_PULL_OFF);
gpio_set_pin_function(MAX3421_MISO_PIN, 2);
// Enable the SPI module
SERCOM2->SPI.CTRLA.bit.ENABLE = 1;
while (SERCOM2->SPI.SYNCBUSY.bit.ENABLE);
//------------- External Interrupt -------------//
// INT pin with external interrupt
gpio_set_pin_direction(MAX3421_INTR_PIN, GPIO_DIRECTION_IN);
gpio_set_pin_pull_mode(MAX3421_INTR_PIN, GPIO_PULL_UP);
// Enable the APB clock for EIC (External Interrupt Controller)
MCLK->APBAMASK.reg |= MCLK_APBAMASK_EIC;
// Configure GCLK for EIC
GCLK->PCHCTRL[EIC_GCLK_ID].reg = GCLK_PCHCTRL_GEN_GCLK0_Val | (1 << GCLK_PCHCTRL_CHEN_Pos);
// Configure PA20 as an input with function A (external interrupt)
gpio_set_pin_direction(MAX3421_INTR_PIN, GPIO_DIRECTION_IN);
gpio_set_pin_pull_mode(MAX3421_INTR_PIN, GPIO_PULL_UP);
gpio_set_pin_function(MAX3421_INTR_PIN, 0);
// Disable EIC
EIC->CTRLA.bit.ENABLE = 0;
while (EIC->SYNCBUSY.bit.ENABLE);
// Configure EXTINT4 (PA20) to trigger on falling edge
EIC->CONFIG[0].reg |= EIC_CONFIG_SENSE4_FALL;
// Enable EXTINT4
EIC->INTENSET.reg = EIC_INTENSET_EXTINT(1 << 4);
// Enable EIC
EIC->CTRLA.bit.ENABLE = 1;
while (EIC->SYNCBUSY.bit.ENABLE);
}
void EIC_4_Handler(void) {
// Clear the interrupt flag
EIC->INTFLAG.reg = EIC_INTFLAG_EXTINT(1 << 4);
@ -273,7 +273,7 @@ void EIC_4_Handler(void)
tuh_int_handler(1);
}
void tuh_max3421e_int_api(uint8_t rhport, bool enabled) {
void tuh_max3421_int_api(uint8_t rhport, bool enabled) {
(void) rhport;
if (enabled) {
@ -285,7 +285,7 @@ void tuh_max3421e_int_api(uint8_t rhport, bool enabled) {
void tuh_max3421_spi_cs_api(uint8_t rhport, bool active) {
(void) rhport;
gpio_set_pin_level(MAX3421E_CS_PIN, active ? 0 : 1);
gpio_set_pin_level(MAX3421_CS_PIN, active ? 0 : 1);
}
bool tuh_max3421_spi_xfer_api(uint8_t rhport, uint8_t const *tx_buf, size_t tx_len, uint8_t *rx_buf, size_t rx_len) {
@ -299,7 +299,7 @@ bool tuh_max3421_spi_xfer_api(uint8_t rhport, uint8_t const *tx_buf, size_t tx_l
// Write data to be transmitted
uint8_t data = 0x00;
if (count < tx_len) {
data = tx_buf[count];
data = tx_buf[count];
}
SERCOM2->SPI.DATA.reg = (uint32_t) data;
@ -322,6 +322,7 @@ bool tuh_max3421_spi_xfer_api(uint8_t rhport, uint8_t const *tx_buf, size_t tx_l
return true;
}
#endif
#endif

14
src/portable/analog/max3421/hcd_max3421.c
View File

@ -212,7 +212,7 @@ static max3421_data_t _hcd_data;
void tuh_max3421_spi_cs_api(uint8_t rhport, bool active);
bool tuh_max3421_spi_xfer_api(uint8_t rhport, uint8_t const * tx_buf, size_t tx_len, uint8_t * rx_buf, size_t rx_len);
void tuh_max3421e_int_api(uint8_t rhport, bool enabled);
void tuh_max3421_int_api(uint8_t rhport, bool enabled);
static void handle_connect_irq(uint8_t rhport, bool in_isr);
static inline void hirq_write(uint8_t rhport, uint8_t data, bool in_isr);
@ -225,7 +225,7 @@ static void max3421_spi_lock(uint8_t rhport, bool in_isr) {
// disable interrupt and mutex lock (for pre-emptive RTOS) if not in_isr
if (!in_isr) {
(void) osal_mutex_lock(_hcd_data.spi_mutex, OSAL_TIMEOUT_WAIT_FOREVER);
tuh_max3421e_int_api(rhport, false);
tuh_max3421_int_api(rhport, false);
}
// assert CS
@ -238,7 +238,7 @@ static void max3421_spi_unlock(uint8_t rhport, bool in_isr) {
// mutex unlock and re-enable interrupt
if (!in_isr) {
tuh_max3421e_int_api(rhport, true);
tuh_max3421_int_api(rhport, true);
(void) osal_mutex_unlock(_hcd_data.spi_mutex);
}
}
@ -411,7 +411,7 @@ bool hcd_configure(uint8_t rhport, uint32_t cfg_id, const void* cfg_param) {
bool hcd_init(uint8_t rhport) {
(void) rhport;
tuh_max3421e_int_api(rhport, false);
tuh_max3421_int_api(rhport, false);
tuh_max3421_spi_cs_api(rhport, false);
TU_LOG2_INT(sizeof(max3421_ep_t));
@ -450,7 +450,7 @@ bool hcd_init(uint8_t rhport) {
// Enable IRQ
hien_write(rhport, DEFAULT_HIEN, false);
tuh_max3421e_int_api(rhport, true);
tuh_max3421_int_api(rhport, true);
// Enable Interrupt pin
reg_write(rhport, CPUCTL_ADDR, CPUCTL_IE, false);
@ -461,13 +461,13 @@ bool hcd_init(uint8_t rhport) {
// Enable USB interrupt
// Not actually enable GPIO interrupt, just set variable to prevent handler to process
void hcd_int_enable (uint8_t rhport) {
tuh_max3421e_int_api(rhport, true);
tuh_max3421_int_api(rhport, true);
}
// Disable USB interrupt
// Not actually disable GPIO interrupt, just set variable to prevent handler to process
void hcd_int_disable(uint8_t rhport) {
tuh_max3421e_int_api(rhport, false);
tuh_max3421_int_api(rhport, false);
}
// Get frame number (1ms)