Merge pull request #2291 from hathach/minor-update-max3421
minor update for max3421
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commit
a91b720c2e
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@ -16,7 +16,7 @@
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</envs>
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</envs>
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</ADDITIONAL_GENERATION_ENVIRONMENT>
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</ADDITIONAL_GENERATION_ENVIRONMENT>
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</configuration>
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</configuration>
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<configuration PROFILE_NAME="esp32s3" ENABLED="false" TOOLCHAIN_NAME="ESP-IDF" GENERATION_OPTIONS="-DBOARD=espressif_s3_devkitm">
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<configuration PROFILE_NAME="espressif_s3_devkitm" ENABLED="true" TOOLCHAIN_NAME="ESP-IDF" GENERATION_OPTIONS="-DBOARD=espressif_s3_devkitm -DMAX3421_HOST=1 -DLOG=2">
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<ADDITIONAL_GENERATION_ENVIRONMENT>
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<ADDITIONAL_GENERATION_ENVIRONMENT>
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<envs>
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<envs>
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<env name="ESPBAUD" value="1500000" />
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<env name="ESPBAUD" value="1500000" />
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@ -38,9 +38,9 @@
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// SPI for USB host shield
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// SPI for USB host shield
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#define MAX3421_SPI_HOST SPI2_HOST
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#define MAX3421_SPI_HOST SPI2_HOST
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#define MAX3421_SCK_PIN 36
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#define MAX3421_SCK_PIN 39
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#define MAX3421_MOSI_PIN 35
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#define MAX3421_MOSI_PIN 42
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#define MAX3421_MISO_PIN 37
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#define MAX3421_MISO_PIN 21
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#define MAX3421_CS_PIN 15
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#define MAX3421_CS_PIN 15
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#define MAX3421_INTR_PIN 14
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#define MAX3421_INTR_PIN 14
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@ -433,8 +433,9 @@ bool hcd_init(uint8_t rhport) {
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reg_write(rhport, PINCTL_ADDR, PINCTL_FDUPSPI, false);
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reg_write(rhport, PINCTL_ADDR, PINCTL_FDUPSPI, false);
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// V1 is 0x01, V2 is 0x12, V3 is 0x13
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// V1 is 0x01, V2 is 0x12, V3 is 0x13
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// uint8_t const revision = reg_read(rhport, REVISION_ADDR, false);
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uint8_t const revision = reg_read(rhport, REVISION_ADDR, false);
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// TU_LOG2_HEX(revision);
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TU_ASSERT(revision == 0x01 || revision == 0x12 || revision == 0x13, false);
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TU_LOG2_HEX(revision);
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// reset
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// reset
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reg_write(rhport, USBCTL_ADDR, USBCTL_CHIPRES, false);
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reg_write(rhport, USBCTL_ADDR, USBCTL_CHIPRES, false);
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