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Merge pull request #1931 from branalba/master 

For STM32H7 BSP boards, initialize RCC_...TypeDef structs as empty
This commit is contained in:
Ha Thach 2023-03-09 17:21:58 +07:00 committed by GitHub
parent be66f5f57f 8c8f26f14e
commit 990fb6ae5c
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GPG Key ID: 4AEE18F83AFDEB23
5 changed files with 15 additions and 15 deletions
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6
hw/bsp/stm32h7/boards/daisyseed/board.h
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@ -57,9 +57,9 @@
//--------------------------------------------------------------------+ //--------------------------------------------------------------------+
static inline void board_stm32h7_clock_init(void) static inline void board_stm32h7_clock_init(void)
{ {
RCC_ClkInitTypeDef RCC_ClkInitStruct; RCC_ClkInitTypeDef RCC_ClkInitStruct = { 0 };
RCC_OscInitTypeDef RCC_OscInitStruct; RCC_OscInitTypeDef RCC_OscInitStruct = { 0 };
RCC_PeriphCLKInitTypeDef PeriphClkInitStruct; RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = { 0 };
/*!< Supply configuration update enable */ /*!< Supply configuration update enable */
/* For STM32H750XB, use "HAL_PWREx_ConfigSupply(PWR_LDO_SUPPLY);" */ /* For STM32H750XB, use "HAL_PWREx_ConfigSupply(PWR_LDO_SUPPLY);" */

6
hw/bsp/stm32h7/boards/stm32h723nucleo/board.h
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@ -64,8 +64,8 @@
//--------------------------------------------------------------------+ //--------------------------------------------------------------------+
static inline void board_stm32h7_clock_init(void) static inline void board_stm32h7_clock_init(void)
{ {
RCC_ClkInitTypeDef RCC_ClkInitStruct; RCC_ClkInitTypeDef RCC_ClkInitStruct = { 0 };
RCC_OscInitTypeDef RCC_OscInitStruct; RCC_OscInitTypeDef RCC_OscInitStruct = { 0 };
/* The PWR block is always enabled on the H7 series- there is no clock /* The PWR block is always enabled on the H7 series- there is no clock
enable. For now, use the default VOS3 scale mode (lowest) and limit clock enable. For now, use the default VOS3 scale mode (lowest) and limit clock
@ -111,7 +111,7 @@ static inline void board_stm32h7_clock_init(void)
separate. However, the main system PLL (PLL1) doesn't have a direct separate. However, the main system PLL (PLL1) doesn't have a direct
connection to the USB peripheral clock to generate 48 MHz, so we do this connection to the USB peripheral clock to generate 48 MHz, so we do this
dance. This will connect PLL1's Q output to the USB peripheral clock. */ dance. This will connect PLL1's Q output to the USB peripheral clock. */
RCC_PeriphCLKInitTypeDef RCC_PeriphCLKInitStruct; RCC_PeriphCLKInitTypeDef RCC_PeriphCLKInitStruct = { 0 };
RCC_PeriphCLKInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB; RCC_PeriphCLKInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB;
RCC_PeriphCLKInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_PLL; RCC_PeriphCLKInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_PLL;

6
hw/bsp/stm32h7/boards/stm32h743eval/board.h
View File

@ -63,9 +63,9 @@
//--------------------------------------------------------------------+ //--------------------------------------------------------------------+
static inline void board_stm32h7_clock_init(void) static inline void board_stm32h7_clock_init(void)
{ {
RCC_ClkInitTypeDef RCC_ClkInitStruct; RCC_ClkInitTypeDef RCC_ClkInitStruct = { 0 };
RCC_OscInitTypeDef RCC_OscInitStruct; RCC_OscInitTypeDef RCC_OscInitStruct = { 0 };
RCC_PeriphCLKInitTypeDef PeriphClkInitStruct; RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = { 0 };
/*!< Supply configuration update enable */ /*!< Supply configuration update enable */
HAL_PWREx_ConfigSupply(PWR_LDO_SUPPLY); HAL_PWREx_ConfigSupply(PWR_LDO_SUPPLY);

6
hw/bsp/stm32h7/boards/stm32h743nucleo/board.h
View File

@ -55,8 +55,8 @@
//--------------------------------------------------------------------+ //--------------------------------------------------------------------+
static inline void board_stm32h7_clock_init(void) static inline void board_stm32h7_clock_init(void)
{ {
RCC_ClkInitTypeDef RCC_ClkInitStruct; RCC_ClkInitTypeDef RCC_ClkInitStruct = { 0 };
RCC_OscInitTypeDef RCC_OscInitStruct; RCC_OscInitTypeDef RCC_OscInitStruct = { 0 };
/* The PWR block is always enabled on the H7 series- there is no clock /* The PWR block is always enabled on the H7 series- there is no clock
enable. For now, use the default VOS3 scale mode (lowest) and limit clock enable. For now, use the default VOS3 scale mode (lowest) and limit clock
@ -102,7 +102,7 @@ static inline void board_stm32h7_clock_init(void)
separate. However, the main system PLL (PLL1) doesn't have a direct separate. However, the main system PLL (PLL1) doesn't have a direct
connection to the USB peripheral clock to generate 48 MHz, so we do this connection to the USB peripheral clock to generate 48 MHz, so we do this
dance. This will connect PLL1's Q output to the USB peripheral clock. */ dance. This will connect PLL1's Q output to the USB peripheral clock. */
RCC_PeriphCLKInitTypeDef RCC_PeriphCLKInitStruct; RCC_PeriphCLKInitTypeDef RCC_PeriphCLKInitStruct = { 0 };
RCC_PeriphCLKInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB; RCC_PeriphCLKInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB;
RCC_PeriphCLKInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_PLL; RCC_PeriphCLKInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_PLL;

6
hw/bsp/stm32h7/boards/stm32h745disco/board.h
View File

@ -57,9 +57,9 @@
//--------------------------------------------------------------------+ //--------------------------------------------------------------------+
static inline void board_stm32h7_clock_init(void) static inline void board_stm32h7_clock_init(void)
{ {
RCC_ClkInitTypeDef RCC_ClkInitStruct; RCC_ClkInitTypeDef RCC_ClkInitStruct = { 0 };
RCC_OscInitTypeDef RCC_OscInitStruct; RCC_OscInitTypeDef RCC_OscInitStruct = { 0 };
RCC_PeriphCLKInitTypeDef PeriphClkInitStruct; RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = { 0 };
/*!< Supply configuration update enable */ /*!< Supply configuration update enable */
/* For STM32H750XB, use "HAL_PWREx_ConfigSupply(PWR_LDO_SUPPLY);" */ /* For STM32H750XB, use "HAL_PWREx_ConfigSupply(PWR_LDO_SUPPLY);" */