Trying to setup the mmu
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@ -28,6 +28,7 @@
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#include "board.h"
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#include "board.h"
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#include "io.h"
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#include "io.h"
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#include "mmu.h"
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//--------------------------------------------------------------------+
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//--------------------------------------------------------------------+
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// Forward USB interrupt events to TinyUSB IRQ Handler
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// Forward USB interrupt events to TinyUSB IRQ Handler
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@ -55,6 +56,7 @@ void board_init(void)
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gpio_initOutputPinWithPullNone(18);
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gpio_initOutputPinWithPullNone(18);
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gpio_setPinOutputBool(18, true);
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gpio_setPinOutputBool(18, true);
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gpio_initOutputPinWithPullNone(42);
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gpio_initOutputPinWithPullNone(42);
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setup_mmu_flat_map();
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// gpio_initOutputPinWithPullNone(23);
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// gpio_initOutputPinWithPullNone(23);
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// gpio_initOutputPinWithPullNone(24);
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// gpio_initOutputPinWithPullNone(24);
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// gpio_initOutputPinWithPullNone(25);
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// gpio_initOutputPinWithPullNone(25);
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@ -83,17 +85,17 @@ void board_init(void)
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// gpio_setPinOutputBool(25, true);
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// gpio_setPinOutputBool(25, true);
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print();
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print();
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// gpio_setPinOutputBool(25, false);
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// gpio_setPinOutputBool(25, false);
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while (true) {
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// while (true) {
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// for (size_t i = 0; i < 5; i++) {
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// // for (size_t i = 0; i < 5; i++) {
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for (size_t j = 0; j < 10000000000; j++) {
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// for (size_t j = 0; j < 10000000000; j++) {
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__asm__("nop");
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// __asm__("nop");
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}
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// }
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gpio_setPinOutputBool(42, true);
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// gpio_setPinOutputBool(42, true);
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for (size_t j = 0; j < 10000000000; j++) {
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// for (size_t j = 0; j < 10000000000; j++) {
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__asm__("nop");
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// __asm__("nop");
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}
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// }
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gpio_setPinOutputBool(42, false);
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// gpio_setPinOutputBool(42, false);
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}
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// }
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// while (1) uart_update();
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// while (1) uart_update();
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}
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}
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@ -18,8 +18,9 @@ CFLAGS += \
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SRC_C += \
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SRC_C += \
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src/portable/broadcom/synopsys/dcd_synopsys.c \
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src/portable/broadcom/synopsys/dcd_synopsys.c \
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$(MCU_DIR)/interrupts.c \
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$(MCU_DIR)/io.c \
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$(MCU_DIR)/io.c \
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$(MCU_DIR)/interrupts.c
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$(MCU_DIR)/mmu.c
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CROSS_COMPILE = aarch64-none-elf-
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CROSS_COMPILE = aarch64-none-elf-
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@ -19,7 +19,7 @@ _start:
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adr x0, vectors // load VBAR_EL1 with virtual
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adr x0, vectors // load VBAR_EL1 with virtual
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// msr vbar_el3, x0 // vector table address
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// msr vbar_el3, x0 // vector table address
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msr vbar_el1, x0 // vector table address
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msr vbar_el1, x0 // vector table address
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// msr vbar_el2, x0 // vector table address
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msr vbar_el2, x0 // vector table address
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isb
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isb
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// Clean the BSS section
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// Clean the BSS section
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@ -45,6 +45,8 @@ irq_entry
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mov x0, #\type
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mov x0, #\type
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mrs x1, esr_el1
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mrs x1, esr_el1
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mrs x2, elr_el1
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mrs x2, elr_el1
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mrs x3, esr_el2
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mrs x4, elr_el2
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b err_hang
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b err_hang
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.endm
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.endm
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@ -1,12 +1,20 @@
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SECTIONS
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SECTIONS
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{
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{
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. = 0x80000; /* Kernel load address for AArch64 */
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. = 0x80000; /* Kernel load address for AArch64 */
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.text : { KEEP(*(.text.boot)) *(.text .text.* .gnu.linkonce.t*) }
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.text : {
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.rodata : { *(.rodata .rodata.* .gnu.linkonce.r*) }
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KEEP(*(.text.boot))
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*(.text .text.* .gnu.linkonce.t*)
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}
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.rodata : {
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. = ALIGN(4096);
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*(.rodata .rodata.* .gnu.linkonce.r*)
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}
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PROVIDE(_data = .);
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PROVIDE(_data = .);
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.data : { *(.data .data.* .gnu.linkonce.d*) }
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.data : {
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. = ALIGN(4096);
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*(.data .data.* .gnu.linkonce.d*)
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}
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.bss (NOLOAD) : {
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.bss (NOLOAD) : {
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. = ALIGN(16);
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__bss_start = .;
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__bss_start = .;
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*(.bss .bss.*)
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*(.bss .bss.*)
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*(COMMON)
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*(COMMON)
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@ -0,0 +1,58 @@
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#include <stdbool.h>
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#include <stdint.h>
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#include "mmu.h"
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// Each entry is a gig.
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volatile uint64_t level_1_table[32] __attribute__((aligned(4096)));
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// Third gig has peripherals
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uint64_t level_2_0x0_c000_0000_to_0x1_0000_0000[512] __attribute__((aligned(4096)));
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void setup_mmu_flat_map(void) {
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// Set the first gig to regular access.
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level_1_table[0] = 0x0000000000000000 |
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MM_DESCRIPTOR_MAIR_INDEX(MT_NORMAL_NC) |
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MM_DESCRIPTOR_BLOCK |
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MM_DESCRIPTOR_VALID;
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level_1_table[2] = ((uint64_t) level_2_0x0_c000_0000_to_0x1_0000_0000) |
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MM_DESCRIPTOR_TABLE |
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MM_DESCRIPTOR_VALID;
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// Set peripherals to register access.
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for (uint64_t i = 480; i < 512; i++) {
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level_2_0x0_c000_0000_to_0x1_0000_0000[i] = (0x00000000c0000000 + (i << 21)) |
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MM_DESCRIPTOR_EXECUTE_NEVER |
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MM_DESCRIPTOR_MAIR_INDEX(MT_DEVICE_nGnRnE) |
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MM_DESCRIPTOR_BLOCK |
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MM_DESCRIPTOR_VALID;
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}
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uint64_t mair = MAIR_VALUE;
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uint64_t tcr = TCR_VALUE;
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uint64_t ttbr0 = ((uint64_t) level_1_table) | MM_TTBR_CNP;
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uint64_t sctlr = 0;
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__asm__ volatile (
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// Set MAIR
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"MSR MAIR_EL2, %[mair]\n\t"
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// Set TTBR0
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"MSR TTBR0_EL2, %[ttbr0]\n\t"
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// Set TCR
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"MSR TCR_EL2, %[tcr]\n\t"
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// The ISB forces these changes to be seen before the MMU is enabled.
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"ISB\n\t"
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// Read System Control Register configuration data
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"MRS %[sctlr], SCTLR_EL2\n\t"
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// Write System Control Register configuration data
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"ORR %[sctlr], %[sctlr], #1\n\t"
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// Set [M] bit and enable the MMU.
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"MSR SCTLR_EL2, %[sctlr]\n\t"
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// The ISB forces these changes to be seen by the next instruction
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"ISB"
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: /* No outputs. */
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: [mair] "r" (mair),
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[tcr] "r" (tcr),
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[ttbr0] "r" (ttbr0),
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[sctlr] "r" (sctlr)
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);
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while (true) {}
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}
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@ -0,0 +1,44 @@
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#pragma once
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// From: https://github.com/s-matyukevich/raspberry-pi-os/blob/master/docs/lesson06/rpi-os.md
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/*
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* Memory region attributes:
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*
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* n = AttrIndx[2:0]
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* n MAIR
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* DEVICE_nGnRnE 000 00000000
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* NORMAL_NC 001 01000100
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*/
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#define MT_DEVICE_nGnRnE 0x0
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#define MT_NORMAL_NC 0x1
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#define MT_DEVICE_nGnRnE_FLAGS 0x00
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#define MT_NORMAL_NC_FLAGS 0x44
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#define MAIR_VALUE (MT_DEVICE_nGnRnE_FLAGS << (8 * MT_DEVICE_nGnRnE)) | (MT_NORMAL_NC_FLAGS << (8 * MT_NORMAL_NC))
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#define TCR_T0SZ (64 - 35)
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#define TCR_PS (0x01 << 16) // 36-bit physical address
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#define TCR_TG0_4K (0 << 14)
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#define TCR_SH0_OUTER_SHAREABLE (0x2 << 12)
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#define TCR_VALUE (TCR_T0SZ | TCR_PS | TCR_TG0_4K | TCR_SH0_OUTER_SHAREABLE)
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#define ENTRY_TYPE_TABLE_DESCRIPTOR 0x11
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#define ENTRY_TYPE_BLOCK_ENTRY 0x01
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#define ENTRY_TYPE_TABLE_ENTRY 0x11
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#define ENTRY_TYPE_INVALID 0x00
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#define MM_DESCRIPTOR_VALID (0x1)
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#define MM_DESCRIPTOR_BLOCK (0x0 << 1)
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#define MM_DESCRIPTOR_TABLE (0x1 << 1)
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// Block attributes
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#define MM_DESCRIPTOR_EXECUTE_NEVER (0x1ull << 54)
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#define MM_DESCRIPTOR_CONTIGUOUS (0x1ull << 52)
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#define MM_DESCRIPTOR_MAIR_INDEX(index) (index << 2)
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#define MM_TTBR_CNP (0x1)
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void setup_mmu_flat_map(void);
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