enable DMA for both pd rx, tx
This commit is contained in:
hathach
parent
9c2a8490af
commit
8181d470e5
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@ -31,7 +31,7 @@
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#if CFG_TUSB_MCU == OPT_MCU_STM32G4
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#include "stm32g4xx.h"
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#include "stm32g4xx_hal_dma.h"
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#include "stm32g4xx_ll_dma.h" // for UCLP REQID
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#else
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#error "Unsupported STM32 family"
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#endif
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@ -40,6 +40,12 @@
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//
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//--------------------------------------------------------------------+
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enum {
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IMR_ATTACHED = UCPD_IMR_TXMSGDISCIE | UCPD_IMR_TXMSGSENTIE | UCPD_IMR_TXMSGABTIE | UCPD_IMR_TXUNDIE |
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UCPD_IMR_RXHRSTDETIE | UCPD_IMR_RXOVRIE | UCPD_IMR_RXMSGENDIE | UCPD_IMR_RXORDDETIE |
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UCPD_IMR_HRSTDISCIE | UCPD_IMR_HRSTSENTIE | UCPD_IMR_FRSEVTIE
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};
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#define PHY_SYNC1 0x18u
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#define PHY_SYNC2 0x11u
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#define PHY_SYNC3 0x06u
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@ -57,55 +63,101 @@
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static uint8_t rx_buf[262] TU_ATTR_ALIGNED(4);
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static uint32_t rx_count = 0;
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static uint8_t tx_buf[262] TU_ATTR_ALIGNED(4);
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static uint32_t tx_count;
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static uint32_t tx_index;
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#define CFG_TUC_STM32_DMA_RX { DMA1_Channel1 }
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//#define CFG_TUC_STM32_DMA_TX { DMA1_Channel2 }
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// address of DMA channel rx, tx for each port
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#define CFG_TUC_STM32_DMA { { DMA1_Channel1_BASE, DMA1_Channel2_BASE } }
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#ifdef CFG_TUC_STM32_DMA_RX
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static DMA_Channel_TypeDef* dma_rx_arr[TUP_TYPEC_RHPORTS_NUM] = CFG_TUC_STM32_DMA_RX;
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//--------------------------------------------------------------------+
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// DMA
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//--------------------------------------------------------------------+
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TU_ATTR_ALWAYS_INLINE static inline
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void dma_rx_start(uint8_t rhport)
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{
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DMA_Channel_TypeDef* dma_rx_ch = dma_rx_arr[rhport];
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static const uint32_t dma_addr_arr[TUP_TYPEC_RHPORTS_NUM][2] = CFG_TUC_STM32_DMA;
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dma_rx_ch->CMAR = (uint32_t) rx_buf;
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dma_rx_ch->CNDTR = sizeof(rx_buf);
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dma_rx_ch->CCR |= DMA_CCR_EN;
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TU_ATTR_ALWAYS_INLINE static inline uint32_t dma_get_addr(uint8_t rhport, bool is_rx) {
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return dma_addr_arr[rhport][is_rx ? 0 : 1];
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}
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#endif
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#ifdef CFG_TUC_STM32_DMA_TX
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static DMA_Channel_TypeDef* dma_tx_arr[TUP_TYPEC_RHPORTS_NUM] = CFG_TUC_STM32_DMA_TX;
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#endif
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static void dma_init(uint8_t rhport, bool is_rx) {
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uint32_t dma_addr = dma_get_addr(rhport, is_rx);
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DMA_Channel_TypeDef* dma_ch = (DMA_Channel_TypeDef*) dma_addr;
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uint32_t req_id;
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if (is_rx) {
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// Peripheral -> Memory, Memory inc, 8-bit, High priority
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dma_ch->CCR = DMA_CCR_MINC | DMA_CCR_PL_1;
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dma_ch->CPAR = (uint32_t) &UCPD1->RXDR;
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req_id = LL_DMAMUX_REQ_UCPD1_RX;
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} else {
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// Memory -> Peripheral, Memory inc, 8-bit, High priority
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dma_ch->CCR = DMA_CCR_MINC | DMA_CCR_PL_1 | DMA_CCR_DIR;
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dma_ch->CPAR = (uint32_t) &UCPD1->TXDR;
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req_id = LL_DMAMUX_REQ_UCPD1_TX;
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}
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// find and set up mux channel TODO support mcu with multiple DMAMUXs
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enum {
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CH_DIFF = DMA1_Channel2_BASE - DMA1_Channel1_BASE
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};
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uint32_t mux_ch_num;
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#ifdef DMA2_BASE
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if (dma_addr > DMA2_BASE) {
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mux_ch_num = 8 * ((dma_addr - DMA2_Channel1_BASE) / CH_DIFF);
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} else
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#endif
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{
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mux_ch_num = (dma_addr - DMA1_Channel1_BASE) / CH_DIFF;
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}
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DMAMUX_Channel_TypeDef* mux_ch = DMAMUX1_Channel0 + mux_ch_num;
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uint32_t mux_ccr = mux_ch->CCR & ~(DMAMUX_CxCR_DMAREQ_ID);
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mux_ccr |= req_id;
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mux_ch->CCR = mux_ccr;
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}
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TU_ATTR_ALWAYS_INLINE static inline void dma_start(uint8_t rhport, bool is_rx, void const* buf, uint16_t len) {
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DMA_Channel_TypeDef* dma_ch = (DMA_Channel_TypeDef*) dma_get_addr(rhport, is_rx);
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dma_ch->CMAR = (uint32_t) buf;
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dma_ch->CNDTR = len;
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dma_ch->CCR |= DMA_CCR_EN;
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}
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TU_ATTR_ALWAYS_INLINE static inline void dma_stop(uint8_t rhport, bool is_rx) {
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DMA_Channel_TypeDef* dma_ch = (DMA_Channel_TypeDef*) dma_get_addr(rhport, is_rx);
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dma_ch->CCR &= ~DMA_CCR_EN;
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}
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TU_ATTR_ALWAYS_INLINE static inline void dma_rx_start(uint8_t rhport) {
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dma_start(rhport, true, rx_buf, sizeof(rx_buf));
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}
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TU_ATTR_ALWAYS_INLINE static inline void dma_tx_start(uint8_t rhport, void const* buf, uint16_t len) {
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UCPD1->TX_ORDSET = PHY_ORDERED_SET_SOP;
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UCPD1->TX_PAYSZ = len;
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dma_start(rhport, false, buf, len);
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}
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//--------------------------------------------------------------------+
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//
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//--------------------------------------------------------------------+
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#include "stm32g4xx_ll_dma.h"
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bool tcd_init(uint8_t rhport, tusb_typec_port_type_t port_type) {
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(void) rhport;
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#ifdef CFG_TUC_STM32_DMA_RX
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// Init DMA
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DMA_Channel_TypeDef* dma_rx_ch = dma_rx_arr[rhport];
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// Peripheral -> Memory, Memory inc, 8-bit, High priority
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dma_rx_ch->CCR = DMA_CCR_MINC | DMA_CCR_PL_1;
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dma_rx_ch->CPAR = (uint32_t) &UCPD1->RXDR;
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LL_DMA_SetPeriphRequest(DMA1, LL_DMA_CHANNEL_1, LL_DMAMUX_REQ_UCPD1_RX);
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#endif
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// Init DMA for RX, TX
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dma_init(rhport, true);
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dma_init(rhport, false);
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// Initialization phase: CFG1
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UCPD1->CFG1 = (0x0d << UCPD_CFG1_HBITCLKDIV_Pos) | (0x10 << UCPD_CFG1_IFRGAP_Pos) | (0x07 << UCPD_CFG1_TRANSWIN_Pos) |
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(0x01 << UCPD_CFG1_PSC_UCPDCLK_Pos) | (0x1f << UCPD_CFG1_RXORDSETEN_Pos) |
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(0 << UCPD_CFG1_TXDMAEN_Pos) | (0 << UCPD_CFG1_RXDMAEN_Pos);
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(0x01 << UCPD_CFG1_PSC_UCPDCLK_Pos) | (0x1f << UCPD_CFG1_RXORDSETEN_Pos);
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UCPD1->CFG1 |= UCPD_CFG1_UCPDEN;
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// General programming sequence (with UCPD configured then enabled)
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@ -118,8 +170,7 @@ bool tcd_init(uint8_t rhport, tusb_typec_port_type_t port_type) {
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vstate_cc[0] = (UCPD1->SR >> UCPD_SR_TYPEC_VSTATE_CC1_Pos) & 0x03;
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vstate_cc[1] = (UCPD1->SR >> UCPD_SR_TYPEC_VSTATE_CC2_Pos) & 0x03;
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TU_LOG1_INT(vstate_cc[0]);
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TU_LOG1_INT(vstate_cc[1]);
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TU_LOG1("Initial VState CC1 = %u, CC2 = %u\r\n", vstate_cc[0], vstate_cc[1]);
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// Enable CC1 & CC2 Interrupt
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UCPD1->IMR = UCPD_IMR_TYPECEVT1IE | UCPD_IMR_TYPECEVT2IE;
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@ -142,7 +193,8 @@ void tcd_int_disable(uint8_t rhport) {
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bool tcd_rx_start(uint8_t rhport, uint8_t* buffer, uint16_t total_bytes) {
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(void) rhport;
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(void) buffer;
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(void) total_bytes;
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return true;
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}
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@ -159,8 +211,6 @@ void tcd_int_handler(uint8_t rhport) {
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uint32_t sr = UCPD1->SR;
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sr &= UCPD1->IMR;
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// TU_LOG1("UCPD1_IRQHandler: sr = 0x%08X\n", sr);
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if (sr & (UCPD_SR_TYPECEVT1 | UCPD_SR_TYPECEVT2)) {
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uint32_t vstate_cc[2];
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vstate_cc[0] = (UCPD1->SR >> UCPD_SR_TYPEC_VSTATE_CC1_Pos) & 0x03;
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@ -169,7 +219,6 @@ void tcd_int_handler(uint8_t rhport) {
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TU_LOG1("VState CC1 = %u, CC2 = %u\n", vstate_cc[0], vstate_cc[1]);
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uint32_t cr = UCPD1->CR;
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uint32_t cfg1 = UCPD1->CFG1;
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// TODO only support SNK for now, required highest voltage for now
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// Enable PHY on correct CC and disable Rd on other CC
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@ -189,28 +238,18 @@ void tcd_int_handler(uint8_t rhport) {
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}
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if (cr & UCPD_CR_PHYRXEN) {
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// Enable Interrupt
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uint32_t imr = UCPD1->IMR;
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imr |= UCPD_IMR_TXMSGDISCIE | UCPD_IMR_TXMSGSENTIE | UCPD_IMR_TXMSGABTIE | UCPD_IMR_TXUNDIE |
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UCPD_IMR_RXHRSTDETIE | UCPD_IMR_RXOVRIE | UCPD_IMR_RXMSGENDIE | UCPD_IMR_RXORDDETIE |
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UCPD_IMR_HRSTDISCIE | UCPD_IMR_HRSTSENTIE | UCPD_IMR_FRSEVTIE;
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// Attached
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UCPD1->IMR |= IMR_ATTACHED;
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UCPD1->CFG1 |= UCPD_CFG1_RXDMAEN | UCPD_CFG1_TXDMAEN;
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#ifdef CFG_TUC_STM32_DMA_RX
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cfg1 |= UCPD_CFG1_RXDMAEN;
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dma_rx_start(rhport);
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#else
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imr |= UCPD_IMR_RXNEIE | UCPD_IMR_RXORDDETIE;
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#endif
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#ifndef CFG_TUC_STM32_DMA_TX
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imr |= UCPD_IMR_TXISIE;
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#endif
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UCPD1->IMR = imr;
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}else {
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// Detached
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UCPD1->CFG1 &= ~(UCPD_CFG1_RXDMAEN | UCPD_CFG1_TXDMAEN);
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UCPD1->IMR &= ~IMR_ATTACHED;
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}
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UCPD1->CR = cr;
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UCPD1->CFG1 = cfg1;
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// ack
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UCPD1->ICR = UCPD_ICR_TYPECEVT1CF | UCPD_ICR_TYPECEVT2CF;
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@ -221,27 +260,15 @@ void tcd_int_handler(uint8_t rhport) {
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// SOP: Start of Packet.
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// UCPD1->RX_ORDSET & UCPD_RX_ORDSET_RXORDSET_Msk;
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// reset count when received SOP
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rx_count = 0;
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// ack
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UCPD1->ICR = UCPD_ICR_RXORDDETCF;
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}
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#ifndef CFG_TUC_STM32_DMA_RX
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if (sr & UCPD_SR_RXNE) {
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// TODO DMA later
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do {
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rx_buf[rx_count++] = UCPD1->RXDR;
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} while (UCPD1->SR & UCPD_SR_RXNE);
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// no ack needed
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}
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#endif
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// Received full message
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if (sr & UCPD_SR_RXMSGEND) {
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dma_stop(rhport, true);
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// Skip if CRC failed
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if (!(sr & UCPD_SR_RXERR)) {
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uint32_t payload_size = UCPD1->RX_PAYSZ;
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@ -251,26 +278,23 @@ void tcd_int_handler(uint8_t rhport) {
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(*(tusb_pd_header_t*) tx_buf) = (tusb_pd_header_t) {
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.msg_type = TUSB_PD_CTRL_GOOD_CRC,
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.data_role = 0, // UFP
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.specs_rev = TUSB_PD_REV30,
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.specs_rev = TUSB_PD_REV20,
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.power_role = 0, // Sink
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.msg_id = rx_header->msg_id,
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.n_data_obj = 0,
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.extended = 0
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};
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tx_count = 0;
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// response with good crc
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UCPD1->TX_ORDSET = PHY_ORDERED_SET_SOP;
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UCPD1->TX_PAYSZ = 2;
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UCPD1->CR |= UCPD_CR_TXSEND; // will trigger TXIS interrupt
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dma_tx_start(rhport, tx_buf, 2);
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// notify stack after good crc ?
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UCPD1->CR |= UCPD_CR_TXSEND;
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// notify stack
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}
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#ifdef CFG_TUC_STM32_DMA_RX
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// prepare next receive
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dma_rx_start(rhport);
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#endif
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// ack
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UCPD1->ICR = UCPD_ICR_RXMSGENDCF;
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@ -283,34 +307,19 @@ void tcd_int_handler(uint8_t rhport) {
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}
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//------------- TX -------------//
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if (sr & UCPD_SR_TXIS) {
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// TU_LOG1("TXIS\n");
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// TODO DMA later
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do {
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UCPD1->TXDR = tx_buf[tx_count++];
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} while (UCPD1->SR & UCPD_SR_TXIS);
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// no ack needed
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}
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if (sr & UCPD_SR_TXMSGSENT) {
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// all byte sent
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TU_LOG1("TXMSGSENT\n");
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dma_stop(rhport, false);
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// ack
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UCPD1->ICR = UCPD_ICR_TXMSGSENTCF;
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}
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// if (sr & UCPD_SR_RXNE) {
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// uint8_t data = UCPD1->RXDR;
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// pd_rx_buf[pd_rx_count++] = data;
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// TU_LOG1_HEX(data);
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// }
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// else {
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// TU_LOG_LOCATION();
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// }
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if (sr & (UCPD_SR_TXMSGDISC | UCPD_SR_TXMSGABT | UCPD_SR_TXUND)) {
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TU_LOG1("TX Error\n");
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dma_stop(rhport, false);
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UCPD1->ICR = UCPD_SR_TXMSGDISC | UCPD_SR_TXMSGABT | UCPD_SR_TXUND;
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}
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}
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#endif
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