fix ehci issue with portsc when enable port power and port reset
fix attached device not regconized if attached before power on
This commit is contained in:
hathach
parent
04c759028a
commit
77f0726361
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@ -0,0 +1,10 @@
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<component name="ProjectRunConfigurationManager">
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<configuration default="false" name="rt1060 redlink" type="com.jetbrains.cidr.embedded.customgdbserver.type" factoryName="com.jetbrains.cidr.embedded.customgdbserver.factory" PROGRAM_PARAMS="gdbserver --gdb-port 55503 --semihost-port -1 MIMXRT1062xxxxA:EVK-MIMXRT1060" REDIRECT_INPUT="false" ELEVATE="false" USE_EXTERNAL_CONSOLE="false" PASS_PARENT_ENVS_2="true" PROJECT_NAME="cdc_msc_hid" TARGET_NAME="cdc_msc_hid" CONFIG_NAME="rt1060 evk" version="1" RUN_TARGET_PROJECT_NAME="cdc_msc_hid" RUN_TARGET_NAME="cdc_msc_hid">
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<custom-gdb-server version="1" gdb-connect="tcp::55503" executable="/usr/local/LinkServer/LinkServer" warmup-ms="0" download-type="ALWAYS" reset-cmd="monitor reset" reset-type="AFTER_DOWNLOAD">
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<debugger kind="GDB" isBundled="true" />
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</custom-gdb-server>
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<method v="2">
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<option name="CLION.COMPOUND.BUILD" enabled="true" />
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</method>
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</configuration>
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</component>
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@ -2,6 +2,7 @@ set(MCU_VARIANT MIMXRT1062)
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set(JLINK_DEVICE MIMXRT1062xxx6A)
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set(PYOCD_TARGET mimxrt1060)
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set(NXPLS_DEVICE MIMXRT1062xxxxA:EVK-MIMXRT1060)
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function(update_board TARGET)
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target_sources(${TARGET} PUBLIC
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@ -121,15 +121,26 @@ function(family_configure_target TARGET)
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# Link dependencies
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target_link_libraries(${TARGET} PUBLIC ${BOARD_TARGET} ${TARGET}-tinyusb)
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# Flash Target
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# group target (not yet supported by clion)
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set_target_properties(${TARGET}-tinyusb ${TARGET}-tinyusb_config
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PROPERTIES FOLDER ${TARGET}_sub
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)
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#---------- Flash ----------
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# Flash using pyocd
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add_custom_target(${TARGET}-pyocd
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COMMAND pyocd flash -t ${PYOCD_TARGET} $<TARGET_FILE:${TARGET}>
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)
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# group target
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set_target_properties(${TARGET}-tinyusb ${TARGET}-tinyusb_config
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PROPERTIES FOLDER ${TARGET}_sub
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# Flash using NXP LinkServer (redlink)
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# https://www.nxp.com/design/software/development-software/mcuxpresso-software-and-tools-/linkserver-for-microcontrollers:LINKERSERVER
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# LinkServer has a bug that can only execute with full path otherwise it throws:
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# realpath error: No such file or directory
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execute_process(COMMAND which LinkServer OUTPUT_VARIABLE LINKSERVER_PATH OUTPUT_STRIP_TRAILING_WHITESPACE)
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add_custom_target(${TARGET}-redlink
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COMMAND ${LINKSERVER_PATH} flash ${NXPLS_DEVICE} load $<TARGET_FILE:${TARGET}>
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)
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endfunction()
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@ -79,7 +79,8 @@ typedef struct
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ehci_qhd_t qhd_pool[QHD_MAX];
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ehci_qtd_t qtd_pool[QTD_MAX] TU_ATTR_ALIGNED(32);
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ehci_registers_t* regs;
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ehci_registers_t* regs; // operational register
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ehci_cap_registers_t* cap_regs; // capability register
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volatile uint32_t uframe_number;
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}ehci_data_t;
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@ -87,6 +88,26 @@ typedef struct
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// Periodic frame list must be 4K alignment
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CFG_TUH_MEM_SECTION TU_ATTR_ALIGNED(4096) static ehci_data_t ehci_data;
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//--------------------------------------------------------------------+
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// Debug
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//--------------------------------------------------------------------+
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#if CFG_TUSB_DEBUG >= EHCI_DBG
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static inline void print_portsc(ehci_registers_t* regs)
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{
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TU_LOG_HEX(EHCI_DBG, regs->portsc);
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TU_LOG(EHCI_DBG, " Current Connect Status: %u\r\n", regs->portsc_bm.current_connect_status);
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TU_LOG(EHCI_DBG, " Connect Status Change : %u\r\n", regs->portsc_bm.connect_status_change);
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TU_LOG(EHCI_DBG, " Port Enabled : %u\r\n", regs->portsc_bm.port_enabled);
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TU_LOG(EHCI_DBG, " Port Enabled Change : %u\r\n", regs->portsc_bm.port_enable_change);
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TU_LOG(EHCI_DBG, " Port Reset : %u\r\n", regs->portsc_bm.port_reset);
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TU_LOG(EHCI_DBG, " Port Power : %u\r\n", regs->portsc_bm.port_power);
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}
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#else
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#define print_portsc(_reg)
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#endif
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//--------------------------------------------------------------------+
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// PROTOTYPE
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//--------------------------------------------------------------------+
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@ -152,11 +173,11 @@ void hcd_port_reset(uint8_t rhport)
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ehci_registers_t* regs = ehci_data.regs;
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// regs->portsc_bm.port_enabled = 0; // disable port before reset
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// regs->portsc_bm.port_reset = 1;
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uint32_t portsc = regs->portsc;
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// mask out all change bits since they are Write 1 to clear
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uint32_t portsc = regs->portsc & ~EHCI_PORTSC_MASK_CHANGE_ALL;
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// EHCI Table 2-16 PortSC
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// when software writes Port Reset bit to a one, it must also write a zero to the Port Enable bit.
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portsc &= ~(EHCI_PORTSC_MASK_PORT_EANBLED);
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portsc |= EHCI_PORTSC_MASK_PORT_RESET;
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@ -167,9 +188,14 @@ void hcd_port_reset_end(uint8_t rhport)
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{
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(void) rhport;
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#if 0
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#if 0 // TODO check if this is necessary
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ehci_registers_t* regs = ehci_data.regs;
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regs->portsc_bm.port_reset = 0;
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// mask out all change bits since they are Write 1 to clear
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uint32_t portsc = regs->portsc & ~EHCI_PORTSC_MASK_CHANGE_ALL;
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portsc &= ~(EHCI_PORTSC_MASK_PORT_RESET);
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regs->portsc = portsc;
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#endif
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}
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@ -240,19 +266,26 @@ void hcd_device_close(uint8_t rhport, uint8_t dev_addr)
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bool ehci_init(uint8_t rhport, uint32_t capability_reg, uint32_t operatial_reg)
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{
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(void) capability_reg; // not used yet
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tu_memclr(&ehci_data, sizeof(ehci_data_t));
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ehci_data.regs = (ehci_registers_t* ) operatial_reg;
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ehci_data.regs = (ehci_registers_t*) operatial_reg;
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ehci_data.cap_regs = (ehci_cap_registers_t*) capability_reg;
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ehci_registers_t* regs = ehci_data.regs;
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//------------- CTRLDSSEGMENT Register (skip) -------------//
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//------------- USB INT Register -------------//
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regs->inten = 0; // 1. disable all the interrupt
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regs->status = EHCI_INT_MASK_ALL; // 2. clear all status
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// EHCI 4.1 Host Controller Initialization
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//------------- CTRLDSSEGMENT Register (skip) -------------//
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//------------- USB INT Register -------------//
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// disable all the interrupt
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regs->inten = 0;
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// clear all status except port change since device maybe connected before this driver is initialized
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regs->status = (EHCI_INT_MASK_ALL & ~EHCI_INT_MASK_PORT_CHANGE);
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// Enable interrupts
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regs->inten = EHCI_INT_MASK_ERROR | EHCI_INT_MASK_PORT_CHANGE | EHCI_INT_MASK_ASYNC_ADVANCE |
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EHCI_INT_MASK_NXP_PERIODIC | EHCI_INT_MASK_NXP_ASYNC | EHCI_INT_MASK_FRAMELIST_ROLLOVER;
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@ -316,7 +349,16 @@ bool ehci_init(uint8_t rhport, uint32_t capability_reg, uint32_t operatial_reg)
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FRAMELIST_SIZE_USBCMD_VALUE;
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//------------- ConfigFlag Register (skip) -------------//
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regs->portsc_bm.port_power = 1; // enable port power
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// enable port power bit in portsc. The function of this bit depends on the value of the Port
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// Power Control (PPC) field in the HCSPARAMS register.
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if (ehci_data.cap_regs->hcsparams_bm.port_power_control) {
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// mask out all change bits since they are Write 1 to clear
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uint32_t portsc = (regs->portsc & ~EHCI_PORTSC_MASK_CHANGE_ALL);
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portsc |= ECHI_PORTSC_MASK_PORT_POWER;
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regs->portsc = portsc;
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}
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return true;
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}
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@ -656,26 +698,6 @@ static void xfer_error_isr(uint8_t hostid)
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}
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}
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#if CFG_TUSB_DEBUG >= EHCI_DBG
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static inline void print_portsc(ehci_registers_t* regs)
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{
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TU_LOG_HEX(EHCI_DBG, regs->portsc);
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TU_LOG(EHCI_DBG, " Current Connect Status: %u\r\n", regs->portsc_bm.current_connect_status);
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TU_LOG(EHCI_DBG, " Connect Status Change : %u\r\n", regs->portsc_bm.connect_status_change);
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TU_LOG(EHCI_DBG, " Port Enabled : %u\r\n", regs->portsc_bm.port_enabled);
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TU_LOG(EHCI_DBG, " Port Enabled Change : %u\r\n", regs->portsc_bm.port_enable_change);
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TU_LOG(EHCI_DBG, " Port Reset : %u\r\n", regs->portsc_bm.port_reset);
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TU_LOG(EHCI_DBG, " Port Power : %u\r\n", regs->portsc_bm.port_power);
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}
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#else
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#define print_portsc(_reg)
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#endif
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//------------- Host Controller Driver's Interrupt Handler -------------//
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void hcd_int_handler(uint8_t rhport)
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{
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@ -695,7 +717,7 @@ void hcd_int_handler(uint8_t rhport)
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if (int_status & EHCI_INT_MASK_PORT_CHANGE)
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{
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uint32_t const port_status = regs->portsc & EHCI_PORTSC_MASK_ALL;
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uint32_t const port_status = regs->portsc & EHCI_PORTSC_MASK_CHANGE_ALL;
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print_portsc(regs);
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if (regs->portsc_bm.connect_status_change)
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@ -267,16 +267,15 @@ TU_VERIFY_STATIC( sizeof(ehci_sitd_t) == 32, "size is not correct" );
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//--------------------------------------------------------------------+
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// EHCI Operational Register
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//--------------------------------------------------------------------+
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enum ehci_interrupt_mask_{
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enum {
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EHCI_INT_MASK_USB = TU_BIT(0),
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EHCI_INT_MASK_ERROR = TU_BIT(1),
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EHCI_INT_MASK_PORT_CHANGE = TU_BIT(2),
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EHCI_INT_MASK_FRAMELIST_ROLLOVER = TU_BIT(3),
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EHCI_INT_MASK_PCI_HOST_SYSTEM_ERROR = TU_BIT(4),
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EHCI_INT_MASK_ASYNC_ADVANCE = TU_BIT(5),
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EHCI_INT_MASK_NXP_SOF = TU_BIT(7),
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EHCI_INT_MASK_NXP_SOF = TU_BIT(7),
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EHCI_INT_MASK_NXP_ASYNC = TU_BIT(18),
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EHCI_INT_MASK_NXP_PERIODIC = TU_BIT(19),
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@ -287,7 +286,7 @@ enum ehci_interrupt_mask_{
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EHCI_INT_MASK_NXP_ASYNC | EHCI_INT_MASK_NXP_PERIODIC
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};
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enum ehci_usbcmd_pos_ {
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enum {
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EHCI_USBCMD_POS_RUN_STOP = 0,
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EHCI_USBCMD_POS_FRAMELIST_SIZE = 2,
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EHCI_USBCMD_POS_PERIOD_ENABLE = 4,
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@ -296,24 +295,27 @@ enum ehci_usbcmd_pos_ {
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EHCI_USBCMD_POS_INTERRUPT_THRESHOLD = 16
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};
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enum ehci_portsc_change_mask_{
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enum {
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EHCI_PORTSC_MASK_CURRENT_CONNECT_STATUS = TU_BIT(0),
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EHCI_PORTSC_MASK_CONNECT_STATUS_CHANGE = TU_BIT(1),
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EHCI_PORTSC_MASK_PORT_EANBLED = TU_BIT(2),
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EHCI_PORTSC_MASK_PORT_ENABLE_CHAGNE = TU_BIT(3),
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EHCI_PORTSC_MASK_PORT_ENABLE_CHANGE = TU_BIT(3),
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EHCI_PORTSC_MASK_OVER_CURRENT_CHANGE = TU_BIT(5),
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EHCI_PORTSC_MASK_FORCE_RESUME = TU_BIT(6),
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EHCI_PORTSC_MASK_PORT_SUSPEND = TU_BIT(7),
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EHCI_PORTSC_MASK_PORT_RESET = TU_BIT(8),
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ECHI_PORTSC_MASK_PORT_POWER = TU_BIT(12),
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EHCI_PORTSC_MASK_ALL =
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EHCI_PORTSC_MASK_CONNECT_STATUS_CHANGE |
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EHCI_PORTSC_MASK_PORT_ENABLE_CHAGNE |
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EHCI_PORTSC_MASK_OVER_CURRENT_CHANGE
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EHCI_PORTSC_MASK_CHANGE_ALL =
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EHCI_PORTSC_MASK_CONNECT_STATUS_CHANGE |
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EHCI_PORTSC_MASK_PORT_ENABLE_CHANGE |
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EHCI_PORTSC_MASK_OVER_CURRENT_CHANGE
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};
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typedef volatile struct
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{
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union {
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uint32_t command;
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uint32_t command; // 0x00
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struct {
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uint32_t run_stop : 1 ; ///< 1=Run. 0=Stop
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@ -333,7 +335,7 @@ typedef volatile struct
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};
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union {
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uint32_t status;
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uint32_t status; // 0x04
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struct {
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uint32_t usb : 1 ; ///< qTD with IOC is retired
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@ -357,7 +359,7 @@ typedef volatile struct
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};
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union{
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uint32_t inten;
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uint32_t inten; // 0x08
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struct {
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uint32_t usb : 1 ;
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@ -375,43 +377,87 @@ typedef volatile struct
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}inten_bm;
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};
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uint32_t frame_index ; ///< Micro frame counter
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uint32_t ctrl_ds_seg ; ///< Control Data Structure Segment
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uint32_t periodic_list_base ; ///< Beginning address of perodic frame list
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uint32_t async_list_addr ; ///< Address of next async QHD to be executed
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uint32_t frame_index ; ///< 0x0C Micro frame counter
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uint32_t ctrl_ds_seg ; ///< 0x10 Control Data Structure Segment
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uint32_t periodic_list_base ; ///< 0x14 Beginning address of perodic frame list
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uint32_t async_list_addr ; ///< 0x18 Address of next async QHD to be executed
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uint32_t nxp_tt_control ; ///< nxp embedded transaction translator (reserved by EHCI specs)
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uint32_t reserved[8] ;
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uint32_t config_flag ; ///< not used by NXP
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uint32_t config_flag ; ///< 0x40 not used by NXP
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union {
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uint32_t portsc ; ///< port status and control
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struct {
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uint32_t current_connect_status : 1; ///< 0: No device, 1: Device is present on port
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uint32_t connect_status_change : 1; ///< Change in Current Connect Status
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uint32_t port_enabled : 1; ///< Ports can only be enabled by HC as a part of the reset and enable. SW can write 0 to disable
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uint32_t port_enable_change : 1; ///< Port Enabled has changed
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uint32_t over_current_active : 1; ///< Port has an over-current condition
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uint32_t over_current_change : 1; ///< Change to Over-current Active
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uint32_t force_port_resume : 1; ///< Resume detected/driven on port. This functionality defined for manipulating this bit depends on the value of the Suspend bit.
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uint32_t suspend : 1; ///< Port in suspend state
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uint32_t port_reset : 1; ///< 1=Port is in Reset. 0=Port is not in Reset
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uint32_t nxp_highspeed_status : 1; ///< NXP customized: 0=connected to the port is not in High-speed mode, 1=connected to the port is in High-speed mode
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uint32_t line_status : 2; ///< D+/D- state: 00: SE0, 10: J-state, 01: K-state
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uint32_t port_power : 1; ///< 0= power off, 1= power on
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uint32_t port_owner : 1; ///< not used by NXP
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uint32_t port_indicator_control : 2; ///< 00b: off, 01b: Amber, 10b: green, 11b: undefined
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uint32_t port_test_control : 4; ///< Port test mode, not used by tinyusb
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uint32_t wake_on_connect_enable : 1; ///< Enables device connects as wake-up events
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uint32_t wake_on_disconnect_enable : 1; ///< Enables device disconnects as wake-up events
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uint32_t wake_on_over_current_enable : 1; ///< Enables over-current conditions as wake-up events
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uint32_t nxp_phy_clock_disable : 1; ///< NXP customized: the PHY can be put into Low Power Suspend – Clock Disable when the downstream device has been put into suspend mode or when no downstream device is connected. Low power suspend is completely under the control of software. 0: enable PHY clock, 1: disable PHY clock
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uint32_t nxp_port_force_fullspeed : 1; ///< NXP customized: Writing this bit to a 1 will force the port to only connect at Full Speed. It disables the chirp sequence that allowsthe port to identify itself as High Speed. This is useful for testing FS configurations with a HS host, hub or device.
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uint32_t TU_RESERVED : 1;
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uint32_t nxp_port_speed : 2; ///< NXP customized: This register field indicates the speed atwhich the port is operating. For HS mode operation in the host controllerand HS/FS operation in the device controller the port routing steers data to the Protocol engine. For FS and LS mode operation in the host controller, the port routing steers data to the Protocol Engine w/ Embedded Transaction Translator. 0x0: Fullspeed, 0x1: Lowspeed, 0x2: Highspeed
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// mixed with RW and R/WC bits, care should be taken when writing to this register
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uint32_t portsc ; ///< 0x44 port status and control
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const struct {
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uint32_t current_connect_status : 1; ///< 00: 0: No device, 1: Device is present on port
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uint32_t connect_status_change : 1; ///< 01: [R/WC] Change in Current Connect Status
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uint32_t port_enabled : 1; ///< 02: Ports can only be enabled by HC as a part of the reset and enable. SW can write 0 to disable
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uint32_t port_enable_change : 1; ///< 03: [R/WC] Port Enabled has changed
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uint32_t over_current_active : 1; ///< 04: Port has an over-current condition
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uint32_t over_current_change : 1; ///< 05: [R/WC] Change to Over-current Active
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uint32_t force_port_resume : 1; ///< 06: Resume detected/driven on port. This functionality defined for manipulating this bit depends on the value of the Suspend bit.
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uint32_t suspend : 1; ///< 07: Port in suspend state
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uint32_t port_reset : 1; ///< 08: 1=Port is in Reset. 0=Port is not in Reset
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uint32_t nxp_highspeed_status : 1; ///< 09: NXP customized: 0=connected to the port is not in High-speed mode, 1=connected to the port is in High-speed mode
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uint32_t line_status : 2; ///< 10-11: D+/D- state: 00: SE0, 10: J-state, 01: K-state
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uint32_t port_power : 1; ///< 12: 0= power off, 1= power on
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uint32_t port_owner : 1; ///< 13: not used by NXP
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uint32_t port_indicator_control : 2; ///< 14-15: 00b: off, 01b: Amber, 10b: green, 11b: undefined
|
||||
uint32_t port_test_control : 4; ///< 16-19: Port test mode, not used by tinyusb
|
||||
uint32_t wake_on_connect_enable : 1; ///< 20: Enables device connects as wake-up events
|
||||
uint32_t wake_on_disconnect_enable : 1; ///< 21: Enables device disconnects as wake-up events
|
||||
uint32_t wake_on_over_current_enable : 1; ///< 22: Enables over-current conditions as wake-up events
|
||||
uint32_t nxp_phy_clock_disable : 1; ///< 23: NXP customized: the PHY can be put into Low Power Suspend – Clock Disable when the downstream device has been put into suspend mode or when no downstream device is connected. Low power suspend is completely under the control of software. 0: enable PHY clock, 1: disable PHY clock
|
||||
uint32_t nxp_port_force_fullspeed : 1; ///< 24: NXP customized: Writing this bit to a 1 will force the port to only connect at Full Speed. It disables the chirp sequence that allowsthe port to identify itself as High Speed. This is useful for testing FS configurations with a HS host, hub or device.
|
||||
uint32_t TU_RESERVED : 1; ///< 25
|
||||
uint32_t nxp_port_speed : 2; ///< 26-27: NXP customized: This register field indicates the speed atwhich the port is operating. For HS mode operation in the host controllerand HS/FS operation in the device controller the port routing steers data to the Protocol engine. For FS and LS mode operation in the host controller, the port routing steers data to the Protocol Engine w/ Embedded Transaction Translator. 0x0: Fullspeed, 0x1: Lowspeed, 0x2: Highspeed
|
||||
uint32_t TU_RESERVED : 4;
|
||||
}portsc_bm;
|
||||
};
|
||||
}ehci_registers_t;
|
||||
} ehci_registers_t;
|
||||
|
||||
//--------------------------------------------------------------------+
|
||||
// Capability Registers
|
||||
//--------------------------------------------------------------------+
|
||||
typedef volatile struct {
|
||||
uint8_t caplength; // 0x00
|
||||
uint8_t TU_RESERVED; // 0x01
|
||||
uint16_t hciversion; // 0x02
|
||||
|
||||
union {
|
||||
uint32_t hcsparams; // 0x04
|
||||
struct {
|
||||
uint32_t num_ports : 4; // [00:03]
|
||||
uint32_t port_power_control : 1; // [04]
|
||||
uint32_t TU_RESERVED : 2; // [05:06]
|
||||
uint32_t port_route_rule : 1; // [07]
|
||||
uint32_t n_pcc : 4; // [08:11] Number of Ports per Companion Controller
|
||||
uint32_t n_cc : 4; // [12:15] Number of Companion Controllers
|
||||
uint32_t port_ind : 1; // [16] Port Indicators
|
||||
uint32_t TU_RESERVED : 3; // [17:19]
|
||||
uint32_t n_ptt : 4; // [20:23] ChipIdea: Number of Ports per Transaction Translator
|
||||
uint32_t n_tt : 4; // [24:27] ChipIdea: Number of Transaction Translators
|
||||
uint32_t TU_RESERVED : 4; // [28:31]
|
||||
} hcsparams_bm;
|
||||
};
|
||||
|
||||
union {
|
||||
uint32_t hccparams; // 0x08
|
||||
struct {
|
||||
uint32_t addr_64bit : 1; // [00] 64-bit Addressing Capability
|
||||
uint32_t programmable_frame_list_flag : 1; // [01] Programmable Frame List Flag
|
||||
uint32_t async_park_cap : 1; // [02] Asynchronous Schedule Park Capability
|
||||
uint32_t TU_RESERVED : 1; // [03]
|
||||
uint32_t iso_schedule_threshold : 4; // [4:7] Isochronous Scheduling Threshold
|
||||
uint32_t eecp : 8; // [8:15] EHCI Extended Capabilities Pointer
|
||||
uint32_t TU_RESERVED : 16;// [16:31]
|
||||
} hccparams_bm;
|
||||
};
|
||||
|
||||
uint32_t hcsp_portroute; // 0x0C HCSP Port Route Register
|
||||
} ehci_cap_registers_t;
|
||||
|
||||
TU_VERIFY_STATIC(sizeof(ehci_cap_registers_t) == 16, "size is not correct");
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue