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This commit is contained in:
hathach 2018-03-02 18:13:35 +07:00
parent 633f46432f
commit 5b110f9f58
19 changed files with 7 additions and 1230 deletions
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12
demos/device/device_os_none/.cproject
View File

@ -86,7 +86,7 @@
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@ -180,7 +180,7 @@
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@ -284,7 +284,7 @@
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@ -377,7 +377,7 @@
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@ -474,7 +474,7 @@
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<sourceEntries>
<entry excluding="mcu/lpc43xx/CMSISv2p10_LPC43xx_DriverLib/src/lpc43xx_lcd.c|mcu/lpc43xx/CMSISv2p10_LPC43xx_DriverLib/src/lpc43xx_rtc.c|mcu/lpc43xx/CMSIS_LPC43xx_DriverLib/src/Font5x7.c|mcu/lpc43xx/CMSIS_LPC43xx_DriverLib/src/lpc43xx_sdmmc.c|hw/mcu/nxp/lpc43xx/keil|mcu/lpc43xx/CMSISv2p10_LPC43xx_DriverLib/src/lpc43xx_evrt.c|mcu/lpc43xx/CMSIS_LPC43xx_DriverLib/src/lpc43xx_ssp.c|mcu/lpc43xx/CMSISv2p10_LPC43xx_DriverLib/src/Font5x7.c|mcu/lpc43xx/CMSISv2p10_LPC43xx_DriverLib/src/lpc43xx_ssp.c|mcu/lpc13uxx|mcu/lpc43xx/CMSIS_LPC43xx_DriverLib/src/lpc43xx_sdif.c|mcu/lpc175x_6x|mcu/lpc11uxx|hw/mcu/nxp/lpc11uxx|mcu/lpc43xx/CMSISv2p10_LPC43xx_DriverLib/src/lpc43xx_i2s.c|mcu/lpc43xx/CMSISv2p10_LPC43xx_DriverLib/src/lpc43xx_wwdt.c|mcu/lpc43xx/CMSIS_LPC43xx_DriverLib/src/lpc43xx_can.c|mcu/lpc43xx/CMSIS_LPC43xx_DriverLib/src/lpc43xx_mcpwm.c|hw/mcu/nxp/lpc13uxx|mcu/lpc43xx/CMSIS_LPC43xx_DriverLib/src/lpc43xx_atimer.c|mcu/lpc43xx/CMSISv2p10_LPC43xx_DriverLib/src/lpc43xx_can.c|hw/mcu/nxp/lpc43xx/CMSIS_LPC43xx_DriverLib/src/sdio.c|mcu/lpc43xx/CMSISv2p10_LPC43xx_DriverLib/src/lpc43xx_mcpwm.c|hw/mcu/nxp/lpc175x_6x|mcu/lpc43xx/CMSISv2p10_LPC43xx_DriverLib/src/lpc43xx_atimer.c|mcu/lpc43xx/CMSISv2p10_LPC43xx_DriverLib/src/lpc43xx_sct.c|mcu/lpc43xx/CMSISv2p10_LPC43xx_DriverLib/src/lpc43xx_emc.c|mcu/lpc43xx/CMSISv2p10_LPC43xx_DriverLib/src/debug_frmwrk.c|mcu/lpc43xx/CMSIS_LPC43xx_DriverLib/src/lpc43xx_gpdma.c|mcu/lpc43xx/CMSIS_LPC43xx_DriverLib/src/lpc43xx_adc.c|mcu/lpc43xx/CMSIS_LPC43xx_DriverLib/src/lpc43xx_i2s.c|mcu/lpc43xx/CMSIS_LPC43xx_DriverLib/src/lpc43xx_wwdt.c|mcu/lpc43xx/CMSIS_LPC43xx_DriverLib/src/LCDTerm.c|mcu/lpc43xx/CMSIS_LPC43xx_DriverLib/src/lpc43xx_rgu.c|mcu/lpc43xx/CMSISv2p10_LPC43xx_DriverLib/src/LCDTerm.c|mcu/lpc43xx/CMSIS_LPC43xx_DriverLib/src/lpc43xx_sct.c|mcu/lpc43xx/CMSIS_LPC43xx_DriverLib/src/debug_frmwrk.c|mcu/lpc43xx/CMSIS_LPC43xx_DriverLib/src/lpc43xx_rtc.c|mcu/lpc43xx/CMSISv2p10_LPC43xx_DriverLib/src/sdio.c|mcu/lpc43xx/CMSIS_LPC43xx_DriverLib/src/lpc43xx_evrt.c|mcu/lpc43xx/CMSISv2p10_LPC43xx_DriverLib/src/lpc43xx_gpdma.c|mcu/lpc43xx/CMSISv2p10_LPC43xx_DriverLib/src/lpc43xx_adc.c|mcu/lpc43xx/CMSISv2p10_LPC43xx_DriverLib/src/lpc43xx_timer.c|mcu/lpc43xx/CMSIS_LPC43xx_DriverLib/src/lpc43xx_dac.c|mcu/lpc43xx/CMSIS_LPC43xx_DriverLib/src/lpc43xx_qei.c|mcu/lpc43xx/CMSIS_LPC43xx_DriverLib/src/lpc43xx_rit.c|mcu/lpc43xx/CMSIS_LPC43xx_DriverLib/src/lpc43xx_pwr.c|mcu/lpc43xx/CMSISv2p10_LPC43xx_DriverLib/src/lpc43xx_dac.c|mcu/lpc43xx/CMSISv2p10_LPC43xx_DriverLib/src/lpc43xx_qei.c|mcu/lpc43xx/CMSISv2p10_LPC43xx_DriverLib/src/lpc43xx_rit.c|mcu/lpc43xx/CMSIS_LPC43xx_DriverLib/src/lpc43xx_emc.c|mcu/lpc43xx/CMSIS_LPC43xx_DriverLib/src/lpc43xx_lcd.c|mcu/lpc43xx/CMSIS_LPC43xx_DriverLib/src/sdio.c" flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name=""/>
<entry excluding="hw/bsp/lpcxpresso1769/startup|hw/bsp/lpcxpresso1347/startup|hw/bsp/lpcxpresso11u68/startup|hw/bsp/lpcxpresso11u68/startup/xpresso/cr_startup_lpc11u.c|mcu/lpc43xx/CMSISv2p10_LPC43xx_DriverLib/src/lpc43xx_lcd.c|mcu/lpc43xx/CMSISv2p10_LPC43xx_DriverLib/src/lpc43xx_rtc.c|mcu/lpc43xx/CMSIS_LPC43xx_DriverLib/src/Font5x7.c|mcu/lpc43xx/CMSIS_LPC43xx_DriverLib/src/lpc43xx_sdmmc.c|hw/mcu/nxp/lpc43xx/keil|mcu/lpc43xx/CMSISv2p10_LPC43xx_DriverLib/src/lpc43xx_evrt.c|mcu/lpc43xx/CMSIS_LPC43xx_DriverLib/src/lpc43xx_ssp.c|mcu/lpc43xx/CMSISv2p10_LPC43xx_DriverLib/src/Font5x7.c|mcu/lpc43xx/CMSISv2p10_LPC43xx_DriverLib/src/lpc43xx_ssp.c|mcu/lpc13uxx|mcu/lpc43xx/CMSIS_LPC43xx_DriverLib/src/lpc43xx_sdif.c|mcu/lpc175x_6x|mcu/lpc11uxx|hw/mcu/nxp/lpc11uxx|mcu/lpc43xx/CMSISv2p10_LPC43xx_DriverLib/src/lpc43xx_i2s.c|mcu/lpc43xx/CMSISv2p10_LPC43xx_DriverLib/src/lpc43xx_wwdt.c|mcu/lpc43xx/CMSIS_LPC43xx_DriverLib/src/lpc43xx_can.c|mcu/lpc43xx/CMSIS_LPC43xx_DriverLib/src/lpc43xx_mcpwm.c|hw/mcu/nxp/lpc13uxx|mcu/lpc43xx/CMSIS_LPC43xx_DriverLib/src/lpc43xx_atimer.c|mcu/lpc43xx/CMSISv2p10_LPC43xx_DriverLib/src/lpc43xx_can.c|hw/mcu/nxp/lpc43xx/CMSIS_LPC43xx_DriverLib/src/sdio.c|mcu/lpc43xx/CMSISv2p10_LPC43xx_DriverLib/src/lpc43xx_mcpwm.c|hw/mcu/nxp/lpc175x_6x|mcu/lpc43xx/CMSISv2p10_LPC43xx_DriverLib/src/lpc43xx_atimer.c|mcu/lpc43xx/CMSISv2p10_LPC43xx_DriverLib/src/lpc43xx_sct.c|mcu/lpc43xx/CMSISv2p10_LPC43xx_DriverLib/src/lpc43xx_emc.c|mcu/lpc43xx/CMSISv2p10_LPC43xx_DriverLib/src/debug_frmwrk.c|mcu/lpc43xx/CMSIS_LPC43xx_DriverLib/src/lpc43xx_gpdma.c|mcu/lpc43xx/CMSIS_LPC43xx_DriverLib/src/lpc43xx_adc.c|mcu/lpc43xx/CMSIS_LPC43xx_DriverLib/src/lpc43xx_i2s.c|mcu/lpc43xx/CMSIS_LPC43xx_DriverLib/src/lpc43xx_wwdt.c|mcu/lpc43xx/CMSIS_LPC43xx_DriverLib/src/LCDTerm.c|mcu/lpc43xx/CMSIS_LPC43xx_DriverLib/src/lpc43xx_rgu.c|mcu/lpc43xx/CMSISv2p10_LPC43xx_DriverLib/src/LCDTerm.c|mcu/lpc43xx/CMSIS_LPC43xx_DriverLib/src/lpc43xx_sct.c|mcu/lpc43xx/CMSIS_LPC43xx_DriverLib/src/debug_frmwrk.c|mcu/lpc43xx/CMSIS_LPC43xx_DriverLib/src/lpc43xx_rtc.c|mcu/lpc43xx/CMSISv2p10_LPC43xx_DriverLib/src/sdio.c|mcu/lpc43xx/CMSIS_LPC43xx_DriverLib/src/lpc43xx_evrt.c|mcu/lpc43xx/CMSISv2p10_LPC43xx_DriverLib/src/lpc43xx_gpdma.c|mcu/lpc43xx/CMSISv2p10_LPC43xx_DriverLib/src/lpc43xx_adc.c|mcu/lpc43xx/CMSISv2p10_LPC43xx_DriverLib/src/lpc43xx_timer.c|mcu/lpc43xx/CMSIS_LPC43xx_DriverLib/src/lpc43xx_dac.c|mcu/lpc43xx/CMSIS_LPC43xx_DriverLib/src/lpc43xx_qei.c|mcu/lpc43xx/CMSIS_LPC43xx_DriverLib/src/lpc43xx_rit.c|mcu/lpc43xx/CMSIS_LPC43xx_DriverLib/src/lpc43xx_pwr.c|mcu/lpc43xx/CMSISv2p10_LPC43xx_DriverLib/src/lpc43xx_dac.c|mcu/lpc43xx/CMSISv2p10_LPC43xx_DriverLib/src/lpc43xx_qei.c|mcu/lpc43xx/CMSISv2p10_LPC43xx_DriverLib/src/lpc43xx_rit.c|mcu/lpc43xx/CMSIS_LPC43xx_DriverLib/src/lpc43xx_emc.c|mcu/lpc43xx/CMSIS_LPC43xx_DriverLib/src/lpc43xx_lcd.c|mcu/lpc43xx/CMSIS_LPC43xx_DriverLib/src/sdio.c" flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name=""/>
</sourceEntries>
</configuration>
</storageModule>
@ -567,7 +567,7 @@
</toolChain>
</folderInfo>
<sourceEntries>
<entry excluding="mcu/lpc13uxx|hw/mcu/nxp/lpc13uxx|boards/embedded_artists/ea4357|mcu/lpc43xx|hw/mcu/nxp/lpc11uxx|mcu/lpc175x_6x|hw/mcu/nxp/lpc43xx|boards/embedded_artists/oem_base_board|hw/mcu/nxp/lpc175x_6x" flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name=""/>
<entry excluding="hw/bsp/lpcxpresso1769/startup|hw/bsp/lpcxpresso1347/startup|hw/bsp/lpcxpresso11u68/startup|hw/bsp/lpcxpresso11u68/startup/xpresso/cr_startup_lpc11u.c|mcu/lpc13uxx|hw/mcu/nxp/lpc13uxx|boards/embedded_artists/ea4357|mcu/lpc43xx|hw/mcu/nxp/lpc11uxx|mcu/lpc175x_6x|hw/mcu/nxp/lpc43xx|boards/embedded_artists/oem_base_board|hw/mcu/nxp/lpc175x_6x" flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name=""/>
</sourceEntries>
</configuration>
</storageModule>

2
demos/device/device_os_none/.project
View File

@ -83,7 +83,7 @@
<link>
<name>hw</name>
<type>2</type>
<location>/home/hathach/Dropbox/tinyusb/workspace/tinyusb/hw</location>
<locationURI>PARENT-3-PROJECT_LOC/hw</locationURI>
</link>
<link>
<name>src</name>

0
hw/bsp/lpcxpresso/board_lpcxpresso11u68.c → hw/bsp/lpcxpresso11u68/board_lpcxpresso11u68.c
View File

0
hw/bsp/lpcxpresso/board_lpcxpresso11u68.h → hw/bsp/lpcxpresso11u68/board_lpcxpresso11u68.h
View File

0
hw/mcu/nxp/lpc11uxx/lpcxpresso/cr_startup_lpc11u.c → hw/bsp/lpcxpresso11u68/startup/xpresso/cr_startup_lpc11u.c
View File

0
hw/bsp/lpcxpresso/board_lpcxpresso1347.c → hw/bsp/lpcxpresso1347/board_lpcxpresso1347.c
View File

0
hw/bsp/lpcxpresso/board_lpcxpresso1347.h → hw/bsp/lpcxpresso1347/board_lpcxpresso1347.h
View File

0
hw/mcu/nxp/lpc13uxx/lpcxpresso/cr_startup_lpc13u.c → hw/bsp/lpcxpresso1347/startup/xpresso/cr_startup_lpc13u.c
View File

0
hw/bsp/lpcxpresso/board_lpcxpresso1769.c → hw/bsp/lpcxpresso1769/board_lpcxpresso1769.c
View File

0
hw/bsp/lpcxpresso/board_lpcxpresso1769.h → hw/bsp/lpcxpresso1769/board_lpcxpresso1769.h
View File

0
hw/mcu/nxp/lpc175x_6x/lpcxpresso/cr_startup_lpc176x.c → hw/bsp/lpcxpresso1769/startup/xpresso/cr_startup_lpc176x.c
View File

19
hw/mcu/nxp/lpc11uxx/keil/lpc11uxx.sct
View File

@ -1,19 +0,0 @@
; *************************************************************
; *** Scatter-Loading Description File generated by uVision ***
; *************************************************************
LR_IROM1 0x00000000 0x00020000 { ; load region size_region
ER_IROM1 0x00000000 0x00020000 { ; load address = execution address
*.o (RESET, +First)
*(InRoot$$Sections)
.ANY (+RO)
}
RW_IRAM1 0x10000000 0x00002000 { ; RW data
.ANY (+RW +ZI)
}
RW_IRAM2 0x20004000 0x00000800 {
*(USBRAM_SECTION)
}
}

252
hw/mcu/nxp/lpc11uxx/keil/startup_LPC11Uxx.s
View File

@ -1,252 +0,0 @@
;/**************************************************************************//**
; * @file startup_LPC11Uxx.s
; * @brief CMSIS Cortex-M0 Core Device Startup File
; * for the NXP LPC11Uxx Device Series
; * @version V1.10
; * @date 24. November 2010
; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
; *
; * @note
; * Copyright (C) 2009-2010 ARM Limited. All rights reserved.
; *
; * @par
; * ARM Limited (ARM) is supplying this software for use with Cortex-M
; * processor based microcontrollers. This file can be freely distributed
; * within development tools that are supporting such ARM based processors.
; *
; * @par
; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
; *
; ******************************************************************************/
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000200
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000100
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD FLEX_INT0_IRQHandler ; All GPIO pin can be routed to FLEX_INTx
DCD FLEX_INT1_IRQHandler
DCD FLEX_INT2_IRQHandler
DCD FLEX_INT3_IRQHandler
DCD FLEX_INT4_IRQHandler
DCD FLEX_INT5_IRQHandler
DCD FLEX_INT6_IRQHandler
DCD FLEX_INT7_IRQHandler
DCD GINT0_IRQHandler
DCD GINT1_IRQHandler ; PIO0 (0:7)
DCD Reserved_IRQHandler ; Reserved
DCD Reserved_IRQHandler
DCD Reserved_IRQHandler
DCD Reserved_IRQHandler
DCD SSP1_IRQHandler ; SSP1
DCD I2C_IRQHandler ; I2C
DCD TIMER16_0_IRQHandler ; 16-bit Timer0
DCD TIMER16_1_IRQHandler ; 16-bit Timer1
DCD TIMER32_0_IRQHandler ; 32-bit Timer0
DCD TIMER32_1_IRQHandler ; 32-bit Timer1
DCD SSP0_IRQHandler ; SSP0
DCD UART_IRQHandler ; UART
DCD USB_IRQHandler ; USB IRQ
DCD USB_FIQHandler ; USB FIQ
DCD ADC_IRQHandler ; A/D Converter
DCD WDT_IRQHandler ; Watchdog timer
DCD BOD_IRQHandler ; Brown Out Detect
DCD FMC_IRQHandler ; IP2111 Flash Memory Controller
DCD Reserved_IRQHandler ; Reserved
DCD Reserved_IRQHandler ; Reserved
DCD USBWakeup_IRQHandler ; USB wake up
DCD Reserved_IRQHandler ; Reserved
IF :LNOT::DEF:NO_CRP
AREA |.ARM.__at_0x02FC|, CODE, READONLY
CRP_Key DCD 0xFFFFFFFF
ENDIF
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
; now, under COMMON NMI.c and NMI.h, a real NMI handler is created if NMI is enabled
; for particular peripheral.
;NMI_Handler PROC
; EXPORT NMI_Handler [WEAK]
; B .
; ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Reserved_IRQHandler PROC
EXPORT Reserved_IRQHandler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT NMI_Handler [WEAK]
EXPORT FLEX_INT0_IRQHandler [WEAK]
EXPORT FLEX_INT1_IRQHandler [WEAK]
EXPORT FLEX_INT2_IRQHandler [WEAK]
EXPORT FLEX_INT3_IRQHandler [WEAK]
EXPORT FLEX_INT4_IRQHandler [WEAK]
EXPORT FLEX_INT5_IRQHandler [WEAK]
EXPORT FLEX_INT6_IRQHandler [WEAK]
EXPORT FLEX_INT7_IRQHandler [WEAK]
EXPORT GINT0_IRQHandler [WEAK]
EXPORT GINT1_IRQHandler [WEAK]
EXPORT SSP1_IRQHandler [WEAK]
EXPORT I2C_IRQHandler [WEAK]
EXPORT TIMER16_0_IRQHandler [WEAK]
EXPORT TIMER16_1_IRQHandler [WEAK]
EXPORT TIMER32_0_IRQHandler [WEAK]
EXPORT TIMER32_1_IRQHandler [WEAK]
EXPORT SSP0_IRQHandler [WEAK]
EXPORT UART_IRQHandler [WEAK]
EXPORT USB_IRQHandler [WEAK]
EXPORT USB_FIQHandler [WEAK]
EXPORT ADC_IRQHandler [WEAK]
EXPORT WDT_IRQHandler [WEAK]
EXPORT BOD_IRQHandler [WEAK]
EXPORT FMC_IRQHandler [WEAK]
EXPORT USBWakeup_IRQHandler [WEAK]
NMI_Handler
FLEX_INT0_IRQHandler
FLEX_INT1_IRQHandler
FLEX_INT2_IRQHandler
FLEX_INT3_IRQHandler
FLEX_INT4_IRQHandler
FLEX_INT5_IRQHandler
FLEX_INT6_IRQHandler
FLEX_INT7_IRQHandler
GINT0_IRQHandler
GINT1_IRQHandler
SSP1_IRQHandler
I2C_IRQHandler
TIMER16_0_IRQHandler
TIMER16_1_IRQHandler
TIMER32_0_IRQHandler
TIMER32_1_IRQHandler
SSP0_IRQHandler
UART_IRQHandler
USB_IRQHandler
USB_FIQHandler
ADC_IRQHandler
WDT_IRQHandler
BOD_IRQHandler
FMC_IRQHandler
USBWakeup_IRQHandler
B .
ENDP
ALIGN
; User Initial Stack & Heap
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END

18
hw/mcu/nxp/lpc13uxx/keil/lpc13uxx.sct
View File

@ -1,18 +0,0 @@
; *************************************************************
; *** Scatter-Loading Description File generated by uVision ***
; *************************************************************
LR_IROM1 0x00000000 0x00010000 { ; load region size_region
ER_IROM1 0x00000000 0x00010000 { ; load address = execution address
*.o (RESET, +First)
*(InRoot$$Sections)
.ANY (+RO)
}
RW_IRAM1 0x10000000 0x00002000 { ; RW data
.ANY (+RW +ZI)
}
RW_IRAM2 0x20004000 0x00000800 {
*(USBRAM_SECTION)
}
}

279
hw/mcu/nxp/lpc13uxx/keil/startup_LPC13Uxx.s
View File

@ -1,279 +0,0 @@
;/**************************************************************************//**
; * @file startup_LPC13Uxx.s
; * @brief CMSIS Cortex-M3 Core Device Startup File
; * for the NXP LPC13Uxx Device Series
; * @version V1.10
; * @date 24. November 2010
; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
; *
; * @note
; * Copyright (C) 2009-2010 ARM Limited. All rights reserved.
; *
; * @par
; * ARM Limited (ARM) is supplying this software for use with Cortex-M
; * processor based microcontrollers. This file can be freely distributed
; * within development tools that are supporting such ARM based processors.
; *
; * @par
; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
; *
; ******************************************************************************/
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000200
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000000
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD PIN_INT0_IRQHandler ; All GPIO pin can be routed to PIN_INTx
DCD PIN_INT1_IRQHandler
DCD PIN_INT2_IRQHandler
DCD PIN_INT3_IRQHandler
DCD PIN_INT4_IRQHandler
DCD PIN_INT5_IRQHandler
DCD PIN_INT6_IRQHandler
DCD PIN_INT7_IRQHandler
DCD GINT0_IRQHandler
DCD GINT1_IRQHandler ; PIO0 (0:7)
DCD Reserved_IRQHandler ; Reserved
DCD Reserved_IRQHandler
DCD OSTIMER_IRQHandler
DCD Reserved_IRQHandler
DCD SSP1_IRQHandler ; SSP1
DCD I2C_IRQHandler ; I2C
DCD CT16B0_IRQHandler ; 16-bit Timer0
DCD CT16B1_IRQHandler ; 16-bit Timer1
DCD CT32B0_IRQHandler ; 32-bit Timer0
DCD CT32B1_IRQHandler ; 32-bit Timer1
DCD SSP0_IRQHandler ; SSP0
DCD USART_IRQHandler ; USART
DCD USB_IRQHandler ; USB IRQ
DCD USB_FIQHandler ; USB FIQ
DCD ADC_IRQHandler ; A/D Converter
DCD WDT_IRQHandler ; Watchdog timer
DCD BOD_IRQHandler ; Brown Out Detect
DCD FMC_IRQHandler ; IP2111 Flash Memory Controller
DCD OSCFAIL_IRQHandler ; OSC FAIL
DCD PVTCIRCUIT_IRQHandler ; PVT CIRCUIT
DCD USBWakeup_IRQHandler ; USB wake up
DCD Reserved_IRQHandler ; Reserved
IF :LNOT::DEF:NO_CRP
AREA |.ARM.__at_0x02FC|, CODE, READONLY
CRP_Key DCD 0xFFFFFFFF
ENDIF
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
; now, under COMMON NMI.c and NMI.h, a real NMI handler is created if NMI is enabled
; for particular peripheral.
;NMI_Handler PROC
; EXPORT NMI_Handler [WEAK]
; B .
; ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Reserved_IRQHandler PROC
EXPORT Reserved_IRQHandler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT NMI_Handler [WEAK]
EXPORT PIN_INT0_IRQHandler [WEAK]
EXPORT PIN_INT1_IRQHandler [WEAK]
EXPORT PIN_INT2_IRQHandler [WEAK]
EXPORT PIN_INT3_IRQHandler [WEAK]
EXPORT PIN_INT4_IRQHandler [WEAK]
EXPORT PIN_INT5_IRQHandler [WEAK]
EXPORT PIN_INT6_IRQHandler [WEAK]
EXPORT PIN_INT7_IRQHandler [WEAK]
EXPORT GINT0_IRQHandler [WEAK]
EXPORT GINT1_IRQHandler [WEAK]
EXPORT OSTIMER_IRQHandler [WEAK]
EXPORT SSP1_IRQHandler [WEAK]
EXPORT I2C_IRQHandler [WEAK]
EXPORT CT16B0_IRQHandler [WEAK]
EXPORT CT16B1_IRQHandler [WEAK]
EXPORT CT32B0_IRQHandler [WEAK]
EXPORT CT32B1_IRQHandler [WEAK]
EXPORT SSP0_IRQHandler [WEAK]
EXPORT USART_IRQHandler [WEAK]
EXPORT USB_IRQHandler [WEAK]
EXPORT USB_FIQHandler [WEAK]
EXPORT ADC_IRQHandler [WEAK]
EXPORT WDT_IRQHandler [WEAK]
EXPORT BOD_IRQHandler [WEAK]
EXPORT FMC_IRQHandler [WEAK]
EXPORT OSCFAIL_IRQHandler [WEAK]
EXPORT PVTCIRCUIT_IRQHandler [WEAK]
EXPORT USBWakeup_IRQHandler [WEAK]
NMI_Handler
PIN_INT0_IRQHandler
PIN_INT1_IRQHandler
PIN_INT2_IRQHandler
PIN_INT3_IRQHandler
PIN_INT4_IRQHandler
PIN_INT5_IRQHandler
PIN_INT6_IRQHandler
PIN_INT7_IRQHandler
GINT0_IRQHandler
GINT1_IRQHandler
OSTIMER_IRQHandler
SSP1_IRQHandler
I2C_IRQHandler
CT16B0_IRQHandler
CT16B1_IRQHandler
CT32B0_IRQHandler
CT32B1_IRQHandler
SSP0_IRQHandler
USART_IRQHandler
USB_IRQHandler
USB_FIQHandler
ADC_IRQHandler
WDT_IRQHandler
BOD_IRQHandler
FMC_IRQHandler
OSCFAIL_IRQHandler
PVTCIRCUIT_IRQHandler
USBWakeup_IRQHandler
B .
ENDP
ALIGN
; User Initial Stack & Heap
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END

287
hw/mcu/nxp/lpc175x_6x/keil/startup_LPC17xx.s
View File

@ -1,287 +0,0 @@
;/**************************************************************************//**
; * @file startup_LPC17xx.s
; * @brief CMSIS Cortex-M3 Core Device Startup File for
; * NXP LPC17xx Device Series
; * @version V1.10
; * @date 06. April 2011
; *
; * @note
; * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
; *
; * @par
; * ARM Limited (ARM) is supplying this software for use with Cortex-M
; * processor based microcontrollers. This file can be freely distributed
; * within development tools that are supporting such ARM based processors.
; *
; * @par
; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
; *
; ******************************************************************************/
; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000200
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000000
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WDT_IRQHandler ; 16: Watchdog Timer
DCD TIMER0_IRQHandler ; 17: Timer0
DCD TIMER1_IRQHandler ; 18: Timer1
DCD TIMER2_IRQHandler ; 19: Timer2
DCD TIMER3_IRQHandler ; 20: Timer3
DCD UART0_IRQHandler ; 21: UART0
DCD UART1_IRQHandler ; 22: UART1
DCD UART2_IRQHandler ; 23: UART2
DCD UART3_IRQHandler ; 24: UART3
DCD PWM1_IRQHandler ; 25: PWM1
DCD I2C0_IRQHandler ; 26: I2C0
DCD I2C1_IRQHandler ; 27: I2C1
DCD I2C2_IRQHandler ; 28: I2C2
DCD SPI_IRQHandler ; 29: SPI
DCD SSP0_IRQHandler ; 30: SSP0
DCD SSP1_IRQHandler ; 31: SSP1
DCD PLL0_IRQHandler ; 32: PLL0 Lock (Main PLL)
DCD RTC_IRQHandler ; 33: Real Time Clock
DCD EINT0_IRQHandler ; 34: External Interrupt 0
DCD EINT1_IRQHandler ; 35: External Interrupt 1
DCD EINT2_IRQHandler ; 36: External Interrupt 2
DCD EINT3_IRQHandler ; 37: External Interrupt 3
DCD ADC_IRQHandler ; 38: A/D Converter
DCD BOD_IRQHandler ; 39: Brown-Out Detect
DCD USB_IRQHandler ; 40: USB
DCD CAN_IRQHandler ; 41: CAN
DCD DMA_IRQHandler ; 42: General Purpose DMA
DCD I2S_IRQHandler ; 43: I2S
DCD ENET_IRQHandler ; 44: Ethernet
DCD RIT_IRQHandler ; 45: Repetitive Interrupt Timer
DCD MCPWM_IRQHandler ; 46: Motor Control PWM
DCD QEI_IRQHandler ; 47: Quadrature Encoder Interface
DCD PLL1_IRQHandler ; 48: PLL1 Lock (USB PLL)
DCD USBActivity_IRQHandler ; 49: USB Activity interrupt to wakeup
DCD CANActivity_IRQHandler ; 50: CAN Activity interrupt to wakeup
IF :LNOT::DEF:NO_CRP
AREA |.ARM.__at_0x02FC|, CODE, READONLY
CRP_Key DCD 0xFFFFFFFF
ENDIF
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WDT_IRQHandler [WEAK]
EXPORT TIMER0_IRQHandler [WEAK]
EXPORT TIMER1_IRQHandler [WEAK]
EXPORT TIMER2_IRQHandler [WEAK]
EXPORT TIMER3_IRQHandler [WEAK]
EXPORT UART0_IRQHandler [WEAK]
EXPORT UART1_IRQHandler [WEAK]
EXPORT UART2_IRQHandler [WEAK]
EXPORT UART3_IRQHandler [WEAK]
EXPORT PWM1_IRQHandler [WEAK]
EXPORT I2C0_IRQHandler [WEAK]
EXPORT I2C1_IRQHandler [WEAK]
EXPORT I2C2_IRQHandler [WEAK]
EXPORT SPI_IRQHandler [WEAK]
EXPORT SSP0_IRQHandler [WEAK]
EXPORT SSP1_IRQHandler [WEAK]
EXPORT PLL0_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT EINT0_IRQHandler [WEAK]
EXPORT EINT1_IRQHandler [WEAK]
EXPORT EINT2_IRQHandler [WEAK]
EXPORT EINT3_IRQHandler [WEAK]
EXPORT ADC_IRQHandler [WEAK]
EXPORT BOD_IRQHandler [WEAK]
EXPORT USB_IRQHandler [WEAK]
EXPORT CAN_IRQHandler [WEAK]
EXPORT DMA_IRQHandler [WEAK]
EXPORT I2S_IRQHandler [WEAK]
EXPORT ENET_IRQHandler [WEAK]
EXPORT RIT_IRQHandler [WEAK]
EXPORT MCPWM_IRQHandler [WEAK]
EXPORT QEI_IRQHandler [WEAK]
EXPORT PLL1_IRQHandler [WEAK]
EXPORT USBActivity_IRQHandler [WEAK]
EXPORT CANActivity_IRQHandler [WEAK]
WDT_IRQHandler
TIMER0_IRQHandler
TIMER1_IRQHandler
TIMER2_IRQHandler
TIMER3_IRQHandler
UART0_IRQHandler
UART1_IRQHandler
UART2_IRQHandler
UART3_IRQHandler
PWM1_IRQHandler
I2C0_IRQHandler
I2C1_IRQHandler
I2C2_IRQHandler
SPI_IRQHandler
SSP0_IRQHandler
SSP1_IRQHandler
PLL0_IRQHandler
RTC_IRQHandler
EINT0_IRQHandler
EINT1_IRQHandler
EINT2_IRQHandler
EINT3_IRQHandler
ADC_IRQHandler
BOD_IRQHandler
USB_IRQHandler
CAN_IRQHandler
DMA_IRQHandler
I2S_IRQHandler
ENET_IRQHandler
RIT_IRQHandler
MCPWM_IRQHandler
QEI_IRQHandler
PLL1_IRQHandler
USBActivity_IRQHandler
CANActivity_IRQHandler
B .
ENDP
ALIGN
; User Initial Stack & Heap
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END

11
hw/mcu/nxp/lpc43xx/Internal FLASH.ini
View File

@ -1,11 +0,0 @@
FUNC void Setup (unsigned int region) {
region &= 0xFF000000;
_WDWORD(0x40043100, region); // Set the shadow pointer
_WDWORD(0xE000ED08, 0); // Set the vector table offset to 0
SP = _RDWORD(0); // Setup Stack Pointer
PC = _RDWORD(4); // Setup Program Counter
}
LOAD %L INCREMENTAL
Setup(0x1a000000); Get ready to execute image in Internal FLASH
g,main

11
hw/mcu/nxp/lpc43xx/keil/lpc43xx_debug_init.ini
View File

@ -1,11 +0,0 @@
FUNC void Setup (unsigned int region) {
region &= 0xFF000000;
_WDWORD(0x40043100, region); // Set the shadow pointer
_WDWORD(0xE000ED08, 0); // Set the vector table offset to 0
SP = _RDWORD(region); // Setup Stack Pointer
PC = _RDWORD(region+4); // Setup Program Counter
}
LOAD %L INCREMENTAL
Setup(__scatterload); // Get ready to execute image in SRAM or whatever region it is in g,main

346
hw/mcu/nxp/lpc43xx/keil/startup_LPC43xx.s
View File

@ -1,346 +0,0 @@
;/***********************************************************************
; * $Id: startup_LPC43xx.s 6473 2011-02-16 17:40:54Z nxp27266 $
; *
; * Project: LPC43xx CMSIS Package
; *
; * Description: Cortex-M3 Core Device Startup File for the NXP LPC43xx
; * Device Series.
; *
; * Copyright(C) 2011, NXP Semiconductor
; * All rights reserved.
; *
; * modified by KEIL
; ***********************************************************************
; * Software that is described herein is for illustrative purposes only
; * which provides customers with programming information regarding the
; * products. This software is supplied "AS IS" without any warranties.
; * NXP Semiconductors assumes no responsibility or liability for the
; * use of the software, conveys no license or title under any patent,
; * copyright, or mask work right to the product. NXP Semiconductors
; * reserves the right to make changes in the software without
; * notification. NXP Semiconductors also make no representation or
; * warranty that such application will be suitable for the specified
; * use without further testing or modification.
; **********************************************************************/
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
Sign_Value EQU 0x5A5A5A5A
__Vectors DCD __initial_sp ; 0 Top of Stack
DCD Reset_Handler ; 1 Reset Handler
DCD NMI_Handler ; 2 NMI Handler
DCD HardFault_Handler ; 3 Hard Fault Handler
DCD MemManage_Handler ; 4 MPU Fault Handler
DCD BusFault_Handler ; 5 Bus Fault Handler
DCD UsageFault_Handler ; 6 Usage Fault Handler
DCD Sign_Value ; 7 Reserved
DCD 0 ; 8 Reserved
DCD 0 ; 9 Reserved
DCD 0 ; 10 Reserved
DCD SVC_Handler ; 11 SVCall Handler
DCD DebugMon_Handler ; 12 Debug Monitor Handler
DCD 0 ; 13 Reserved
DCD PendSV_Handler ; 14 PendSV Handler
DCD SysTick_Handler ; 15 SysTick Handler
; External Interrupts
DCD DAC_IRQHandler ; 16 D/A Converter
DCD M0CORE_IRQHandler ; 17 M0 Core
DCD DMA_IRQHandler ; 18 General Purpose DMA
DCD EZH_IRQHandler ; 19 EZH/EDM
DCD FLASH_EEPROM_IRQHandler ; 20 Reserved for Typhoon
DCD ETH_IRQHandler ; 21 Ethernet
DCD SDIO_IRQHandler ; 22 SD/MMC
DCD LCD_IRQHandler ; 23 LCD
DCD USB0_IRQHandler ; 24 USB0
DCD USB1_IRQHandler ; 25 USB1
DCD SCT_IRQHandler ; 26 State Configurable Timer
DCD RIT_IRQHandler ; 27 Repetitive Interrupt Timer
DCD TIMER0_IRQHandler ; 28 Timer0
DCD TIMER1_IRQHandler ; 29 Timer1
DCD TIMER2_IRQHandler ; 30 Timer2
DCD TIMER3_IRQHandler ; 31 Timer3
DCD MCPWM_IRQHandler ; 32 Motor Control PWM
DCD ADC0_IRQHandler ; 33 A/D Converter 0
DCD I2C0_IRQHandler ; 34 I2C0
DCD I2C1_IRQHandler ; 35 I2C1
DCD SPI_IRQHandler ; 36 SPI
DCD ADC1_IRQHandler ; 37 A/D Converter 1
DCD SSP0_IRQHandler ; 38 SSP0
DCD SSP1_IRQHandler ; 39 SSP1
DCD UART0_IRQHandler ; 40 UART0
DCD UART1_IRQHandler ; 41 UART1
DCD UART2_IRQHandler ; 42 UART2
DCD UART3_IRQHandler ; 43 UART3
DCD I2S0_IRQHandler ; 44 I2S0
DCD I2S1_IRQHandler ; 45 I2S1
DCD SPIFI_IRQHandler ; 46 SPI Flash Interface
DCD SGPIO_IRQHandler ; 47 SGPIO
DCD GPIO0_IRQHandler ; 48 GPIO0
DCD GPIO1_IRQHandler ; 49 GPIO1
DCD GPIO2_IRQHandler ; 50 GPIO2
DCD GPIO3_IRQHandler ; 51 GPIO3
DCD GPIO4_IRQHandler ; 52 GPIO4
DCD GPIO5_IRQHandler ; 53 GPIO5
DCD GPIO6_IRQHandler ; 54 GPIO6
DCD GPIO7_IRQHandler ; 55 GPIO7
DCD GINT0_IRQHandler ; 56 GINT0
DCD GINT1_IRQHandler ; 57 GINT1
DCD EVRT_IRQHandler ; 58 Event Router
DCD CAN1_IRQHandler ; 59 C_CAN1
DCD 0 ; 60 Reserved
DCD VADC_IRQHandler ; 61 VADC
DCD ATIMER_IRQHandler ; 62 ATIMER
DCD RTC_IRQHandler ; 63 RTC
DCD 0 ; 64 Reserved
DCD WDT_IRQHandler ; 65 WDT
DCD M0s_IRQHandler ; 66 M0s
DCD CAN0_IRQHandler ; 67 C_CAN0
DCD QEI_IRQHandler ; 68 QEI
;CRP address at offset 0x2FC relative to the BOOT Bank address
IF :LNOT::DEF:NO_CRP
SPACE (0x2FC - (. - __Vectors))
; EXPORT CRP_Key
CRP_Key DCD 0xFFFFFFFF
; 0xFFFFFFFF => CRP Disabled
; 0x12345678 => CRP Level 1
; 0x87654321 => CRP Level 2
; 0x43218765 => CRP Level 3 (ARE YOU SURE?)
; 0x4E697370 => NO ISP (ARE YOU SURE?)
ENDIF
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT DAC_IRQHandler [WEAK]
EXPORT M0CORE_IRQHandler [WEAK]
EXPORT DMA_IRQHandler [WEAK]
EXPORT EZH_IRQHandler [WEAK]
EXPORT FLASH_EEPROM_IRQHandler [WEAK]
EXPORT ETH_IRQHandler [WEAK]
EXPORT SDIO_IRQHandler [WEAK]
EXPORT LCD_IRQHandler [WEAK]
EXPORT USB0_IRQHandler [WEAK]
EXPORT USB1_IRQHandler [WEAK]
EXPORT SCT_IRQHandler [WEAK]
EXPORT RIT_IRQHandler [WEAK]
EXPORT TIMER0_IRQHandler [WEAK]
EXPORT TIMER1_IRQHandler [WEAK]
EXPORT TIMER2_IRQHandler [WEAK]
EXPORT TIMER3_IRQHandler [WEAK]
EXPORT MCPWM_IRQHandler [WEAK]
EXPORT ADC0_IRQHandler [WEAK]
EXPORT I2C0_IRQHandler [WEAK]
EXPORT I2C1_IRQHandler [WEAK]
EXPORT SPI_IRQHandler [WEAK]
EXPORT ADC1_IRQHandler [WEAK]
EXPORT SSP0_IRQHandler [WEAK]
EXPORT SSP1_IRQHandler [WEAK]
EXPORT UART0_IRQHandler [WEAK]
EXPORT UART1_IRQHandler [WEAK]
EXPORT UART2_IRQHandler [WEAK]
EXPORT UART3_IRQHandler [WEAK]
EXPORT I2S0_IRQHandler [WEAK]
EXPORT I2S1_IRQHandler [WEAK]
EXPORT SPIFI_IRQHandler [WEAK]
EXPORT SGPIO_IRQHandler [WEAK]
EXPORT GPIO0_IRQHandler [WEAK]
EXPORT GPIO1_IRQHandler [WEAK]
EXPORT GPIO2_IRQHandler [WEAK]
EXPORT GPIO3_IRQHandler [WEAK]
EXPORT GPIO4_IRQHandler [WEAK]
EXPORT GPIO5_IRQHandler [WEAK]
EXPORT GPIO6_IRQHandler [WEAK]
EXPORT GPIO7_IRQHandler [WEAK]
EXPORT GINT0_IRQHandler [WEAK]
EXPORT GINT1_IRQHandler [WEAK]
EXPORT EVRT_IRQHandler [WEAK]
EXPORT CAN1_IRQHandler [WEAK]
EXPORT VADC_IRQHandler [WEAK]
EXPORT ATIMER_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT WDT_IRQHandler [WEAK]
EXPORT M0s_IRQHandler [WEAK]
EXPORT CAN0_IRQHandler [WEAK]
EXPORT QEI_IRQHandler [WEAK]
DAC_IRQHandler
M0CORE_IRQHandler
DMA_IRQHandler
EZH_IRQHandler
FLASH_EEPROM_IRQHandler
ETH_IRQHandler
SDIO_IRQHandler
LCD_IRQHandler
USB0_IRQHandler
USB1_IRQHandler
SCT_IRQHandler
RIT_IRQHandler
TIMER0_IRQHandler
TIMER1_IRQHandler
TIMER2_IRQHandler
TIMER3_IRQHandler
MCPWM_IRQHandler
ADC0_IRQHandler
I2C0_IRQHandler
I2C1_IRQHandler
SPI_IRQHandler
ADC1_IRQHandler
SSP0_IRQHandler
SSP1_IRQHandler
UART0_IRQHandler
UART1_IRQHandler
UART2_IRQHandler
UART3_IRQHandler
I2S0_IRQHandler
I2S1_IRQHandler
SPIFI_IRQHandler
SGPIO_IRQHandler
GPIO0_IRQHandler
GPIO1_IRQHandler
GPIO2_IRQHandler
GPIO3_IRQHandler
GPIO4_IRQHandler
GPIO5_IRQHandler
GPIO6_IRQHandler
GPIO7_IRQHandler
GINT0_IRQHandler
GINT1_IRQHandler
EVRT_IRQHandler
CAN1_IRQHandler
VADC_IRQHandler
ATIMER_IRQHandler
RTC_IRQHandler
WDT_IRQHandler
M0s_IRQHandler
CAN0_IRQHandler
QEI_IRQHandler
B .
ENDP
ALIGN
; User Initial Stack & Heap
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
AREA |.text|,CODE, READONLY
getPC PROC
EXPORT getPC
MOV R0,LR
BX LR
ENDP
END