Add dcd_musb.c
This commit is contained in:
kkitayam
parent
f183d0810b
commit
50ca0dda2c
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@ -122,6 +122,8 @@ void board_init(void)
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for (int i = 0; i < 16; ++i) __NOP();
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SYSCTL->SRUSB = 0u;
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USB0->CC = USB_CC_CLKEN | (3u << USB_CC_CLKDIV_S); /* 60MHz = 240MHz / 4 */
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__DMB(); /* Wait for completion of opening of the clock gate */
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}
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//--------------------------------------------------------------------+
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@ -11,6 +11,9 @@ CFLAGS += \
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-D__MSP432E401Y__ \
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-DCFG_TUSB_MCU=OPT_MCU_MSP432E4xx
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# mcu driver cause following warnings
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CFLAGS += -Wno-error=cast-qual -Wno-error=format=
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# All source paths should be relative to the top level.
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LD_FILE = hw/mcu/ti/msp432e4/Source/msp432e401y.ld
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LDINC += $(TOP)/hw/mcu/ti/msp432e4/Include
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@ -19,7 +22,7 @@ LDFLAGS += $(addprefix -L,$(LDINC))
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MCU_DIR = hw/mcu/ti/msp432e4
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SRC_C += \
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src/portable/mentor/dcd_musb.c \
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src/portable/mentor/musb/dcd_musb.c \
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$(MCU_DIR)/Source/system_msp432e401y.c
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INC += \
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@ -37,12 +40,6 @@ ifneq ($(OS),Windows_NT)
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export LD_LIBRARY_PATH=$(dir $(shell which MSP430Flasher))
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endif
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# flash target using TI MSP430-Flasher
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# http://www.ti.com/tool/MSP430-FLASHER
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# Please add its installation dir to PATH
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flash: $(BUILD)/$(PROJECT).hex
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MSP430Flasher -w $< -z [VCC]
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# flash target using mspdebug.
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flash-mspdebug: $(BUILD)/$(PROJECT).elf
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$(MSPDEBUG) tilib "prog $<" --allow-fw-update
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# For flash-jlink target
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JLINK_DEVICE = MSP432E401Y
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JLINK_IF = SWD
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@ -0,0 +1,836 @@
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/*
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* The MIT License (MIT)
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*
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* Copyright (c) 2021 Koji KITAYAMA
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*
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* This file is part of the TinyUSB stack.
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*/
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#include "tusb_option.h"
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#if CFG_TUSB_MCU == OPT_MCU_MSP432E4xx
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#if __GNUC__ > 8 && defined(__ARM_FEATURE_UNALIGNED)
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/* GCC warns that an address may be unaligned, even though
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* the target CPU has the capability for unaligned memory access. */
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_Pragma("GCC diagnostic ignored \"-Waddress-of-packed-member\"");
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#endif
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#include "device/dcd.h"
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#include "msp.h"
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/*------------------------------------------------------------------
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* MACRO TYPEDEF CONSTANT ENUM DECLARATION
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*------------------------------------------------------------------*/
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#define REQUEST_TYPE_INVALID (0xFFu)
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typedef struct {
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uint_fast16_t beg; /* offset of including first element */
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uint_fast16_t end; /* offset of excluding the last element */
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} free_block_t;
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typedef struct TU_ATTR_PACKED {
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uint16_t TXMAXP;
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uint8_t TXCSRL;
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uint8_t TXCSRH;
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uint16_t RXMAXP;
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uint8_t RXCSRL;
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uint8_t RXCSRH;
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uint16_t RXCOUNT;
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uint16_t RESERVED[3];
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} hw_endpoint_t;
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typedef union {
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uint8_t u8;
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uint16_t u16;
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uint32_t u32;
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} hw_fifo_t;
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typedef struct TU_ATTR_PACKED
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{
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void *buf; /* the start address of a transfer data buffer */
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uint16_t length; /* the number of bytes in the buffer */
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uint16_t remaining; /* the number of bytes remaining in the buffer */
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} pipe_state_t;
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typedef struct
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{
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tusb_control_request_t setup_packet;
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uint16_t remaining_ctrl; /* The number of bytes remaining in data stage of control transfer. */
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int8_t status_out;
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pipe_state_t pipe0;
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pipe_state_t pipe[2][7];
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} dcd_data_t;
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/*------------------------------------------------------------------
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* INTERNAL OBJECT & FUNCTION DECLARATION
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*------------------------------------------------------------------*/
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static dcd_data_t _dcd;
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static inline free_block_t *find_containing_block(free_block_t *beg, free_block_t *end, uint_fast16_t addr)
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{
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free_block_t *cur = beg;
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for (; cur < end && ((addr < cur->beg) || (cur->end <= addr)); ++cur) ;
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return cur;
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}
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static inline int update_free_block_list(free_block_t *blks, unsigned num, uint_fast16_t addr, uint_fast16_t size)
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{
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free_block_t *p = find_containing_block(blks, blks + num, addr);
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TU_ASSERT(p != blks + num, -2);
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if (p->beg == addr) {
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/* Shrink block */
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p->beg = addr + size;
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if (p->beg != p->end) return 0;
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/* remove block */
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free_block_t *end = blks + num;
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while (p + 1 < end) {
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*p = *(p + 1);
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++p;
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}
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return -1;
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} else {
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/* Split into 2 blocks */
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free_block_t tmp = {
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.beg = addr + size,
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.end = p->end
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};
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p->end = addr;
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if (p->beg == p->end) {
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if (tmp.beg != tmp.end) {
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*p = tmp;
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return 0;
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}
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/* remove block */
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free_block_t *end = blks + num;
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while (p + 1 < end) {
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*p = *(p + 1);
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++p;
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}
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return -1;
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}
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if (tmp.beg == tmp.end) return 0;
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blks[num] = tmp;
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return 1;
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}
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}
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static inline unsigned free_block_size(free_block_t const *blk)
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{
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return blk->end - blk->beg;
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}
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#if 0
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static inline void print_block_list(free_block_t const *blk, unsigned num)
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{
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TU_LOG1("*************\n");
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for (unsigned i = 0; i < num; ++i) {
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TU_LOG1(" Blk%u %u %u\n", i, blk->beg, blk->end);
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++blk;
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}
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}
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#else
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#define print_block_list(a,b)
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#endif
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static unsigned find_free_memory(uint_fast16_t size_in_log2_minus3)
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{
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free_block_t free_blocks[2 * (DCD_ATTR_ENDPOINT_MAX - 1)];
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unsigned num_blocks = 1;
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/* Initialize free memory block list */
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free_blocks[0].beg = 64 / 8;
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free_blocks[0].end = (4 << 10) / 8; /* 4KiB / 8 bytes */
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for (int i = 1; i < DCD_ATTR_ENDPOINT_MAX; ++i) {
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uint_fast16_t addr;
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int num;
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USB0->EPIDX = i;
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addr = USB0->TXFIFOADD;
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if (addr) {
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unsigned sz = USB0->TXFIFOSZ;
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unsigned sft = (sz & USB_TXFIFOSZ_SIZE_M) + ((sz & USB_TXFIFOSZ_DPB) ? 1: 0);
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num = update_free_block_list(free_blocks, num_blocks, addr, 1 << sft);
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TU_ASSERT(-2 < num, 0);
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num_blocks += num;
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print_block_list(free_blocks, num_blocks);
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}
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addr = USB0->RXFIFOADD;
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if (addr) {
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unsigned sz = USB0->RXFIFOSZ;
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unsigned sft = (sz & USB_RXFIFOSZ_SIZE_M) + ((sz & USB_RXFIFOSZ_DPB) ? 1: 0);
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num = update_free_block_list(free_blocks, num_blocks, addr, 1 << sft);
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TU_ASSERT(-2 < num, 0);
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num_blocks += num;
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print_block_list(free_blocks, num_blocks);
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}
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}
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print_block_list(free_blocks, num_blocks);
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/* Find the best fit memory block */
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uint_fast16_t size_in_8byte_unit = 1 << size_in_log2_minus3;
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free_block_t const *min = NULL;
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uint_fast16_t min_sz = 0xFFFFu;
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free_block_t const *end = &free_blocks[num_blocks];
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for (free_block_t const *cur = &free_blocks[0]; cur < end; ++cur) {
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uint_fast16_t sz = free_block_size(cur);
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if (sz < size_in_8byte_unit) continue;
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if (size_in_8byte_unit == sz) return cur->beg;
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if (sz < min_sz) min = cur;
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}
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TU_ASSERT(min, 0);
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return min->beg;
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}
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static inline volatile hw_endpoint_t* edpt_regs(unsigned epnum_minus1)
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{
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volatile hw_endpoint_t *regs = (volatile hw_endpoint_t*)((uintptr_t)&USB0->TXMAXP1);
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return regs + epnum_minus1;
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}
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static void pipe_write_packet(void *buf, volatile void *fifo, unsigned len)
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{
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volatile hw_fifo_t *reg = (volatile hw_fifo_t*)fifo;
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uintptr_t addr = (uintptr_t)buf;
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while (len >= 4) {
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reg->u32 = *(uint32_t const *)addr;
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addr += 4;
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len -= 4;
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}
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if (len >= 2) {
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reg->u16 = *(uint16_t const *)addr;
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addr += 2;
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len -= 2;
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}
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if (len) {
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reg->u8 = *(uint8_t const *)addr;
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}
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}
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static void pipe_read_packet(void *buf, volatile void *fifo, unsigned len)
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{
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volatile hw_fifo_t *reg = (volatile hw_fifo_t*)fifo;
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uintptr_t addr = (uintptr_t)buf;
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while (len >= 4) {
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*(uint32_t *)addr = reg->u32;
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addr += 4;
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len -= 4;
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}
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if (len >= 2) {
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*(uint32_t *)addr = reg->u16;
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addr += 2;
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len -= 2;
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}
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if (len) {
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*(uint32_t *)addr = reg->u8;
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}
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}
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static void process_setup_packet(uint8_t rhport)
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{
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uint32_t *p = (void*)&_dcd.setup_packet;
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p[0] = USB0->FIFO0_WORD;
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p[1] = USB0->FIFO0_WORD;
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_dcd.pipe0.buf = NULL;
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_dcd.pipe0.length = 0;
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_dcd.pipe0.remaining = 0;
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dcd_event_setup_received(rhport, (const uint8_t*)(uintptr_t)&_dcd.setup_packet, true);
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const unsigned len = _dcd.setup_packet.wLength;
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_dcd.remaining_ctrl = len;
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const unsigned dir_in = tu_edpt_dir(_dcd.setup_packet.bmRequestType);
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/* Clear RX FIFO and reverse the transaction direction */
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if (len && dir_in) USB0->CSRL0 = USB_CSRL0_RXRDYC;
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}
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static bool handle_xfer_in(uint_fast8_t ep_addr)
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{
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unsigned epnum_minus1 = tu_edpt_number(ep_addr) - 1;
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pipe_state_t *pipe = &_dcd.pipe[tu_edpt_dir(ep_addr)][epnum_minus1];
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const unsigned rem = pipe->remaining;
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if (!rem) {
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pipe->buf = NULL;
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return true;
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}
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volatile hw_endpoint_t *regs = edpt_regs(epnum_minus1);
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const unsigned mps = regs->TXMAXP;
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const unsigned len = TU_MIN(mps, rem);
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void *buf = pipe->buf;
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// TU_LOG1(" %p mps %d len %d rem %d\n", buf, mps, len, rem);
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if (len) {
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pipe_write_packet(buf, &USB0->FIFO1_WORD + epnum_minus1, len);
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pipe->buf = buf + len;
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pipe->remaining = rem - len;
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}
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regs->TXCSRL = USB_TXCSRL1_TXRDY;
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// TU_LOG1(" TXCSRL%d = %x %d\n", epnum_minus1 + 1, regs->TXCSRL, rem - len);
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return false;
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}
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static bool handle_xfer_out(uint_fast8_t ep_addr)
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{
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unsigned epnum_minus1 = tu_edpt_number(ep_addr) - 1;
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pipe_state_t *pipe = &_dcd.pipe[tu_edpt_dir(ep_addr)][epnum_minus1];
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volatile hw_endpoint_t *regs = edpt_regs(epnum_minus1);
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// TU_LOG1(" RXCSRL%d = %x\n", epnum_minus1 + 1, regs->RXCSRL);
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TU_ASSERT(regs->RXCSRL & USB_RXCSRL1_RXRDY);
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const unsigned mps = regs->RXMAXP;
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const unsigned rem = pipe->remaining;
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const unsigned vld = regs->RXCOUNT;
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const unsigned len = TU_MIN(TU_MIN(rem, mps), vld);
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void *buf = pipe->buf;
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if (len) {
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pipe_read_packet(buf, &USB0->FIFO1_WORD + epnum_minus1, len);
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pipe->buf = buf + len;
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pipe->remaining = rem - len;
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}
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if ((len < mps) || (rem == len)) {
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pipe->buf = NULL;
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return NULL != buf;
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}
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regs->RXCSRL = 0; /* Clear RXRDY bit */
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return false;
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}
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static bool edpt_n_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t *buffer, uint16_t total_bytes)
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{
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(void)rhport;
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unsigned epnum_minus1 = tu_edpt_number(ep_addr) - 1;
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unsigned dir_in = tu_edpt_dir(ep_addr);
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pipe_state_t *pipe = &_dcd.pipe[dir_in][epnum_minus1];
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pipe->buf = buffer;
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pipe->length = total_bytes;
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pipe->remaining = total_bytes;
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if (dir_in) {
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handle_xfer_in(ep_addr);
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} else {
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volatile hw_endpoint_t *regs = edpt_regs(epnum_minus1);
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if (regs->RXCSRL & USB_RXCSRL1_RXRDY) regs->RXCSRL = 0;
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}
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return true;
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}
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static bool edpt0_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t *buffer, uint16_t total_bytes)
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{
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(void)rhport;
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TU_ASSERT(total_bytes <= 64); /* Current implementation supports for only up to 64 bytes. */
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const unsigned req = _dcd.setup_packet.bmRequestType;
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TU_ASSERT(req != REQUEST_TYPE_INVALID || total_bytes == 0);
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if (req == REQUEST_TYPE_INVALID || _dcd.status_out) {
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/* STATUS OUT stage.
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* MUSB controller automatically handles STATUS OUT packets without
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* software helps. We do not have to do anything. And STATUS stage
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* may have already finished and received the next setup packet
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* without calling this function, so we have no choice but to
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* invoke the callback function of status packet here. */
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// TU_LOG1(" STATUS OUT USB0->CSRL0 = %x\n", USB0->CSRL0);
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_dcd.status_out = 0;
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if (req == REQUEST_TYPE_INVALID) {
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dcd_event_xfer_complete(rhport, ep_addr, total_bytes, XFER_RESULT_SUCCESS, false);
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} else {
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/* The next setup packet has already been received, it aborts
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* invoking callback function to avoid confusing TUSB stack. */
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TU_LOG1("Drop CONTROL_STAGE_ACK\n");
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}
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return true;
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}
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const unsigned dir_in = tu_edpt_dir(ep_addr);
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if (tu_edpt_dir(req) == dir_in) { /* DATA stage */
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TU_ASSERT(total_bytes <= _dcd.remaining_ctrl);
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const unsigned rem = _dcd.remaining_ctrl;
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const unsigned len = TU_MIN(TU_MIN(rem, 64), total_bytes);
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if (dir_in) {
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pipe_write_packet(buffer, &USB0->FIFO0_WORD, len);
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_dcd.pipe0.buf = buffer + len;
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_dcd.pipe0.length = len;
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_dcd.pipe0.remaining = 0;
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_dcd.remaining_ctrl = rem - len;
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if ((len < 64) || (rem == len)) {
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_dcd.setup_packet.bmRequestType = REQUEST_TYPE_INVALID; /* Change to STATUS/SETUP stage */
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_dcd.status_out = 1;
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/* Flush TX FIFO and reverse the transaction direction. */
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USB0->CSRL0 = USB_CSRL0_TXRDY | USB_CSRL0_DATAEND;
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} else {
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USB0->CSRL0 = USB_CSRL0_TXRDY; /* Flush TX FIFO to return ACK. */
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}
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// TU_LOG1(" IN USB0->CSRL0 = %x\n", USB0->CSRL0);
|
||||
} else {
|
||||
// TU_LOG1(" OUT USB0->CSRL0 = %x\n", USB0->CSRL0);
|
||||
_dcd.pipe0.buf = buffer;
|
||||
_dcd.pipe0.length = len;
|
||||
_dcd.pipe0.remaining = len;
|
||||
USB0->CSRL0 = USB_CSRL0_RXRDYC; /* Clear RX FIFO to return ACK. */
|
||||
}
|
||||
} else if (dir_in) {
|
||||
// TU_LOG1(" STATUS IN USB0->CSRL0 = %x\n", USB0->CSRL0);
|
||||
_dcd.pipe0.buf = NULL;
|
||||
_dcd.pipe0.length = 0;
|
||||
_dcd.pipe0.remaining = 0;
|
||||
/* Clear RX FIFO and reverse the transaction direction */
|
||||
USB0->CSRL0 = USB_CSRL0_RXRDYC | USB_CSRL0_DATAEND;
|
||||
}
|
||||
return true;
|
||||
}
|
||||
|
||||
static void process_ep0(uint8_t rhport)
|
||||
{
|
||||
uint_fast8_t csrl = USB0->CSRL0;
|
||||
|
||||
// TU_LOG1(" EP0 USB0->CSRL0 = %x\n", csrl);
|
||||
|
||||
if (csrl & USB_CSRL0_STALLED) {
|
||||
/* Returned STALL packet to HOST. */
|
||||
USB0->CSRL0 = 0; /* Clear STALL */
|
||||
return;
|
||||
}
|
||||
|
||||
unsigned req = _dcd.setup_packet.bmRequestType;
|
||||
if (csrl & USB_CSRL0_SETEND) {
|
||||
TU_LOG1(" ABORT by the next packets\n");
|
||||
USB0->CSRL0 = USB_CSRL0_SETENDC;
|
||||
if (req != REQUEST_TYPE_INVALID && _dcd.pipe0.buf) {
|
||||
/* DATA stage was aborted by receiving STATUS or SETUP packet. */
|
||||
_dcd.pipe0.buf = NULL;
|
||||
_dcd.setup_packet.bmRequestType = REQUEST_TYPE_INVALID;
|
||||
dcd_event_xfer_complete(rhport,
|
||||
req & TUSB_DIR_IN_MASK,
|
||||
_dcd.pipe0.length - _dcd.pipe0.remaining,
|
||||
XFER_RESULT_SUCCESS, true);
|
||||
}
|
||||
req = REQUEST_TYPE_INVALID;
|
||||
if (!(csrl & USB_CSRL0_RXRDY)) return; /* Received SETUP packet */
|
||||
}
|
||||
|
||||
if (csrl & USB_CSRL0_RXRDY) {
|
||||
/* Received SETUP or DATA OUT packet */
|
||||
if (req == REQUEST_TYPE_INVALID) {
|
||||
/* SETUP */
|
||||
TU_ASSERT(sizeof(tusb_control_request_t) == USB0->COUNT0,);
|
||||
process_setup_packet(rhport);
|
||||
return;
|
||||
}
|
||||
if (_dcd.pipe0.buf) {
|
||||
/* DATA OUT */
|
||||
const unsigned vld = USB0->COUNT0;
|
||||
const unsigned rem = _dcd.pipe0.remaining;
|
||||
const unsigned len = TU_MIN(TU_MIN(rem, 64), vld);
|
||||
pipe_read_packet(_dcd.pipe0.buf, &USB0->FIFO0_WORD, len);
|
||||
|
||||
_dcd.pipe0.remaining = rem - len;
|
||||
_dcd.remaining_ctrl -= len;
|
||||
|
||||
_dcd.pipe0.buf = NULL;
|
||||
dcd_event_xfer_complete(rhport,
|
||||
tu_edpt_addr(0, TUSB_DIR_OUT),
|
||||
_dcd.pipe0.length - _dcd.pipe0.remaining,
|
||||
XFER_RESULT_SUCCESS, true);
|
||||
}
|
||||
return;
|
||||
}
|
||||
|
||||
/* When CSRL0 is zero, it means that completion of sending a any length packet
|
||||
* or receiving a zero length packet. */
|
||||
if (req != REQUEST_TYPE_INVALID && !tu_edpt_dir(req)) {
|
||||
/* STATUS IN */
|
||||
if (*(const uint16_t*)(uintptr_t)&_dcd.setup_packet == 0x0500) {
|
||||
/* The address must be changed on completion of the control transfer. */
|
||||
USB0->FADDR = (uint8_t)_dcd.setup_packet.wValue;
|
||||
}
|
||||
_dcd.setup_packet.bmRequestType = REQUEST_TYPE_INVALID;
|
||||
dcd_event_xfer_complete(rhport,
|
||||
tu_edpt_addr(0, TUSB_DIR_IN),
|
||||
_dcd.pipe0.length - _dcd.pipe0.remaining,
|
||||
XFER_RESULT_SUCCESS, true);
|
||||
return;
|
||||
}
|
||||
if (_dcd.pipe0.buf) {
|
||||
/* DATA IN */
|
||||
_dcd.pipe0.buf = NULL;
|
||||
dcd_event_xfer_complete(rhport,
|
||||
tu_edpt_addr(0, TUSB_DIR_IN),
|
||||
_dcd.pipe0.length - _dcd.pipe0.remaining,
|
||||
XFER_RESULT_SUCCESS, true);
|
||||
}
|
||||
}
|
||||
|
||||
static void process_edpt_n(uint8_t rhport, uint_fast8_t ep_addr)
|
||||
{
|
||||
bool completed;
|
||||
const unsigned dir_in = tu_edpt_dir(ep_addr);
|
||||
const unsigned epn_minus1 = tu_edpt_number(ep_addr) - 1;
|
||||
|
||||
volatile hw_endpoint_t *regs = edpt_regs(epn_minus1);
|
||||
if (dir_in) {
|
||||
// TU_LOG1(" TXCSRL%d = %x\n", epn_minus1 + 1, regs->TXCSRL);
|
||||
if (regs->TXCSRL & USB_TXCSRL1_STALLED) {
|
||||
regs->TXCSRL &= ~(USB_TXCSRL1_STALLED | USB_TXCSRL1_UNDRN);
|
||||
return;
|
||||
}
|
||||
completed = handle_xfer_in(ep_addr);
|
||||
} else {
|
||||
// TU_LOG1(" RXCSRL%d = %x\n", epn_minus1 + 1, regs->RXCSRL);
|
||||
if (regs->RXCSRL & USB_RXCSRL1_STALLED) {
|
||||
regs->RXCSRL &= ~(USB_RXCSRL1_STALLED | USB_RXCSRL1_OVER);
|
||||
return;
|
||||
}
|
||||
completed = handle_xfer_out(ep_addr);
|
||||
}
|
||||
|
||||
if (completed) {
|
||||
pipe_state_t *pipe = &_dcd.pipe[dir_in][tu_edpt_number(ep_addr) - 1];
|
||||
dcd_event_xfer_complete(rhport, ep_addr,
|
||||
pipe->length - pipe->remaining,
|
||||
XFER_RESULT_SUCCESS, true);
|
||||
}
|
||||
}
|
||||
|
||||
static void process_bus_reset(uint8_t rhport)
|
||||
{
|
||||
/* When bmRequestType is REQUEST_TYPE_INVALID(0xFF),
|
||||
* a control transfer state is SETUP or STATUS stage. */
|
||||
_dcd.setup_packet.bmRequestType = REQUEST_TYPE_INVALID;
|
||||
_dcd.status_out = 0;
|
||||
/* When pipe0.buf has not NULL, DATA stage works in progress. */
|
||||
_dcd.pipe0.buf = NULL;
|
||||
|
||||
/* Clear FIFO settings */
|
||||
for (unsigned i = 1; i < DCD_ATTR_ENDPOINT_MAX; ++i) {
|
||||
USB0->EPIDX = i;
|
||||
USB0->TXFIFOSZ = 0;
|
||||
USB0->TXFIFOADD = 0;
|
||||
USB0->RXFIFOSZ = 0;
|
||||
USB0->RXFIFOADD = 0;
|
||||
}
|
||||
dcd_event_bus_reset(rhport, TUSB_SPEED_FULL, true);
|
||||
}
|
||||
|
||||
/*------------------------------------------------------------------
|
||||
* Device API
|
||||
*------------------------------------------------------------------*/
|
||||
|
||||
void dcd_init(uint8_t rhport)
|
||||
{
|
||||
(void)rhport;
|
||||
USB0->IE |= USB_IE_SUSPND;
|
||||
NVIC_ClearPendingIRQ(USB0_IRQn);
|
||||
|
||||
dcd_connect(rhport);
|
||||
}
|
||||
|
||||
void dcd_int_enable(uint8_t rhport)
|
||||
{
|
||||
(void)rhport;
|
||||
NVIC_EnableIRQ(USB0_IRQn);
|
||||
}
|
||||
|
||||
void dcd_int_disable(uint8_t rhport)
|
||||
{
|
||||
(void)rhport;
|
||||
NVIC_DisableIRQ(USB0_IRQn);
|
||||
}
|
||||
|
||||
// Receive Set Address request, mcu port must also include status IN response
|
||||
void dcd_set_address(uint8_t rhport, uint8_t dev_addr)
|
||||
{
|
||||
(void)rhport;
|
||||
(void)dev_addr;
|
||||
_dcd.pipe0.buf = NULL;
|
||||
_dcd.pipe0.length = 0;
|
||||
_dcd.pipe0.remaining = 0;
|
||||
/* Clear RX FIFO to return ACK. */
|
||||
USB0->CSRL0 = USB_CSRL0_RXRDYC | USB_CSRL0_DATAEND;
|
||||
}
|
||||
|
||||
// Wake up host
|
||||
void dcd_remote_wakeup(uint8_t rhport)
|
||||
{
|
||||
(void)rhport;
|
||||
USB0->POWER |= USB_POWER_RESUME;
|
||||
|
||||
unsigned cnt = SystemCoreClock / 1000;
|
||||
while (cnt--) __NOP();
|
||||
|
||||
USB0->POWER &= ~USB_POWER_RESUME;
|
||||
}
|
||||
|
||||
// Connect by enabling internal pull-up resistor on D+/D-
|
||||
void dcd_connect(uint8_t rhport)
|
||||
{
|
||||
(void)rhport;
|
||||
USB0->POWER |= USB_POWER_SOFTCONN;
|
||||
}
|
||||
|
||||
// Disconnect by disabling internal pull-up resistor on D+/D-
|
||||
void dcd_disconnect(uint8_t rhport)
|
||||
{
|
||||
(void)rhport;
|
||||
USB0->POWER &= ~USB_POWER_SOFTCONN;
|
||||
}
|
||||
|
||||
//--------------------------------------------------------------------+
|
||||
// Endpoint API
|
||||
//--------------------------------------------------------------------+
|
||||
|
||||
// Configure endpoint's registers according to descriptor
|
||||
bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * ep_desc)
|
||||
{
|
||||
(void) rhport;
|
||||
|
||||
const unsigned ep_addr = ep_desc->bEndpointAddress;
|
||||
const unsigned epn = tu_edpt_number(ep_addr);
|
||||
const unsigned dir_in = tu_edpt_dir(ep_addr);
|
||||
const unsigned xfer = ep_desc->bmAttributes.xfer;
|
||||
const unsigned mps = tu_edpt_packet_size(ep_desc);
|
||||
|
||||
TU_ASSERT(epn < DCD_ATTR_ENDPOINT_MAX);
|
||||
|
||||
pipe_state_t *pipe = &_dcd.pipe[dir_in][epn - 1];
|
||||
pipe->buf = NULL;
|
||||
pipe->length = 0;
|
||||
pipe->remaining = 0;
|
||||
|
||||
volatile hw_endpoint_t *regs = edpt_regs(epn - 1);
|
||||
if (dir_in) {
|
||||
regs->TXMAXP = mps;
|
||||
regs->TXCSRH = (xfer == TUSB_XFER_ISOCHRONOUS) ? USB_TXCSRH1_ISO : 0;
|
||||
if (regs->TXCSRL & USB_TXCSRL1_TXRDY)
|
||||
regs->TXCSRL = USB_TXCSRL1_CLRDT | USB_TXCSRL1_FLUSH;
|
||||
else
|
||||
regs->TXCSRL = USB_TXCSRL1_CLRDT;
|
||||
} else {
|
||||
regs->RXMAXP = mps;
|
||||
regs->RXCSRH = (xfer == TUSB_XFER_ISOCHRONOUS) ? USB_RXCSRH1_ISO : 0;
|
||||
if (regs->RXCSRL & USB_RXCSRL1_RXRDY)
|
||||
regs->RXCSRL = USB_RXCSRL1_CLRDT | USB_RXCSRL1_FLUSH;
|
||||
else
|
||||
regs->RXCSRL = USB_RXCSRL1_CLRDT;
|
||||
}
|
||||
|
||||
/* Setup FIFO */
|
||||
int size_in_log2_minus3 = 28 - TU_MIN(28, __CLZ((uint32_t)mps));
|
||||
if ((8u << size_in_log2_minus3) < mps) ++size_in_log2_minus3;
|
||||
unsigned addr = find_free_memory(size_in_log2_minus3);
|
||||
TU_ASSERT(addr);
|
||||
|
||||
USB0->EPIDX = epn;
|
||||
if (dir_in) {
|
||||
USB0->TXFIFOADD = addr;
|
||||
USB0->TXFIFOSZ = size_in_log2_minus3;
|
||||
} else {
|
||||
USB0->RXFIFOADD = addr;
|
||||
USB0->RXFIFOSZ = size_in_log2_minus3;
|
||||
}
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
void dcd_edpt_close_all(uint8_t rhport)
|
||||
{
|
||||
(void) rhport;
|
||||
volatile hw_endpoint_t *regs = (volatile hw_endpoint_t *)(uintptr_t)&USB0->TXMAXP1;
|
||||
unsigned const ie = NVIC_GetEnableIRQ(USB0_IRQn);
|
||||
NVIC_DisableIRQ(USB0_IRQn);
|
||||
for (unsigned i = 1; i < DCD_ATTR_ENDPOINT_MAX; ++i) {
|
||||
regs->TXMAXP = 0;
|
||||
regs->TXCSRH = 0;
|
||||
if (regs->TXCSRL & USB_TXCSRL1_TXRDY)
|
||||
regs->TXCSRL = USB_TXCSRL1_CLRDT | USB_TXCSRL1_FLUSH;
|
||||
else
|
||||
regs->TXCSRL = USB_TXCSRL1_CLRDT;
|
||||
|
||||
regs->RXMAXP = 0;
|
||||
regs->RXCSRH = 0;
|
||||
if (regs->RXCSRL & USB_RXCSRL1_RXRDY)
|
||||
regs->RXCSRL = USB_RXCSRL1_CLRDT | USB_RXCSRL1_FLUSH;
|
||||
else
|
||||
regs->RXCSRL = USB_RXCSRL1_CLRDT;
|
||||
|
||||
USB0->EPIDX = i;
|
||||
USB0->TXFIFOSZ = 0;
|
||||
USB0->TXFIFOADD = 0;
|
||||
USB0->RXFIFOSZ = 0;
|
||||
USB0->RXFIFOADD = 0;
|
||||
}
|
||||
if (ie) NVIC_EnableIRQ(USB0_IRQn);
|
||||
}
|
||||
|
||||
void dcd_edpt_close(uint8_t rhport, uint8_t ep_addr)
|
||||
{
|
||||
(void)rhport;
|
||||
unsigned const epn = tu_edpt_number(ep_addr);
|
||||
unsigned const dir_in = tu_edpt_dir(ep_addr);
|
||||
|
||||
hw_endpoint_t volatile *regs = edpt_regs(epn - 1);
|
||||
unsigned const ie = NVIC_GetEnableIRQ(USB0_IRQn);
|
||||
NVIC_DisableIRQ(USB0_IRQn);
|
||||
if (dir_in) {
|
||||
regs->TXMAXP = 0;
|
||||
regs->TXCSRH = 0;
|
||||
if (regs->TXCSRL & USB_TXCSRL1_TXRDY)
|
||||
regs->TXCSRL = USB_TXCSRL1_CLRDT | USB_TXCSRL1_FLUSH;
|
||||
else
|
||||
regs->TXCSRL = USB_TXCSRL1_CLRDT;
|
||||
|
||||
USB0->EPIDX = epn;
|
||||
USB0->TXFIFOSZ = 0;
|
||||
USB0->TXFIFOADD = 0;
|
||||
} else {
|
||||
regs->RXMAXP = 0;
|
||||
regs->RXCSRH = 0;
|
||||
if (regs->RXCSRL & USB_RXCSRL1_RXRDY)
|
||||
regs->RXCSRL = USB_RXCSRL1_CLRDT | USB_RXCSRL1_FLUSH;
|
||||
else
|
||||
regs->RXCSRL = USB_RXCSRL1_CLRDT;
|
||||
|
||||
USB0->EPIDX = epn;
|
||||
USB0->RXFIFOSZ = 0;
|
||||
USB0->RXFIFOADD = 0;
|
||||
}
|
||||
if (ie) NVIC_EnableIRQ(USB0_IRQn);
|
||||
}
|
||||
|
||||
// Submit a transfer, When complete dcd_event_xfer_complete() is invoked to notify the stack
|
||||
bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t total_bytes)
|
||||
{
|
||||
(void)rhport;
|
||||
bool ret;
|
||||
// TU_LOG1("X %x %d\n", ep_addr, total_bytes);
|
||||
|
||||
unsigned const ie = NVIC_GetEnableIRQ(USB0_IRQn);
|
||||
NVIC_DisableIRQ(USB0_IRQn);
|
||||
if (tu_edpt_number(ep_addr))
|
||||
ret = edpt_n_xfer(rhport, ep_addr, buffer, total_bytes);
|
||||
else
|
||||
ret = edpt0_xfer(rhport, ep_addr, buffer, total_bytes);
|
||||
if (ie) NVIC_EnableIRQ(USB0_IRQn);
|
||||
return ret;
|
||||
}
|
||||
|
||||
// Submit a transfer where is managed by FIFO, When complete dcd_event_xfer_complete() is invoked to notify the stack - optional, however, must be listed in usbd.c
|
||||
bool dcd_edpt_xfer_fifo(uint8_t rhport, uint8_t ep_addr, tu_fifo_t * ff, uint16_t total_bytes)
|
||||
{
|
||||
(void) rhport;
|
||||
(void) ep_addr;
|
||||
(void) ff;
|
||||
(void) total_bytes;
|
||||
return false;
|
||||
}
|
||||
|
||||
// Stall endpoint
|
||||
void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr)
|
||||
{
|
||||
(void)rhport;
|
||||
unsigned const epn = tu_edpt_number(ep_addr);
|
||||
unsigned const ie = NVIC_GetEnableIRQ(USB0_IRQn);
|
||||
NVIC_DisableIRQ(USB0_IRQn);
|
||||
if (0 == epn) {
|
||||
if (!ep_addr) { /* Ignore EP80 */
|
||||
_dcd.setup_packet.bmRequestType = REQUEST_TYPE_INVALID;
|
||||
_dcd.pipe0.buf = NULL;
|
||||
USB0->CSRL0 = USB_CSRL0_STALL;
|
||||
}
|
||||
} else {
|
||||
volatile hw_endpoint_t *regs = edpt_regs(epn - 1);
|
||||
if (tu_edpt_dir(ep_addr)) { /* IN */
|
||||
regs->TXCSRL = USB_TXCSRL1_STALL;
|
||||
} else { /* OUT */
|
||||
TU_ASSERT(!(regs->RXCSRL & USB_RXCSRL1_RXRDY),);
|
||||
regs->RXCSRL = USB_RXCSRL1_STALL;
|
||||
}
|
||||
}
|
||||
if (ie) NVIC_EnableIRQ(USB0_IRQn);
|
||||
}
|
||||
|
||||
// clear stall, data toggle is also reset to DATA0
|
||||
void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr)
|
||||
{
|
||||
(void)rhport;
|
||||
unsigned const epn = tu_edpt_number(ep_addr);
|
||||
hw_endpoint_t volatile *regs = edpt_regs(epn - 1);
|
||||
unsigned const ie = NVIC_GetEnableIRQ(USB0_IRQn);
|
||||
NVIC_DisableIRQ(USB0_IRQn);
|
||||
if (tu_edpt_dir(ep_addr)) { /* IN */
|
||||
regs->TXCSRL = USB_TXCSRL1_CLRDT;
|
||||
} else { /* OUT */
|
||||
regs->RXCSRL = USB_RXCSRL1_CLRDT;
|
||||
}
|
||||
if (ie) NVIC_EnableIRQ(USB0_IRQn);
|
||||
}
|
||||
|
||||
/*-------------------------------------------------------------------
|
||||
* ISR
|
||||
*-------------------------------------------------------------------*/
|
||||
void dcd_int_handler(uint8_t rhport)
|
||||
{
|
||||
uint_fast8_t is, txis, rxis;
|
||||
|
||||
is = USB0->IS; /* read and clear interrupt status */
|
||||
txis = USB0->TXIS; /* read and clear interrupt status */
|
||||
rxis = USB0->RXIS; /* read and clear interrupt status */
|
||||
// TU_LOG1("D%2x T%2x R%2x\n", is, txis, rxis);
|
||||
|
||||
is &= USB0->IE; /* Clear disabled interrupts */
|
||||
if (is & USB_IS_DISCON) {
|
||||
}
|
||||
if (is & USB_IS_SOF) {
|
||||
dcd_event_bus_signal(rhport, DCD_EVENT_SOF, true);
|
||||
}
|
||||
if (is & USB_IS_RESET) {
|
||||
process_bus_reset(rhport);
|
||||
}
|
||||
if (is & USB_IS_RESUME) {
|
||||
dcd_event_bus_signal(rhport, DCD_EVENT_RESUME, true);
|
||||
}
|
||||
if (is & USB_IS_SUSPEND) {
|
||||
dcd_event_bus_signal(rhport, DCD_EVENT_SUSPEND, true);
|
||||
}
|
||||
|
||||
txis &= USB0->TXIE; /* Clear disabled interrupts */
|
||||
if (txis & USB_TXIE_EP0) {
|
||||
process_ep0(rhport);
|
||||
txis &= ~TU_BIT(0);
|
||||
}
|
||||
while (txis) {
|
||||
unsigned const num = __builtin_ctz(txis);
|
||||
process_edpt_n(rhport, tu_edpt_addr(num, TUSB_DIR_IN));
|
||||
txis &= ~TU_BIT(num);
|
||||
}
|
||||
rxis &= USB0->RXIE; /* Clear disabled interrupts */
|
||||
while (rxis) {
|
||||
unsigned const num = __builtin_ctz(rxis);
|
||||
process_edpt_n(rhport, tu_edpt_addr(num, TUSB_DIR_OUT));
|
||||
rxis &= ~TU_BIT(num);
|
||||
}
|
||||
}
|
||||
|
||||
#endif
|
||||
Loading…
Reference in New Issue