add renesas ek-ra4m3 board port
Signed-off-by: Rafael Silva <rafaelsilva@ajtec.pt>
This commit is contained in:
Rafael Silva
parent
0bf0e0b35f
commit
4c89776a27
|
|
@ -48,6 +48,7 @@ jobs:
|
|||
- 'mm32'
|
||||
- 'msp432e4'
|
||||
- 'nrf'
|
||||
- 'ra'
|
||||
- 'rp2040'
|
||||
- 'samd11'
|
||||
- 'samd21'
|
||||
|
|
|
|||
|
|
@ -127,13 +127,16 @@
|
|||
|
||||
#elif CFG_TUSB_MCU == OPT_MCU_RP2040
|
||||
#include "pico.h"
|
||||
|
||||
|
||||
#elif CFG_TUSB_MCU == OPT_MCU_EFM32GG
|
||||
#include "em_device.h"
|
||||
|
||||
#elif CFG_TUSB_MCU == OPT_MCU_RX63X || CFG_TUSB_MCU == OPT_MCU_RX65X
|
||||
// no header needed
|
||||
|
||||
#elif CFG_TUSB_MCU == OPT_MCU_RAXXX
|
||||
#include "bsp_api.h"
|
||||
|
||||
#elif CFG_TUSB_MCU == OPT_MCU_GD32VF103
|
||||
#include "gd32vf103.h"
|
||||
|
||||
|
|
|
|||
|
|
@ -0,0 +1,15 @@
|
|||
CFLAGS += \
|
||||
-mcpu=cortex-m33 \
|
||||
-mfloat-abi=hard \
|
||||
-mfpu=fpv5-sp-d16 \
|
||||
-DCFG_TUSB_MCU=OPT_MCU_RAXXX
|
||||
|
||||
FSP_MCU_DIR = hw/mcu/renesas/fsp/ra/fsp/src/bsp/mcu/ra4m3
|
||||
FSP_BOARD_DIR = hw/mcu/renesas/fsp/ra/board/ra4m3_ek
|
||||
|
||||
# All source paths should be relative to the top level.
|
||||
LD_FILE = $(BOARD_PATH)/ek_ra4m3.ld
|
||||
|
||||
# For flash-jlink target
|
||||
JLINK_DEVICE = R7FA4M3AF
|
||||
JLINK_IF = SWD
|
||||
|
|
@ -0,0 +1,210 @@
|
|||
/*
|
||||
* The MIT License (MIT)
|
||||
*
|
||||
* Copyright (c) 2022, Rafael Silva
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
* of this software and associated documentation files (the "Software"), to deal
|
||||
* in the Software without restriction, including without limitation the rights
|
||||
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
* copies of the Software, and to permit persons to whom the Software is
|
||||
* furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
||||
* THE SOFTWARE.
|
||||
*
|
||||
* This file is part of the TinyUSB stack.
|
||||
*/
|
||||
|
||||
#include <stdio.h>
|
||||
|
||||
#include "bsp/board.h"
|
||||
#include "bsp_api.h"
|
||||
#include "r_ioport.h"
|
||||
#include "r_ioport_api.h"
|
||||
#include "renesas.h"
|
||||
|
||||
/* Key code for writing PRCR register. */
|
||||
#define BSP_PRV_PRCR_KEY (0xA500U)
|
||||
#define BSP_PRV_PRCR_PRC1_UNLOCK ((BSP_PRV_PRCR_KEY) | 0x2U)
|
||||
#define BSP_PRV_PRCR_LOCK ((BSP_PRV_PRCR_KEY) | 0x0U)
|
||||
|
||||
#define SW1 (BSP_IO_PORT_00_PIN_05)
|
||||
#define SW2 (BSP_IO_PORT_00_PIN_06)
|
||||
#define LED1 (BSP_IO_PORT_04_PIN_15)
|
||||
#define LED3 (BSP_IO_PORT_04_PIN_00)
|
||||
#define LED2 (BSP_IO_PORT_04_PIN_04)
|
||||
|
||||
/* ISR prototypes */
|
||||
void usbfs_interrupt_handler(void);
|
||||
void usbfs_resume_handler(void);
|
||||
void usbfs_d0fifo_handler(void);
|
||||
void usbfs_d1fifo_handler(void);
|
||||
|
||||
BSP_DONT_REMOVE const
|
||||
fsp_vector_t g_vector_table[BSP_ICU_VECTOR_MAX_ENTRIES] BSP_PLACE_IN_SECTION(BSP_SECTION_APPLICATION_VECTORS) = {
|
||||
[0] = usbfs_interrupt_handler, /* USBFS INT (USBFS interrupt) */
|
||||
[1] = usbfs_resume_handler, /* USBFS RESUME (USBFS resume interrupt) */
|
||||
[2] = usbfs_d0fifo_handler, /* USBFS FIFO 0 (DMA transfer request 0) */
|
||||
[3] = usbfs_d1fifo_handler, /* USBFS FIFO 1 (DMA transfer request 1) */
|
||||
};
|
||||
const bsp_interrupt_event_t g_interrupt_event_link_select[BSP_ICU_VECTOR_MAX_ENTRIES] = {
|
||||
[0] = BSP_PRV_IELS_ENUM(EVENT_USBFS_INT), /* USBFS INT (USBFS interrupt) */
|
||||
[1] = BSP_PRV_IELS_ENUM(EVENT_USBFS_RESUME), /* USBFS RESUME (USBFS resume interrupt) */
|
||||
[2] = BSP_PRV_IELS_ENUM(EVENT_USBFS_FIFO_0), /* USBFS FIFO 0 (DMA transfer request 0) */
|
||||
[3] = BSP_PRV_IELS_ENUM(EVENT_USBFS_FIFO_1) /* USBFS FIFO 1 (DMA transfer request 1) */
|
||||
};
|
||||
|
||||
const ioport_pin_cfg_t g_bsp_pin_cfg_data[] = {
|
||||
{.pin = BSP_IO_PORT_04_PIN_07,
|
||||
.pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_USB_FS)},
|
||||
{.pin = BSP_IO_PORT_05_PIN_00,
|
||||
.pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_USB_FS)},
|
||||
{.pin = BSP_IO_PORT_05_PIN_01,
|
||||
.pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_USB_FS)},
|
||||
{.pin = LED1, .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW)},
|
||||
{.pin = LED2, .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW)},
|
||||
{.pin = LED3, .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW)},
|
||||
{.pin = SW1, .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_INPUT)},
|
||||
{.pin = SW2, .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_INPUT)}};
|
||||
|
||||
const ioport_cfg_t g_bsp_pin_cfg = {
|
||||
.number_of_pins = sizeof(g_bsp_pin_cfg_data) / sizeof(ioport_pin_cfg_t),
|
||||
.p_pin_cfg_data = &g_bsp_pin_cfg_data[0],
|
||||
};
|
||||
ioport_instance_ctrl_t g_ioport_ctrl;
|
||||
const ioport_instance_t g_ioport = {.p_api = &g_ioport_on_ioport, .p_ctrl = &g_ioport_ctrl, .p_cfg = &g_bsp_pin_cfg};
|
||||
|
||||
//--------------------------------------------------------------------+
|
||||
// Forward USB interrupt events to TinyUSB IRQ Handler
|
||||
//--------------------------------------------------------------------+
|
||||
void usbfs_interrupt_handler(void)
|
||||
{
|
||||
IRQn_Type irq = R_FSP_CurrentIrqGet();
|
||||
R_BSP_IrqStatusClear(irq);
|
||||
|
||||
tud_int_handler(0);
|
||||
}
|
||||
void usbfs_resume_handler(void)
|
||||
{
|
||||
IRQn_Type irq = R_FSP_CurrentIrqGet();
|
||||
R_BSP_IrqStatusClear(irq);
|
||||
|
||||
tud_int_handler(0);
|
||||
}
|
||||
void usbfs_d0fifo_handler(void)
|
||||
{
|
||||
IRQn_Type irq = R_FSP_CurrentIrqGet();
|
||||
R_BSP_IrqStatusClear(irq);
|
||||
|
||||
tud_int_handler(0);
|
||||
}
|
||||
void usbfs_d1fifo_handler(void)
|
||||
{
|
||||
IRQn_Type irq = R_FSP_CurrentIrqGet();
|
||||
R_BSP_IrqStatusClear(irq);
|
||||
|
||||
tud_int_handler(0);
|
||||
}
|
||||
|
||||
void board_init(void)
|
||||
{
|
||||
/* Configure pins. */
|
||||
R_IOPORT_Open(&g_ioport_ctrl, &g_bsp_pin_cfg);
|
||||
|
||||
/* Enable USB_BASE */
|
||||
R_SYSTEM->PRCR = (uint16_t) BSP_PRV_PRCR_PRC1_UNLOCK;
|
||||
R_MSTP->MSTPCRB &= ~(1U << 11U);
|
||||
R_SYSTEM->PRCR = (uint16_t) BSP_PRV_PRCR_LOCK;
|
||||
|
||||
#if CFG_TUSB_OS == OPT_OS_FREERTOS
|
||||
// If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher )
|
||||
NVIC_SetPriority(TU_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
|
||||
NVIC_SetPriority(USBFS_RESUME_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
|
||||
NVIC_SetPriority(USBFS_FIFO_0_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
|
||||
NVIC_SetPriority(USBFS_FIFO_1_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
|
||||
#endif
|
||||
|
||||
#if CFG_TUSB_OS == OPT_OS_NONE
|
||||
/* Init systick */
|
||||
SysTick_Config(SystemCoreClock / 1000);
|
||||
#endif
|
||||
}
|
||||
|
||||
//--------------------------------------------------------------------+
|
||||
// Board porting API
|
||||
//--------------------------------------------------------------------+
|
||||
|
||||
void board_led_write(bool state)
|
||||
{
|
||||
R_IOPORT_PinWrite(&g_ioport_ctrl, LED1, state);
|
||||
R_IOPORT_PinWrite(&g_ioport_ctrl, LED2, state);
|
||||
R_IOPORT_PinWrite(&g_ioport_ctrl, LED3, state);
|
||||
}
|
||||
|
||||
uint32_t board_button_read(void)
|
||||
{
|
||||
bsp_io_level_t lvl;
|
||||
R_IOPORT_PinRead(&g_ioport_ctrl, SW1, &lvl);
|
||||
return lvl;
|
||||
}
|
||||
|
||||
int board_uart_read(uint8_t *buf, int len)
|
||||
{
|
||||
(void) buf;
|
||||
(void) len;
|
||||
return 0;
|
||||
}
|
||||
|
||||
int board_uart_write(void const *buf, int len)
|
||||
{
|
||||
(void) buf;
|
||||
(void) len;
|
||||
return 0;
|
||||
}
|
||||
|
||||
#if CFG_TUSB_OS == OPT_OS_NONE
|
||||
volatile uint32_t system_ticks = 0;
|
||||
void SysTick_Handler(void)
|
||||
{
|
||||
system_ticks++;
|
||||
}
|
||||
|
||||
uint32_t board_millis(void)
|
||||
{
|
||||
return system_ticks;
|
||||
}
|
||||
#else
|
||||
#endif
|
||||
|
||||
int close(int fd)
|
||||
{
|
||||
(void) fd;
|
||||
return -1;
|
||||
}
|
||||
int fstat(int fd, void *pstat)
|
||||
{
|
||||
(void) fd;
|
||||
(void) pstat;
|
||||
return 0;
|
||||
}
|
||||
off_t lseek(int fd, off_t pos, int whence)
|
||||
{
|
||||
(void) fd;
|
||||
(void) pos;
|
||||
(void) whence;
|
||||
return 0;
|
||||
}
|
||||
int isatty(int fd)
|
||||
{
|
||||
(void) fd;
|
||||
return 1;
|
||||
}
|
||||
|
|
@ -0,0 +1,575 @@
|
|||
/* generated memory regions file - do not edit */
|
||||
RAM_START = 0x20000000;
|
||||
RAM_LENGTH = 0x20000;
|
||||
FLASH_START = 0x00000000;
|
||||
FLASH_LENGTH = 0x100000;
|
||||
DATA_FLASH_START = 0x08000000;
|
||||
DATA_FLASH_LENGTH = 0x2000;
|
||||
OPTION_SETTING_START = 0x0100A100;
|
||||
OPTION_SETTING_LENGTH = 0x100;
|
||||
OPTION_SETTING_S_START = 0x0100A200;
|
||||
OPTION_SETTING_S_LENGTH = 0x100;
|
||||
ID_CODE_START = 0x00000000;
|
||||
ID_CODE_LENGTH = 0x0;
|
||||
SDRAM_START = 0x90000000;
|
||||
SDRAM_LENGTH = 0x0;
|
||||
QSPI_FLASH_START = 0x60000000;
|
||||
QSPI_FLASH_LENGTH = 0x4000000;
|
||||
OSPI_DEVICE_0_START = 0x68000000;
|
||||
OSPI_DEVICE_0_LENGTH = 0x0;
|
||||
OSPI_DEVICE_1_START = 0x70000000;
|
||||
OSPI_DEVICE_1_LENGTH = 0x0;
|
||||
|
||||
/*
|
||||
Linker File for Renesas FSP
|
||||
*/
|
||||
|
||||
QSPI_FLASH_PRV_LENGTH = DEFINED(QSPI_FLASH_SIZE) ? ABSOLUTE(QSPI_FLASH_SIZE) : ABSOLUTE(QSPI_FLASH_LENGTH);
|
||||
OSPI_DEVICE_0_PRV_LENGTH = DEFINED(OSPI_DEVICE_0_SIZE) ? ABSOLUTE(OSPI_DEVICE_0_SIZE) : ABSOLUTE(OSPI_DEVICE_0_LENGTH);
|
||||
OSPI_DEVICE_1_PRV_LENGTH = DEFINED(OSPI_DEVICE_1_SIZE) ? ABSOLUTE(OSPI_DEVICE_1_SIZE) : ABSOLUTE(OSPI_DEVICE_1_LENGTH);
|
||||
|
||||
/* This is a non-secure project if the OPTION_SETTING region is non-zero and it does not start at the base address for
|
||||
* secure option settings (meaning the secure option settings were already allocated in the secure project). */
|
||||
__TZ_NS_PROJECT = LENGTH(OPTION_SETTING) && DEFINED(OPTION_SETTING_S_START) && (ABSOLUTE(OPTION_SETTING_START_S) != ORIGIN(OPTION_SETTING));
|
||||
|
||||
/* This is a secure project if the option setting base address matches the option setting base address for secure
|
||||
* option settings. This is also set for flat projects because the CPU runs in secure mode for flat projects.
|
||||
* This is not defined for projects that do not support TrustZone. */
|
||||
__TZ_S_PROJECT = LENGTH(OPTION_SETTING) && DEFINED(OPTION_SETTING_S_START) && (ABSOLUTE(OPTION_SETTING_START_S) == ORIGIN(OPTION_SETTING));
|
||||
|
||||
/* If a flat (secure) project has defined RAM_NS_BUFFER_LENGTH, then emit IDAU symbols to allocate non-secure RAM. */
|
||||
__RESERVE_NS_RAM = __TZ_S_PROJECT && DEFINED(RAM_NS_BUFFER_LENGTH);
|
||||
|
||||
RAM_NS_BUFFER_BLOCK_LENGTH = DEFINED(RAM_NS_BUFFER_LENGTH) ? ALIGN(RAM_NS_BUFFER_LENGTH, 8192) : 0;
|
||||
RAM_NS_BUFFER_LENGTH = DEFINED(RAM_NS_BUFFER_LENGTH) ? RAM_NS_BUFFER_LENGTH : 0;
|
||||
RAM_NS_BUFFER_START = RAM_START + RAM_LENGTH - RAM_NS_BUFFER_LENGTH;
|
||||
RAM_NS_BUFFER_BLOCK_START = RAM_START + RAM_LENGTH - RAM_NS_BUFFER_BLOCK_LENGTH;
|
||||
|
||||
/* Define memory regions. */
|
||||
MEMORY
|
||||
{
|
||||
FLASH (rx) : ORIGIN = FLASH_START, LENGTH = FLASH_LENGTH
|
||||
RAM (rwx) : ORIGIN = RAM_START, LENGTH = RAM_LENGTH
|
||||
DATA_FLASH (rx) : ORIGIN = DATA_FLASH_START, LENGTH = DATA_FLASH_LENGTH
|
||||
QSPI_FLASH (rx) : ORIGIN = QSPI_FLASH_START, LENGTH = QSPI_FLASH_PRV_LENGTH
|
||||
OSPI_DEVICE_0 (rx) : ORIGIN = OSPI_DEVICE_0_START, LENGTH = OSPI_DEVICE_0_PRV_LENGTH
|
||||
OSPI_DEVICE_1 (rx) : ORIGIN = OSPI_DEVICE_1_START, LENGTH = OSPI_DEVICE_1_PRV_LENGTH
|
||||
SDRAM (rwx) : ORIGIN = SDRAM_START, LENGTH = SDRAM_LENGTH
|
||||
OPTION_SETTING (r): ORIGIN = OPTION_SETTING_START, LENGTH = OPTION_SETTING_LENGTH
|
||||
OPTION_SETTING_S (r): ORIGIN = OPTION_SETTING_S_START, LENGTH = OPTION_SETTING_S_LENGTH
|
||||
ID_CODE (rx) : ORIGIN = ID_CODE_START, LENGTH = ID_CODE_LENGTH
|
||||
}
|
||||
|
||||
OPTION_SETTING_START_NS = 0x0100A180;
|
||||
OPTION_SETTING_START_S = 0x0100A100;
|
||||
|
||||
/* Library configurations */
|
||||
GROUP(libgcc.a libc.a libm.a libnosys.a)
|
||||
|
||||
/* Linker script to place sections and symbol values. Should be used together
|
||||
* with other linker script that defines memory regions FLASH and RAM.
|
||||
* It references following symbols, which must be defined in code:
|
||||
* Reset_Handler : Entry of reset handler
|
||||
*
|
||||
* It defines following symbols, which code can use without definition:
|
||||
* __exidx_start
|
||||
* __exidx_end
|
||||
* __copy_table_start__
|
||||
* __copy_table_end__
|
||||
* __zero_table_start__
|
||||
* __zero_table_end__
|
||||
* __etext
|
||||
* __data_start__
|
||||
* __preinit_array_start
|
||||
* __preinit_array_end
|
||||
* __init_array_start
|
||||
* __init_array_end
|
||||
* __fini_array_start
|
||||
* __fini_array_end
|
||||
* __data_end__
|
||||
* __bss_start__
|
||||
* __bss_end__
|
||||
* __HeapLimit
|
||||
* __StackLimit
|
||||
* __StackTop
|
||||
* __stack
|
||||
* __Vectors_End
|
||||
* __Vectors_Size
|
||||
* __qspi_flash_start__
|
||||
* __qspi_flash_end__
|
||||
* __qspi_flash_code_size__
|
||||
* __qspi_region_max_size__
|
||||
* __qspi_region_start_address__
|
||||
* __qspi_region_end_address__
|
||||
* __ospi_device_0_start__
|
||||
* __ospi_device_0_end__
|
||||
* __ospi_device_0_code_size__
|
||||
* __ospi_device_0_region_max_size__
|
||||
* __ospi_device_0_region_start_address__
|
||||
* __ospi_device_0_region_end_address__
|
||||
* __ospi_device_1_start__
|
||||
* __ospi_device_1_end__
|
||||
* __ospi_device_1_code_size__
|
||||
* __ospi_device_1_region_max_size__
|
||||
* __ospi_device_1_region_start_address__
|
||||
* __ospi_device_1_region_end_address__
|
||||
*/
|
||||
ENTRY(Reset_Handler)
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
.text :
|
||||
{
|
||||
__tz_FLASH_S = ABSOLUTE(FLASH_START);
|
||||
__ROM_Start = .;
|
||||
|
||||
/* Even though the vector table is not 256 entries (1KB) long, we still allocate that much
|
||||
* space because ROM registers are at address 0x400 and there is very little space
|
||||
* in between. */
|
||||
KEEP(*(.fixed_vectors*))
|
||||
KEEP(*(.application_vectors*))
|
||||
__Vectors_End = .;
|
||||
|
||||
/* ROM Registers start at address 0x00000400 */
|
||||
. = __ROM_Start + 0x400;
|
||||
KEEP(*(.rom_registers*))
|
||||
|
||||
/* Reserving 0x100 bytes of space for ROM registers. */
|
||||
. = __ROM_Start + 0x500;
|
||||
|
||||
*(.text*)
|
||||
|
||||
KEEP(*(.version))
|
||||
KEEP(*(.init))
|
||||
KEEP(*(.fini))
|
||||
|
||||
/* .ctors */
|
||||
*crtbegin.o(.ctors)
|
||||
*crtbegin?.o(.ctors)
|
||||
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
|
||||
*(SORT(.ctors.*))
|
||||
*(.ctors)
|
||||
|
||||
/* .dtors */
|
||||
*crtbegin.o(.dtors)
|
||||
*crtbegin?.o(.dtors)
|
||||
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
|
||||
*(SORT(.dtors.*))
|
||||
*(.dtors)
|
||||
|
||||
*(.rodata*)
|
||||
__usb_dev_descriptor_start_fs = .;
|
||||
KEEP(*(.usb_device_desc_fs*))
|
||||
__usb_cfg_descriptor_start_fs = .;
|
||||
KEEP(*(.usb_config_desc_fs*))
|
||||
__usb_interface_descriptor_start_fs = .;
|
||||
KEEP(*(.usb_interface_desc_fs*))
|
||||
__usb_descriptor_end_fs = .;
|
||||
__usb_dev_descriptor_start_hs = .;
|
||||
KEEP(*(.usb_device_desc_hs*))
|
||||
__usb_cfg_descriptor_start_hs = .;
|
||||
KEEP(*(.usb_config_desc_hs*))
|
||||
__usb_interface_descriptor_start_hs = .;
|
||||
KEEP(*(.usb_interface_desc_hs*))
|
||||
__usb_descriptor_end_hs = .;
|
||||
|
||||
KEEP(*(.eh_frame*))
|
||||
|
||||
__ROM_End = .;
|
||||
} > FLASH = 0xFF
|
||||
|
||||
__Vectors_Size = __Vectors_End - __Vectors;
|
||||
|
||||
.ARM.extab :
|
||||
{
|
||||
*(.ARM.extab* .gnu.linkonce.armextab.*)
|
||||
} > FLASH
|
||||
|
||||
__exidx_start = .;
|
||||
.ARM.exidx :
|
||||
{
|
||||
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
|
||||
} > FLASH
|
||||
__exidx_end = .;
|
||||
|
||||
/* To copy multiple ROM to RAM sections,
|
||||
* uncomment .copy.table section and,
|
||||
* define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */
|
||||
/*
|
||||
.copy.table :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
__copy_table_start__ = .;
|
||||
LONG (__etext)
|
||||
LONG (__data_start__)
|
||||
LONG (__data_end__ - __data_start__)
|
||||
LONG (__etext2)
|
||||
LONG (__data2_start__)
|
||||
LONG (__data2_end__ - __data2_start__)
|
||||
__copy_table_end__ = .;
|
||||
} > FLASH
|
||||
*/
|
||||
|
||||
/* To clear multiple BSS sections,
|
||||
* uncomment .zero.table section and,
|
||||
* define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */
|
||||
/*
|
||||
.zero.table :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
__zero_table_start__ = .;
|
||||
LONG (__bss_start__)
|
||||
LONG (__bss_end__ - __bss_start__)
|
||||
LONG (__bss2_start__)
|
||||
LONG (__bss2_end__ - __bss2_start__)
|
||||
__zero_table_end__ = .;
|
||||
} > FLASH
|
||||
*/
|
||||
|
||||
__etext = .;
|
||||
|
||||
__tz_RAM_S = ORIGIN(RAM);
|
||||
|
||||
/* If DTC is used, put the DTC vector table at the start of SRAM.
|
||||
This avoids memory holes due to 1K alignment required by it. */
|
||||
.fsp_dtc_vector_table (NOLOAD) :
|
||||
{
|
||||
. = ORIGIN(RAM);
|
||||
*(.fsp_dtc_vector_table)
|
||||
} > RAM
|
||||
|
||||
/* Initialized data section. */
|
||||
.data :
|
||||
{
|
||||
__data_start__ = .;
|
||||
. = ALIGN(4);
|
||||
|
||||
__Code_In_RAM_Start = .;
|
||||
|
||||
KEEP(*(.code_in_ram*))
|
||||
__Code_In_RAM_End = .;
|
||||
|
||||
*(vtable)
|
||||
/* Don't use *(.data*) because it will place data meant for .data_flash in this section. */
|
||||
*(.data.*)
|
||||
*(.data)
|
||||
|
||||
. = ALIGN(4);
|
||||
/* preinit data */
|
||||
PROVIDE_HIDDEN (__preinit_array_start = .);
|
||||
KEEP(*(.preinit_array))
|
||||
PROVIDE_HIDDEN (__preinit_array_end = .);
|
||||
|
||||
. = ALIGN(4);
|
||||
/* init data */
|
||||
PROVIDE_HIDDEN (__init_array_start = .);
|
||||
KEEP(*(SORT(.init_array.*)))
|
||||
KEEP(*(.init_array))
|
||||
PROVIDE_HIDDEN (__init_array_end = .);
|
||||
|
||||
|
||||
. = ALIGN(4);
|
||||
/* finit data */
|
||||
PROVIDE_HIDDEN (__fini_array_start = .);
|
||||
KEEP(*(SORT(.fini_array.*)))
|
||||
KEEP(*(.fini_array))
|
||||
PROVIDE_HIDDEN (__fini_array_end = .);
|
||||
|
||||
KEEP(*(.jcr*))
|
||||
|
||||
. = ALIGN(4);
|
||||
|
||||
/* All data end */
|
||||
__data_end__ = .;
|
||||
|
||||
} > RAM AT > FLASH
|
||||
|
||||
|
||||
/* TrustZone Secure Gateway Stubs Section. */
|
||||
.gnu.sgstubs : ALIGN (1024)
|
||||
{
|
||||
. = DEFINED(FLASH_NSC_START) ? ABSOLUTE(FLASH_NSC_START) : ALIGN(1024);
|
||||
__tz_FLASH_C = DEFINED(FLASH_NSC_START) ? ABSOLUTE(FLASH_NSC_START) : __RESERVE_NS_RAM ? ABSOLUTE(FLASH_START + FLASH_LENGTH) : ALIGN(1024);
|
||||
_start_sg = .;
|
||||
*(.gnu.sgstubs*)
|
||||
. = ALIGN(32);
|
||||
_end_sg = .;
|
||||
} > FLASH
|
||||
|
||||
__tz_FLASH_N = DEFINED(FLASH_NS_START) ? ABSOLUTE(FLASH_NS_START) : __RESERVE_NS_RAM ? ABSOLUTE(FLASH_START + FLASH_LENGTH) : ALIGN(32768);
|
||||
|
||||
/* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */
|
||||
__tz_QSPI_FLASH_S = ORIGIN(QSPI_FLASH);
|
||||
|
||||
/* QSPI_FLASH section to be downloaded via debugger */
|
||||
.qspi_flash :
|
||||
{
|
||||
__qspi_flash_start__ = .;
|
||||
KEEP(*(.qspi_flash*))
|
||||
KEEP(*(.code_in_qspi*))
|
||||
__qspi_flash_end__ = .;
|
||||
} > QSPI_FLASH
|
||||
__qspi_flash_code_size__ = __qspi_flash_end__ - __qspi_flash_start__;
|
||||
|
||||
/* QSPI_FLASH non-retentive section, creates a copy in internal flash that can be copied to QSPI */
|
||||
__qspi_flash_code_addr__ = __etext + (__data_end__ - __data_start__);
|
||||
.qspi_non_retentive : AT (__qspi_flash_code_addr__)
|
||||
{
|
||||
__qspi_non_retentive_start__ = .;
|
||||
KEEP(*(.qspi_non_retentive*))
|
||||
__qspi_non_retentive_end__ = .;
|
||||
} > QSPI_FLASH
|
||||
__qspi_non_retentive_size__ = __qspi_non_retentive_end__ - __qspi_non_retentive_start__;
|
||||
|
||||
__qspi_region_max_size__ = 0x4000000; /* Must be the same as defined in MEMORY above */
|
||||
__qspi_region_start_address__ = __qspi_flash_start__;
|
||||
__qspi_region_end_address__ = __qspi_flash_start__ + __qspi_region_max_size__;
|
||||
|
||||
/* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */
|
||||
__tz_QSPI_FLASH_N = __qspi_non_retentive_end__;
|
||||
|
||||
/* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */
|
||||
__tz_OSPI_DEVICE_0_S = ORIGIN(OSPI_DEVICE_0);
|
||||
|
||||
/* OSPI_DEVICE_0 section to be downloaded via debugger */
|
||||
.OSPI_DEVICE_0 :
|
||||
{
|
||||
__ospi_device_0_start__ = .;
|
||||
KEEP(*(.ospi_device_0*))
|
||||
KEEP(*(.code_in_ospi_device_0*))
|
||||
__ospi_device_0_end__ = .;
|
||||
} > OSPI_DEVICE_0
|
||||
__ospi_device_0_code_size__ = __ospi_device_0_end__ - __ospi_device_0_start__;
|
||||
|
||||
/* OSPI_DEVICE_0 non-retentive section, creates a copy in internal flash that can be copied to OSPI */
|
||||
__ospi_device_0_code_addr__ = __etext + (__data_end__ - __data_start__);
|
||||
.ospi_device_0_non_retentive : AT (__ospi_device_0_code_addr__)
|
||||
{
|
||||
__ospi_device_0_non_retentive_start__ = .;
|
||||
KEEP(*(.ospi_device_0_non_retentive*))
|
||||
__ospi_device_0_non_retentive_end__ = .;
|
||||
} > OSPI_DEVICE_0
|
||||
__ospi_device_0_non_retentive_size__ = __ospi_device_0_non_retentive_end__ - __ospi_device_0_non_retentive_start__;
|
||||
|
||||
__ospi_device_0_region_max_size__ = 0x8000000; /* Must be the same as defined in MEMORY above */
|
||||
__ospi_device_0_region_start_address__ = __ospi_device_0_start__;
|
||||
__ospi_device_0_region_end_address__ = __ospi_device_0_start__ + __ospi_device_0_region_max_size__;
|
||||
|
||||
/* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */
|
||||
__tz_OSPI_DEVICE_0_N = __ospi_device_0_non_retentive_end__;
|
||||
|
||||
/* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */
|
||||
__tz_OSPI_DEVICE_1_S = ORIGIN(OSPI_DEVICE_1);
|
||||
|
||||
/* OSPI_DEVICE_1 section to be downloaded via debugger */
|
||||
.OSPI_DEVICE_1 :
|
||||
{
|
||||
__ospi_device_1_start__ = .;
|
||||
KEEP(*(.ospi_device_1*))
|
||||
KEEP(*(.code_in_ospi_device_1*))
|
||||
__ospi_device_1_end__ = .;
|
||||
} > OSPI_DEVICE_1
|
||||
__ospi_device_1_code_size__ = __ospi_device_1_end__ - __ospi_device_1_start__;
|
||||
|
||||
/* OSPI_DEVICE_1 non-retentive section, creates a copy in internal flash that can be copied to OSPI */
|
||||
__ospi_device_1_code_addr__ = __etext + (__data_end__ - __data_start__);
|
||||
.ospi_device_1_non_retentive : AT (__ospi_device_1_code_addr__)
|
||||
{
|
||||
__ospi_device_1_non_retentive_start__ = .;
|
||||
KEEP(*(.ospi_device_1_non_retentive*))
|
||||
__ospi_device_1_non_retentive_end__ = .;
|
||||
} > OSPI_DEVICE_1
|
||||
__ospi_device_1_non_retentive_size__ = __ospi_device_1_non_retentive_end__ - __ospi_device_1_non_retentive_start__;
|
||||
|
||||
__ospi_device_1_region_max_size__ = 0x10000000; /* Must be the same as defined in MEMORY above */
|
||||
__ospi_device_1_region_start_address__ = __ospi_device_1_start__;
|
||||
__ospi_device_1_region_end_address__ = __ospi_device_1_start__ + __ospi_device_1_region_max_size__;
|
||||
|
||||
/* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */
|
||||
__tz_OSPI_DEVICE_1_N = __ospi_device_1_non_retentive_end__;
|
||||
|
||||
.noinit (NOLOAD):
|
||||
{
|
||||
. = ALIGN(4);
|
||||
__noinit_start = .;
|
||||
KEEP(*(.noinit*))
|
||||
. = ALIGN(8);
|
||||
/* Place the FreeRTOS heap here so that the __HeapLimit calculation does not include the freertos heap. */
|
||||
KEEP(*(.heap.*))
|
||||
__noinit_end = .;
|
||||
} > RAM
|
||||
|
||||
.bss :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
__bss_start__ = .;
|
||||
*(.bss*)
|
||||
*(COMMON)
|
||||
. = ALIGN(4);
|
||||
__bss_end__ = .;
|
||||
} > RAM
|
||||
|
||||
.heap (NOLOAD):
|
||||
{
|
||||
. = ALIGN(8);
|
||||
__HeapBase = .;
|
||||
/* Place the STD heap here. */
|
||||
KEEP(*(.heap))
|
||||
__HeapLimit = .;
|
||||
} > RAM
|
||||
|
||||
/* Stacks are stored in this section. */
|
||||
.stack_dummy (NOLOAD):
|
||||
{
|
||||
. = ALIGN(8);
|
||||
__StackLimit = .;
|
||||
/* Main stack */
|
||||
KEEP(*(.stack))
|
||||
__StackTop = .;
|
||||
/* Thread stacks */
|
||||
KEEP(*(.stack*))
|
||||
__StackTopAll = .;
|
||||
} > RAM
|
||||
|
||||
PROVIDE(__stack = __StackTopAll);
|
||||
|
||||
/* This symbol represents the end of user allocated RAM. The RAM after this symbol can be used
|
||||
at run time for things such as ThreadX memory pool allocations. */
|
||||
__RAM_segment_used_end__ = ALIGN(__StackTopAll , 4);
|
||||
|
||||
/* RAM_NSC_START can be used to set a fixed address for non-secure callable RAM in secure projects.
|
||||
* If it is not specified, the address for NSC RAM is the end of RAM aligned to a 1K boundary.
|
||||
* In flat projects that require non-secure RAM, this variable is set to the start of non-secure RAM. */
|
||||
__tz_RAM_C = DEFINED(RAM_NSC_START) ? ABSOLUTE(RAM_NSC_START) : __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_BLOCK_START) : ALIGN(__RAM_segment_used_end__, 1024);
|
||||
|
||||
/* RAM_NS_START can be used to set a fixed address for non-secure RAM in secure projects or flat projects.
|
||||
* RAM_NS_BUFFER_BLOCK_LENGTH is used to allocate non-secure buffers in a flat project. If it is not
|
||||
* specified, the address for NSC RAM is the end of RAM aligned to an 8K boundary.
|
||||
* In flat projects that require non-secure RAM, this variable is set to the start of non-secure RAM. */
|
||||
__tz_RAM_N = DEFINED(RAM_NS_START) ? ABSOLUTE(RAM_NS_START) : __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_BLOCK_START) : ALIGN(__tz_RAM_C, 8192);
|
||||
|
||||
/* Non-secure buffers must be in non-secure RAM. This is primarily used for the EDMAC in flat projects.
|
||||
* The EDMAC is a non-secure bus master and can only access non-secure RAM. */
|
||||
.ns_buffer (NOLOAD):
|
||||
{
|
||||
/* Allocate RAM on a 32-byte boundary to help with placement of Ethernet buffers. */
|
||||
. = __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_START & 0xFFFFFFE0) : .;
|
||||
|
||||
KEEP(*(.ns_buffer*))
|
||||
} > RAM
|
||||
|
||||
/* Data flash. */
|
||||
.data_flash :
|
||||
{
|
||||
. = ORIGIN(DATA_FLASH);
|
||||
__tz_DATA_FLASH_S = .;
|
||||
__Data_Flash_Start = .;
|
||||
KEEP(*(.data_flash*))
|
||||
__Data_Flash_End = .;
|
||||
|
||||
__tz_DATA_FLASH_N = DEFINED(DATA_FLASH_NS_START) ? ABSOLUTE(DATA_FLASH_NS_START) : __RESERVE_NS_RAM ? ABSOLUTE(DATA_FLASH_START + DATA_FLASH_LENGTH) : ALIGN(1024);
|
||||
} > DATA_FLASH
|
||||
|
||||
/* Note: There are no secure/non-secure boundaries for SDRAM. These symbols are provided for the RA configuration tool. */
|
||||
__tz_SDRAM_S = ORIGIN(SDRAM);
|
||||
|
||||
/* SDRAM */
|
||||
.sdram (NOLOAD):
|
||||
{
|
||||
__SDRAM_Start = .;
|
||||
KEEP(*(.sdram*))
|
||||
KEEP(*(.frame*))
|
||||
__SDRAM_End = .;
|
||||
} > SDRAM
|
||||
|
||||
/* Note: There are no secure/non-secure boundaries for SDRAM. These symbols are provided for the RA configuration tool. */
|
||||
__tz_SDRAM_N = __SDRAM_End;
|
||||
|
||||
/* Note: There are no secure/non-secure boundaries for ID_CODE. These symbols are provided for the RA configuration tool. */
|
||||
__tz_ID_CODE_S = ORIGIN(ID_CODE);
|
||||
|
||||
.id_code :
|
||||
{
|
||||
__ID_Code_Start = .;
|
||||
KEEP(*(.id_code*))
|
||||
__ID_Code_End = .;
|
||||
} > ID_CODE
|
||||
|
||||
/* Note: There are no secure/non-secure boundaries for ID_CODE. These symbols are provided for the RA configuration tool. */
|
||||
__tz_ID_CODE_N = __ID_Code_End;
|
||||
|
||||
/* Symbol required for RA Configuration tool. */
|
||||
__tz_OPTION_SETTING_S = ORIGIN(OPTION_SETTING);
|
||||
|
||||
.option_setting :
|
||||
{
|
||||
__OPTION_SETTING_Start = .;
|
||||
KEEP(*(.option_setting_ofs0))
|
||||
. = __TZ_S_PROJECT ? __OPTION_SETTING_Start + 0x10 : __OPTION_SETTING_Start;
|
||||
KEEP(*(.option_setting_dualsel))
|
||||
. = __TZ_S_PROJECT ? __OPTION_SETTING_Start + 0x34 : __OPTION_SETTING_Start;
|
||||
KEEP(*(.option_setting_sas))
|
||||
__OPTION_SETTING_End = .;
|
||||
} > OPTION_SETTING = 0xFF
|
||||
|
||||
/* Symbol required for RA Configuration tool. */
|
||||
__tz_OPTION_SETTING_N = OPTION_SETTING_START_NS;
|
||||
|
||||
.option_setting_ns :
|
||||
{
|
||||
__OPTION_SETTING_NS_Start = .;
|
||||
KEEP(*(.option_setting_ofs1))
|
||||
. = __TZ_NS_PROJECT ? __OPTION_SETTING_NS_Start + 0x10 : __OPTION_SETTING_NS_Start;
|
||||
KEEP(*(.option_setting_banksel))
|
||||
. = __TZ_NS_PROJECT ? __OPTION_SETTING_NS_Start + 0x40 : __OPTION_SETTING_NS_Start;
|
||||
KEEP(*(.option_setting_bps0))
|
||||
. = __TZ_NS_PROJECT ? __OPTION_SETTING_NS_Start + 0x44 : __OPTION_SETTING_NS_Start;
|
||||
KEEP(*(.option_setting_bps1))
|
||||
. = __TZ_NS_PROJECT ? __OPTION_SETTING_NS_Start + 0x48 : __OPTION_SETTING_NS_Start;
|
||||
KEEP(*(.option_setting_bps2))
|
||||
. = __TZ_NS_PROJECT ? __OPTION_SETTING_NS_Start + 0x60 : __OPTION_SETTING_NS_Start;
|
||||
KEEP(*(.option_setting_pbps0))
|
||||
. = __TZ_NS_PROJECT ? __OPTION_SETTING_NS_Start + 0x64 : __OPTION_SETTING_NS_Start;
|
||||
KEEP(*(.option_setting_pbps1))
|
||||
. = __TZ_NS_PROJECT ? __OPTION_SETTING_NS_Start + 0x68 : __OPTION_SETTING_NS_Start;
|
||||
KEEP(*(.option_setting_pbps2))
|
||||
__OPTION_SETTING_NS_End = .;
|
||||
} > OPTION_SETTING = 0xFF
|
||||
|
||||
/* Symbol required for RA Configuration tool. */
|
||||
__tz_OPTION_SETTING_S_S = ORIGIN(OPTION_SETTING_S);
|
||||
|
||||
.option_setting_s :
|
||||
{
|
||||
__OPTION_SETTING_S_Start = .;
|
||||
KEEP(*(.option_setting_ofs1_sec))
|
||||
. = __TZ_S_PROJECT ? __OPTION_SETTING_S_Start + 0x10 : __OPTION_SETTING_S_Start;
|
||||
KEEP(*(.option_setting_banksel_sec))
|
||||
. = __TZ_S_PROJECT ? __OPTION_SETTING_S_Start + 0x40 : __OPTION_SETTING_S_Start;
|
||||
KEEP(*(.option_setting_bps_sec0))
|
||||
. = __TZ_S_PROJECT ? __OPTION_SETTING_S_Start + 0x44 : __OPTION_SETTING_S_Start;
|
||||
KEEP(*(.option_setting_bps_sec1))
|
||||
. = __TZ_S_PROJECT ? __OPTION_SETTING_S_Start + 0x48 : __OPTION_SETTING_S_Start;
|
||||
KEEP(*(.option_setting_bps_sec2))
|
||||
. = __TZ_S_PROJECT ? __OPTION_SETTING_S_Start + 0x60 : __OPTION_SETTING_S_Start;
|
||||
KEEP(*(.option_setting_pbps_sec0))
|
||||
. = __TZ_S_PROJECT ? __OPTION_SETTING_S_Start + 0x64 : __OPTION_SETTING_S_Start;
|
||||
KEEP(*(.option_setting_pbps_sec1))
|
||||
. = __TZ_S_PROJECT ? __OPTION_SETTING_S_Start + 0x68 : __OPTION_SETTING_S_Start;
|
||||
KEEP(*(.option_setting_pbps_sec2))
|
||||
. = __TZ_S_PROJECT ? __OPTION_SETTING_S_Start + 0x80 : __OPTION_SETTING_S_Start;
|
||||
KEEP(*(.option_setting_ofs1_sel))
|
||||
. = __TZ_S_PROJECT ? __OPTION_SETTING_S_Start + 0x90 : __OPTION_SETTING_S_Start;
|
||||
KEEP(*(.option_setting_banksel_sel))
|
||||
. = __TZ_S_PROJECT ? __OPTION_SETTING_S_Start + 0xC0 : __OPTION_SETTING_S_Start;
|
||||
KEEP(*(.option_setting_bps_sel0))
|
||||
. = __TZ_S_PROJECT ? __OPTION_SETTING_S_Start + 0xC4 : __OPTION_SETTING_S_Start;
|
||||
KEEP(*(.option_setting_bps_sel1))
|
||||
. = __TZ_S_PROJECT ? __OPTION_SETTING_S_Start + 0xC8 : __OPTION_SETTING_S_Start;
|
||||
KEEP(*(.option_setting_bps_sel2))
|
||||
__OPTION_SETTING_S_End = .;
|
||||
} > OPTION_SETTING_S = 0xFF
|
||||
|
||||
/* Symbol required for RA Configuration tool. */
|
||||
__tz_OPTION_SETTING_S_N = __OPTION_SETTING_S_End;
|
||||
}
|
||||
|
|
@ -0,0 +1,35 @@
|
|||
/* generated configuration header file - do not edit */
|
||||
#ifndef BSP_CFG_H_
|
||||
#define BSP_CFG_H_
|
||||
|
||||
#include "board.h"
|
||||
#include "bsp_clock_cfg.h"
|
||||
#include "bsp_mcu_family_cfg.h"
|
||||
|
||||
#undef RA_NOT_DEFINED
|
||||
#define BSP_CFG_RTOS (0)
|
||||
#if defined(_RA_BOOT_IMAGE)
|
||||
#define BSP_CFG_BOOT_IMAGE (1)
|
||||
#endif
|
||||
#define BSP_CFG_MCU_VCC_MV (3300)
|
||||
#define BSP_CFG_STACK_MAIN_BYTES (0x400)
|
||||
#define BSP_CFG_HEAP_BYTES (0x400)
|
||||
#define BSP_CFG_PARAM_CHECKING_ENABLE (1)
|
||||
#define BSP_CFG_ASSERT (0)
|
||||
#define BSP_CFG_ERROR_LOG (0)
|
||||
|
||||
#define BSP_CFG_PFS_PROTECT ((1))
|
||||
|
||||
#define BSP_CFG_C_RUNTIME_INIT ((1))
|
||||
#define BSP_CFG_EARLY_INIT ((0))
|
||||
|
||||
#define BSP_CFG_STARTUP_CLOCK_REG_NOT_RESET ((0))
|
||||
|
||||
#define BSP_CLOCK_CFG_MAIN_OSC_POPULATED (1)
|
||||
|
||||
#define BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE (0)
|
||||
#define BSP_CLOCK_CFG_SUBCLOCK_DRIVE (0)
|
||||
#define BSP_CLOCK_CFG_SUBCLOCK_POPULATED (1)
|
||||
#define BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS 1000
|
||||
|
||||
#endif /* BSP_CFG_H_ */
|
||||
|
|
@ -0,0 +1,27 @@
|
|||
/* generated configuration header file - do not edit */
|
||||
#ifndef BSP_CLOCK_CFG_H_
|
||||
#define BSP_CLOCK_CFG_H_
|
||||
|
||||
#define BSP_CFG_CLOCKS_SECURE (0)
|
||||
#define BSP_CFG_CLOCKS_OVERRIDE (0)
|
||||
#define BSP_CFG_XTAL_HZ (24000000) /* XTAL 24000000Hz */
|
||||
#define BSP_CFG_HOCO_FREQUENCY (2) /* HOCO 20MHz */
|
||||
#define BSP_CFG_PLL_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC) /* PLL Src: XTAL */
|
||||
#define BSP_CFG_PLL_DIV (BSP_CLOCKS_PLL_DIV_3) /* PLL Div /3 */
|
||||
#define BSP_CFG_PLL_MUL BSP_CLOCKS_PLL_MUL_24_0 /* PLL Mul x24.0 */
|
||||
#define BSP_CFG_PLL2_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC) /* PLL2 Src: XTAL */
|
||||
#define BSP_CFG_PLL2_DIV (BSP_CLOCKS_PLL_DIV_3) /* PLL2 Div /3 */
|
||||
#define BSP_CFG_PLL2_MUL BSP_CLOCKS_PLL_MUL_24_0 /* PLL2 Mul x24.0 */
|
||||
#define BSP_CFG_CLOCK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL) /* Clock Src: PLL */
|
||||
#define BSP_CFG_CLKOUT_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* CLKOUT Disabled */
|
||||
#define BSP_CFG_UCK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL2) /* UCLK Src: PLL2 */
|
||||
#define BSP_CFG_ICLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* ICLK Div /2 */
|
||||
#define BSP_CFG_PCLKA_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* PCLKA Div /2 */
|
||||
#define BSP_CFG_PCLKB_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_4) /* PCLKB Div /4 */
|
||||
#define BSP_CFG_PCLKC_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_4) /* PCLKC Div /4 */
|
||||
#define BSP_CFG_PCLKD_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* PCLKD Div /2 */
|
||||
#define BSP_CFG_FCLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_4) /* FCLK Div /4 */
|
||||
#define BSP_CFG_CLKOUT_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* CLKOUT Div /1 */
|
||||
#define BSP_CFG_UCK_DIV (BSP_CLOCKS_USB_CLOCK_DIV_4) /* UCLK Div /4 */
|
||||
|
||||
#endif /* BSP_CLOCK_CFG_H_ */
|
||||
|
|
@ -0,0 +1,260 @@
|
|||
/* generated configuration header file through renesas e2 studio */
|
||||
#ifndef BSP_MCU_FAMILY_CFG_H_
|
||||
#define BSP_MCU_FAMILY_CFG_H_
|
||||
|
||||
#include "bsp_clock_cfg.h"
|
||||
#include "bsp_mcu_info.h"
|
||||
|
||||
#define BSP_CFG_MCU_PART_SERIES (4)
|
||||
#define BSP_MCU_R7FA4M3AF3CFB
|
||||
#define BSP_ROM_SIZE_BYTES (1048576)
|
||||
#define BSP_RAM_SIZE_BYTES (131072)
|
||||
#define BSP_DATA_FLASH_SIZE_BYTES (8192)
|
||||
#define BSP_PACKAGE_LQFP
|
||||
#define BSP_PACKAGE_PINS (144)
|
||||
|
||||
#define BSP_MCU_GROUP_RA4M3 (1)
|
||||
#define BSP_LOCO_HZ (32768)
|
||||
#define BSP_MOCO_HZ (8000000)
|
||||
#define BSP_SUB_CLOCK_HZ (32768)
|
||||
#if BSP_CFG_HOCO_FREQUENCY == 0
|
||||
#define BSP_HOCO_HZ (16000000)
|
||||
#elif BSP_CFG_HOCO_FREQUENCY == 1
|
||||
#define BSP_HOCO_HZ (18000000)
|
||||
#elif BSP_CFG_HOCO_FREQUENCY == 2
|
||||
#define BSP_HOCO_HZ (20000000)
|
||||
#else
|
||||
#error "Invalid HOCO frequency chosen (BSP_CFG_HOCO_FREQUENCY) in bsp_clock_cfg.h"
|
||||
#endif
|
||||
|
||||
#define BSP_CFG_FLL_ENABLE (0)
|
||||
|
||||
#define BSP_CORTEX_VECTOR_TABLE_ENTRIES (16U)
|
||||
#define BSP_VECTOR_TABLE_MAX_ENTRIES (112U)
|
||||
#define BSP_MCU_VBATT_SUPPORT (1)
|
||||
|
||||
#if defined(_RA_TZ_SECURE)
|
||||
#define BSP_TZ_SECURE_BUILD (1)
|
||||
#define BSP_TZ_NONSECURE_BUILD (0)
|
||||
#elif defined(_RA_TZ_NONSECURE)
|
||||
#define BSP_TZ_SECURE_BUILD (0)
|
||||
#define BSP_TZ_NONSECURE_BUILD (1)
|
||||
#else
|
||||
#define BSP_TZ_SECURE_BUILD (0)
|
||||
#define BSP_TZ_NONSECURE_BUILD (0)
|
||||
#endif
|
||||
|
||||
/* TrustZone Settings */
|
||||
#define BSP_TZ_CFG_INIT_SECURE_ONLY (BSP_CFG_CLOCKS_SECURE || (!BSP_CFG_CLOCKS_OVERRIDE))
|
||||
#define BSP_TZ_CFG_SKIP_INIT (BSP_TZ_NONSECURE_BUILD && BSP_TZ_CFG_INIT_SECURE_ONLY)
|
||||
#define BSP_TZ_CFG_EXCEPTION_RESPONSE (0)
|
||||
|
||||
/* CMSIS TrustZone Settings */
|
||||
#define SCB_CSR_AIRCR_INIT (1)
|
||||
#define SCB_AIRCR_BFHFNMINS_VAL (0)
|
||||
#define SCB_AIRCR_SYSRESETREQS_VAL (1)
|
||||
#define SCB_AIRCR_PRIS_VAL (0)
|
||||
#define TZ_FPU_NS_USAGE (1)
|
||||
#define SCB_NSACR_CP10_11_VAL (3U)
|
||||
|
||||
#define FPU_FPCCR_TS_VAL (1U)
|
||||
#define FPU_FPCCR_CLRONRETS_VAL (1)
|
||||
|
||||
#define FPU_FPCCR_CLRONRET_VAL (1)
|
||||
|
||||
/* The C-Cache line size that is configured during startup. */
|
||||
#define BSP_CFG_C_CACHE_LINE_SIZE (1U)
|
||||
|
||||
/* Type 1 Peripheral Security Attribution */
|
||||
|
||||
/* Peripheral Security Attribution Register (PSAR) Settings */
|
||||
#define BSP_TZ_CFG_PSARB \
|
||||
((((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* CAN1 */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2) /* CAN0 */ | \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 8) /* IIC1 */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 9) /* IIC0 */ | \
|
||||
(((1 > 0) ? 0U : 1U) << 11) /* USBFS */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 18) /* SPI1 */ | \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 19) /* SPI0 */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 22) /* SCI9 */ | \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 23) /* SCI8 */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 24) /* SCI7 */ | \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 25) /* SCI6 */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 26) /* SCI5 */ | \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 27) /* SCI4 */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 28) /* SCI3 */ | \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 29) /* SCI2 */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 30) /* SCI1 */ | \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 31) /* SCI0 */ | 0x33f4f9) /* Unused */
|
||||
#define BSP_TZ_CFG_PSARC \
|
||||
((((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) /* CAC */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* CRC */ | \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 3) /* CTSU */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 8) /* SSIE0 */ | \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 12) /* SDHI0 */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 13) /* DOC */ | \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 31) /* SCE9 */ | 0x7fffcef4) /* Unused */
|
||||
#define BSP_TZ_CFG_PSARD \
|
||||
((((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) /* AGT3 */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* AGT2 */ | \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2) /* AGT1 */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 3) /* AGT0 */ | \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 11) /* POEG3 */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 12) /* POEG2 */ | \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 13) /* POEG1 */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 14) /* POEG0 */ | \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 15) /* ADC1 */ | (((1 > 0) ? 0U : 1U) << 16) /* ADC0 */ | \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 20) /* DAC */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 22) /* TSN */ | \
|
||||
0xffae07f0) /* Unused */
|
||||
#define BSP_TZ_CFG_PSARE \
|
||||
((((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) /* WDT */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* IWDT */ | \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2) /* RTC */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 14) /* AGT5 */ | \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 15) /* AGT4 */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 22) /* GPT9 */ | \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 23) /* GPT8 */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 24) /* GPT7 */ | \
|
||||
(((1 > 0) ? 0U : 1U) << 25) /* GPT6 */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 26) /* GPT5 */ | \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 27) /* GPT4 */ | (((1 > 0) ? 0U : 1U) << 28) /* GPT3 */ | \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 29) /* GPT2 */ | (((1 > 0) ? 0U : 1U) << 30) /* GPT1 */ | \
|
||||
(((1 > 0) ? 0U : 1U) << 31) /* GPT0 */ | 0x3f3ff8) /* Unused */
|
||||
#define BSP_TZ_CFG_MSSAR \
|
||||
((((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) /* ELC */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* DTC_DMAC */ | \
|
||||
0xfffffffc) /* Unused */
|
||||
|
||||
/* Type 2 Peripheral Security Attribution */
|
||||
|
||||
/* Security attribution for Cache registers. */
|
||||
#define BSP_TZ_CFG_CSAR (0xFFFFFFFFU)
|
||||
|
||||
/* Security attribution for RSTSRn registers. */
|
||||
#define BSP_TZ_CFG_RSTSAR (0xFFFFFFFFU)
|
||||
|
||||
/* Security attribution for registers of LVD channels. */
|
||||
#define BSP_TZ_CFG_LVDSAR \
|
||||
((((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) | /* LVD Channel 1 */ \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) | /* LVD Channel 2 */ \
|
||||
0xFFFFFFFCU)
|
||||
|
||||
/* Security attribution for LPM registers. */
|
||||
#define BSP_TZ_CFG_LPMSAR ((RA_NOT_DEFINED > 0) ? 0xFFFFFCEAU : 0xFFFFFFFFU)
|
||||
/* Deep Standby Interrupt Factor Security Attribution Register. */
|
||||
#define BSP_TZ_CFG_DPFSAR ((RA_NOT_DEFINED > 0) ? 0xF2E00000U : 0xFFFFFFFFU)
|
||||
|
||||
/* Security attribution for CGC registers. */
|
||||
#if BSP_CFG_CLOCKS_SECURE
|
||||
/* Protect all CGC registers from Non-secure write access. */
|
||||
#define BSP_TZ_CFG_CGFSAR (0xFFFCE402U)
|
||||
#else
|
||||
/* Allow Secure and Non-secure write access. */
|
||||
#define BSP_TZ_CFG_CGFSAR (0xFFFFFFFFU)
|
||||
#endif
|
||||
|
||||
/* Security attribution for Battery Backup registers. */
|
||||
#define BSP_TZ_CFG_BBFSAR (0x00FFFFFF)
|
||||
|
||||
/* Security attribution for registers for IRQ channels. */
|
||||
#define BSP_TZ_CFG_ICUSARA \
|
||||
((((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0U) /* External IRQ0 */ | \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1U) /* External IRQ1 */ | \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2U) /* External IRQ2 */ | \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 3U) /* External IRQ3 */ | \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 4U) /* External IRQ4 */ | \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 5U) /* External IRQ5 */ | \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 6U) /* External IRQ6 */ | \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 7U) /* External IRQ7 */ | \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 8U) /* External IRQ8 */ | \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 9U) /* External IRQ9 */ | (((1 > 0) ? 0U : 1U) << 10U) /* External IRQ10 */ | \
|
||||
(((1 > 0) ? 0U : 1U) << 11U) /* External IRQ11 */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 12U) /* External IRQ12 */ | \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 13U) /* External IRQ13 */ | \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 14U) /* External IRQ14 */ | \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 15U) /* External IRQ15 */ | 0xFFFF0000U)
|
||||
|
||||
/* Security attribution for NMI registers. */
|
||||
#define BSP_TZ_CFG_ICUSARB (0 | 0xFFFFFFFEU) /* Should match AIRCR.BFHFNMINS. */
|
||||
|
||||
/* Security attribution for registers for DMAC channels */
|
||||
#define BSP_TZ_CFG_ICUSARC \
|
||||
((((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0U) /* DMAC Channel 0 */ | \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1U) /* DMAC Channel 1 */ | \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2U) /* DMAC Channel 2 */ | \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 3U) /* DMAC Channel 3 */ | \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 4U) /* DMAC Channel 4 */ | \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 5U) /* DMAC Channel 5 */ | \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 6U) /* DMAC Channel 6 */ | \
|
||||
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 7U) /* DMAC Channel 7 */ | 0xFFFFFF00U)
|
||||
|
||||
/* Security attribution registers for SELSR0. */
|
||||
#define BSP_TZ_CFG_ICUSARD ((RA_NOT_DEFINED > 0) ? 0xFFFFFFFEU : 0xFFFFFFFFU)
|
||||
|
||||
/* Security attribution registers for WUPEN0. */
|
||||
#define BSP_TZ_CFG_ICUSARE ((RA_NOT_DEFINED > 0) ? 0x04F2FFFFU : 0xFFFFFFFFU)
|
||||
|
||||
/* Security attribution registers for WUPEN1. */
|
||||
#define BSP_TZ_CFG_ICUSARF ((RA_NOT_DEFINED > 0) ? 0xFFFFFFF8U : 0xFFFFFFFFU)
|
||||
|
||||
/* Set DTCSTSAR if the Secure program uses the DTC. */
|
||||
// #if RA_NOT_DEFINED == RA_NOT_DEFINED
|
||||
#define BSP_TZ_CFG_DTC_USED (0U)
|
||||
// #else
|
||||
// #define BSP_TZ_CFG_DTC_USED (1U)
|
||||
// #endif
|
||||
|
||||
/* Security attribution of FLWT and FCKMHZ registers. */
|
||||
/* If the CGC registers are only accessible in Secure mode, than there is no
|
||||
* reason for nonsecure applications to access FLWT and FCKMHZ. */
|
||||
#if BSP_CFG_CLOCKS_SECURE
|
||||
/* Protect FLWT and FCKMHZ registers from nonsecure write access. */
|
||||
#define BSP_TZ_CFG_FSAR (0xFEFEU)
|
||||
#else
|
||||
/* Allow Secure and Non-secure write access. */
|
||||
#define BSP_TZ_CFG_FSAR (0xFFFFU)
|
||||
#endif
|
||||
|
||||
/* Security attribution for SRAM registers. */
|
||||
/* If the CGC registers are only accessible in Secure mode, than there is no
|
||||
* reason for Non Secure applications to access
|
||||
* SRAM0WTEN and therefore there is no reason to access PRCR2. */
|
||||
#define BSP_TZ_CFG_SRAMSAR (1 | ((BSP_CFG_CLOCKS_SECURE == 0) ? (1U << 1U) : 0U) | 4 | 0xFFFFFFF8U)
|
||||
|
||||
/* Security attribution for Standby RAM registers. */
|
||||
#define BSP_TZ_CFG_STBRAMSAR (0 | 0xFFFFFFF0U)
|
||||
|
||||
/* Security attribution for the DMAC Bus Master MPU settings. */
|
||||
/* The DMAC Bus Master MPU settings should align with the DMAC channel settings.
|
||||
*/
|
||||
#define BSP_TZ_CFG_MMPUSARA (BSP_TZ_CFG_ICUSARC)
|
||||
|
||||
/* Security Attribution Register A for BUS Control registers. */
|
||||
#define BSP_TZ_CFG_BUSSARA (0xFFFFFFFFU)
|
||||
/* Security Attribution Register B for BUS Control registers. */
|
||||
#define BSP_TZ_CFG_BUSSARB (0xFFFFFFFFU)
|
||||
|
||||
#define OFS_SEQ1 0xA001A001 | (1 << 1) | (3 << 2)
|
||||
#define OFS_SEQ2 (15 << 4) | (3 << 8) | (3 << 10)
|
||||
#define OFS_SEQ3 (1 << 12) | (1 << 14) | (1 << 17)
|
||||
#define OFS_SEQ4 (3 << 18) | (15 << 20) | (3 << 24) | (3 << 26)
|
||||
#define OFS_SEQ5 (1 << 28) | (1 << 30)
|
||||
#define BSP_CFG_ROM_REG_OFS0 (OFS_SEQ1 | OFS_SEQ2 | OFS_SEQ3 | OFS_SEQ4 | OFS_SEQ5)
|
||||
|
||||
/* Option Function Select Register 1 Security Attribution */
|
||||
#if defined(_RA_TZ_SECURE) || defined(_RA_TZ_NONSECURE)
|
||||
#define BSP_CFG_ROM_REG_OFS1_SEL \
|
||||
(0xFFFFF8F8U | ((BSP_CFG_CLOCKS_SECURE == 0) ? 0x700U : 0U) | ((RA_NOT_DEFINED > 0) ? 0U : 0x7U))
|
||||
#else
|
||||
#define BSP_CFG_ROM_REG_OFS1_SEL (0xFFFFF8F8U)
|
||||
#endif
|
||||
|
||||
#define BSP_CFG_ROM_REG_OFS1 (0xFFFFFEF8 | (1 << 2) | (3) | (1 << 8))
|
||||
|
||||
/* Used to create IELS values for the interrupt initialization table
|
||||
* g_interrupt_event_link_select. */
|
||||
#define BSP_PRV_IELS_ENUM(vector) (ELC_##vector)
|
||||
/* Dual Mode Select Register */
|
||||
#define BSP_CFG_ROM_REG_DUALSEL (0xFFFFFFFFU)
|
||||
/* Block Protection Register 0 */
|
||||
#define BSP_CFG_ROM_REG_BPS0 (~(0U))
|
||||
/* Block Protection Register 1 */
|
||||
#define BSP_CFG_ROM_REG_BPS1 (~(0U))
|
||||
/* Block Protection Register 2 */
|
||||
#define BSP_CFG_ROM_REG_BPS2 (0xFFFFFFFFU)
|
||||
/* Permanent Block Protection Register 0 */
|
||||
#define BSP_CFG_ROM_REG_PBPS0 (~(0U))
|
||||
/* Permanent Block Protection Register 1 */
|
||||
#define BSP_CFG_ROM_REG_PBPS1 (~(0U))
|
||||
/* Permanent Block Protection Register 2 */
|
||||
#define BSP_CFG_ROM_REG_PBPS2 (0xFFFFFFFFU)
|
||||
/* Security Attribution for Block Protection Register 0 (If any blocks are
|
||||
* marked as protected in the secure application, then mark them as secure) */
|
||||
#define BSP_CFG_ROM_REG_BPS_SEL0 (BSP_CFG_ROM_REG_BPS0 & BSP_CFG_ROM_REG_PBPS0)
|
||||
/* Security Attribution for Block Protection Register 1 (If any blocks are
|
||||
* marked as protected in the secure application, then mark them as secure) */
|
||||
#define BSP_CFG_ROM_REG_BPS_SEL1 (BSP_CFG_ROM_REG_BPS1 & BSP_CFG_ROM_REG_PBPS1)
|
||||
/* Security Attribution for Block Protection Register 2 (If any blocks are
|
||||
* marked as protected in the secure application, then mark them as secure) */
|
||||
#define BSP_CFG_ROM_REG_BPS_SEL2 (0xFFFFFFFFU)
|
||||
#define BSP_CLOCK_CFG_MAIN_OSC_WAIT (9)
|
||||
|
||||
#endif /* BSP_MCU_FAMILY_CFG_H_ */
|
||||
|
|
@ -0,0 +1,7 @@
|
|||
/* generated configuration header file - do not edit */
|
||||
#ifndef R_IOPORT_CFG_H_
|
||||
#define R_IOPORT_CFG_H_
|
||||
|
||||
#define IOPORT_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE)
|
||||
|
||||
#endif /* R_IOPORT_CFG_H_ */
|
||||
|
|
@ -0,0 +1,5 @@
|
|||
/* vector numbers are configurable/dynamic, hence this, it will be used inside the port */
|
||||
#define TU_IRQn 0
|
||||
#define USBFS_RESUME_IRQn 1
|
||||
#define USBFS_FIFO_0_IRQn 2
|
||||
#define USBFS_FIFO_1_IRQn 3
|
||||
|
|
@ -0,0 +1,55 @@
|
|||
DEPS_SUBMODULES += hw/mcu/renesas/fsp lib/CMSIS_5
|
||||
|
||||
# Cross Compiler for RA
|
||||
CROSS_COMPILE = arm-none-eabi-
|
||||
|
||||
include $(TOP)/$(BOARD_PATH)/board.mk
|
||||
|
||||
CFLAGS += \
|
||||
-Wno-error=undef \
|
||||
-Wno-error=strict-prototypes \
|
||||
-Wno-error=cast-align \
|
||||
-Wno-error=cast-qual \
|
||||
-Wno-error=unused-but-set-variable \
|
||||
-Wno-error=unused-variable \
|
||||
-mthumb \
|
||||
-nostdlib \
|
||||
-nostartfiles \
|
||||
-ffunction-sections \
|
||||
-fdata-sections \
|
||||
-ffreestanding
|
||||
|
||||
SRC_C += \
|
||||
src/portable/renesas/link/dcd_link.c \
|
||||
src/portable/renesas/link/hcd_link.c \
|
||||
hw/mcu/renesas/fsp/ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/startup.c \
|
||||
hw/mcu/renesas/fsp/ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/system.c \
|
||||
hw/mcu/renesas/fsp/ra/fsp/src/bsp/mcu/all/bsp_clocks.c \
|
||||
hw/mcu/renesas/fsp/ra/fsp/src/bsp/mcu/all/bsp_common.c \
|
||||
hw/mcu/renesas/fsp/ra/fsp/src/bsp/mcu/all/bsp_delay.c \
|
||||
hw/mcu/renesas/fsp/ra/fsp/src/bsp/mcu/all/bsp_group_irq.c \
|
||||
hw/mcu/renesas/fsp/ra/fsp/src/bsp/mcu/all/bsp_guard.c \
|
||||
hw/mcu/renesas/fsp/ra/fsp/src/bsp/mcu/all/bsp_io.c \
|
||||
hw/mcu/renesas/fsp/ra/fsp/src/bsp/mcu/all/bsp_irq.c \
|
||||
hw/mcu/renesas/fsp/ra/fsp/src/bsp/mcu/all/bsp_register_protection.c \
|
||||
hw/mcu/renesas/fsp/ra/fsp/src/bsp/mcu/all/bsp_rom_registers.c \
|
||||
hw/mcu/renesas/fsp/ra/fsp/src/bsp/mcu/all/bsp_sbrk.c \
|
||||
hw/mcu/renesas/fsp/ra/fsp/src/bsp/mcu/all/bsp_security.c \
|
||||
hw/mcu/renesas/fsp/ra/fsp/src/r_ioport/r_ioport.c \
|
||||
$(FSP_BOARD_DIR)/board_init.c \
|
||||
$(FSP_BOARD_DIR)/board_leds.c
|
||||
|
||||
INC += \
|
||||
$(TOP)/lib/CMSIS_5/CMSIS/Core/Include \
|
||||
$(TOP)/hw/mcu/renesas/fsp/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include \
|
||||
$(TOP)/$(BOARD_PATH) \
|
||||
$(TOP)/$(BOARD_PATH)/fsp_cfg \
|
||||
$(TOP)/hw/mcu/renesas/fsp/ra/fsp/inc \
|
||||
$(TOP)/hw/mcu/renesas/fsp/ra/fsp/inc/api \
|
||||
$(TOP)/hw/mcu/renesas/fsp/ra/fsp/inc/instances \
|
||||
$(TOP)/$(FSP_MCU_DIR) \
|
||||
$(TOP)/$(FSP_BOARD_DIR)
|
||||
|
||||
# For freeRTOS port source
|
||||
# hack to use the port provided by renesas
|
||||
FREERTOS_PORT = hw/mcu/renesas/fsp/ra/fsp/src/rm_freertos_port
|
||||
Loading…
Reference in New Issue