dcd_stm32h7: Merge relevant changes from dcd_stm32f4. USB2 -> USB works as alias.
This commit is contained in:
William D. Jones
parent
4fe34c8f9b
commit
3efc81b285
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@ -1,7 +1,8 @@
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/*
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* The MIT License (MIT)
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*
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* Copyright (c) 2019 William D. Jones for Adafruit Industries
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* Copyright (c) 2018 Scott Shawcroft, 2019 William D. Jones for Adafruit Industries
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* Copyright (c) 2019 Ha Thach (tinyusb.org)
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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@ -34,10 +35,15 @@
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/*------------------------------------------------------------------*/
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/* MACRO TYPEDEF CONSTANT ENUM
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*------------------------------------------------------------------*/
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#define DEVICE_BASE (USB_OTG_DeviceTypeDef *) (USB2_OTG_FS_PERIPH_BASE + USB_OTG_DEVICE_BASE)
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#define OUT_EP_BASE (USB_OTG_OUTEndpointTypeDef *) (USB2_OTG_FS_PERIPH_BASE + USB_OTG_OUT_ENDPOINT_BASE)
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#define IN_EP_BASE (USB_OTG_INEndpointTypeDef *) (USB2_OTG_FS_PERIPH_BASE + USB_OTG_IN_ENDPOINT_BASE)
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#define FIFO_BASE(_x) (volatile uint32_t *) (USB2_OTG_FS_PERIPH_BASE + USB_OTG_FIFO_BASE + (_x) * USB_OTG_FIFO_SIZE)
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#define DEVICE_BASE (USB_OTG_DeviceTypeDef *) (USB_OTG_FS_PERIPH_BASE + USB_OTG_DEVICE_BASE)
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#define OUT_EP_BASE (USB_OTG_OUTEndpointTypeDef *) (USB_OTG_FS_PERIPH_BASE + USB_OTG_OUT_ENDPOINT_BASE)
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#define IN_EP_BASE (USB_OTG_INEndpointTypeDef *) (USB_OTG_FS_PERIPH_BASE + USB_OTG_IN_ENDPOINT_BASE)
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#define FIFO_BASE(_x) (volatile uint32_t *) (USB_OTG_FS_PERIPH_BASE + USB_OTG_FIFO_BASE + (_x) * USB_OTG_FIFO_SIZE)
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// TODO Merge with OTG_HS
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// Max endpoints for each direction
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#define EP_MAX 8
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#define EP_FIFO_SIZE 4096
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static TU_ATTR_ALIGNED(4) uint32_t _setup_packet[6];
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static uint8_t _setup_offs; // We store up to 3 setup packets.
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@ -52,18 +58,16 @@ typedef struct {
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typedef volatile uint32_t * usb_fifo_t;
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xfer_ctl_t xfer_status[4][2];
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xfer_ctl_t xfer_status[EP_MAX][2];
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#define XFER_CTL_BASE(_ep, _dir) &xfer_status[_ep][_dir]
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// Setup the control endpoint 0.
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static void bus_reset(void)
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{
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static void bus_reset(void) {
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USB_OTG_DeviceTypeDef * dev = DEVICE_BASE;
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USB_OTG_OUTEndpointTypeDef * out_ep = OUT_EP_BASE;
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for(int n = 0; n < 4; n++)
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{
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for(uint8_t n = 0; n < EP_MAX; n++) {
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out_ep[n].DOEPCTL |= USB_OTG_DOEPCTL_SNAK;
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}
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@ -71,45 +75,45 @@ static void bus_reset(void)
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dev->DOEPMSK |= USB_OTG_DOEPMSK_STUPM | USB_OTG_DOEPMSK_XFRCM;
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dev->DIEPMSK |= USB_OTG_DIEPMSK_TOM | USB_OTG_DIEPMSK_XFRCM;
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// Peripheral FIFO architecture (Rev6 RM 56.11.1)
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// "USB Data FIFOs" section in reference manual
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// Peripheral FIFO architecture
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//
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// --------------- 1024 ( 4096 bytes )
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// | IN FIFO 7 |
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// --------------- 320 or 1024 ( 1280 or 4096 bytes )
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// | IN FIFO MAX |
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// ---------------
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// | ... |
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// | ... |
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// --------------- y + x + 16 + GRXFSIZ
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// | IN FIFO 2 |
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// | IN FIFO 2 |
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// --------------- x + 16 + GRXFSIZ
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// | IN FIFO 1 |
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// | IN FIFO 1 |
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// --------------- 16 + GRXFSIZ
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// | IN FIFO 0 |
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// | IN FIFO 0 |
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// --------------- GRXFSIZ
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// | OUT FIFO |
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// | ( Shared ) |
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// | OUT FIFO |
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// | ( Shared ) |
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// --------------- 0
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//
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// FIFO sizes are set up by the following rules (each word 32-bits):
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// All EP OUT shared a unique OUT FIFO which uses (based on page 2747 of Rev 6 of reference manual):
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// * 10 locations in hardware for setup packets + setup control words
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// (up to 3 setup packets).
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// * 2 locations for OUT endpoint control words.
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// * 16 for largest packet size of 64 bytes. ( TODO Highspeed is 512 bytes)
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// * 1 location for global NAK (not required/used here).
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// According to "FIFO RAM allocation" section in RM, FIFO RAM are allocated as follows (each word 32-bits):
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// - Each EP IN needs at least max packet size, 16 words is sufficient for EP0 IN
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//
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// It is recommended to allocate 2 times the largest packet size, therefore
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// Recommended value = 10 + 1 + 2 x (16+2) = 47 --> Let's make it 50
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USB2_OTG_FS->GRXFSIZ = 50;
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// - All EP OUT shared a unique OUT FIFO which uses
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// * 10 locations in hardware for setup packets + setup control words (up to 3 setup packets).
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// * 2 locations for OUT endpoint control words.
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// * 16 for largest packet size of 64 bytes. ( TODO Highspeed is 512 bytes)
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// * 1 location for global NAK (not required/used here).
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// * It is recommended to allocate 2 times the largest packet size, therefore
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// Recommended value = 10 + 1 + 2 x (16+2) = 47 --> Let's make it 52
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USB_OTG_FS->GRXFSIZ = 52;
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// Control IN uses FIFO 0 with 64 bytes ( 16 32-bit word )
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USB2_OTG_FS->DIEPTXF0_HNPTXFSIZ = (16 << USB_OTG_TX0FD_Pos) | (USB2_OTG_FS->GRXFSIZ & 0x0000ffffUL);
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USB_OTG_FS->DIEPTXF0_HNPTXFSIZ = (16 << USB_OTG_TX0FD_Pos) | (USB_OTG_FS->GRXFSIZ & 0x0000ffffUL);
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out_ep[0].DOEPTSIZ |= (3 << USB_OTG_DOEPTSIZ_STUPCNT_Pos);
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USB2_OTG_FS->GINTMSK |= USB_OTG_GINTMSK_OEPINT | USB_OTG_GINTMSK_IEPINT;
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USB_OTG_FS->GINTMSK |= USB_OTG_GINTMSK_OEPINT | USB_OTG_GINTMSK_IEPINT;
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}
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static void end_of_reset(void)
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{
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static void end_of_reset(void) {
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USB_OTG_DeviceTypeDef * dev = DEVICE_BASE;
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USB_OTG_INEndpointTypeDef * in_ep = IN_EP_BASE;
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// On current silicon on the Full Speed core, speed is fixed to Full Speed.
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@ -139,22 +143,23 @@ void dcd_init (uint8_t rhport)
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{
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(void) rhport;
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// Programming model begins on page 2634 of Rev 6 of reference manual.
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USB2_OTG_FS->GAHBCFG |= USB_OTG_GAHBCFG_TXFELVL | USB_OTG_GAHBCFG_GINT;
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// Programming model begins in the last section of the chapter on the USB
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// peripheral in each Reference Manual.
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USB_OTG_FS->GAHBCFG |= USB_OTG_GAHBCFG_TXFELVL | USB_OTG_GAHBCFG_GINT;
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// No HNP/SRP (no OTG support), program timeout later, turnaround
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// programmed for 32+ MHz.
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USB2_OTG_FS->GUSBCFG |= (0x06 << USB_OTG_GUSBCFG_TRDT_Pos) | USB_OTG_GUSBCFG_PHYSEL;
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USB_OTG_FS->GUSBCFG |= (0x06 << USB_OTG_GUSBCFG_TRDT_Pos) | USB_OTG_GUSBCFG_PHYSEL;
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// Clear all used interrupts
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USB2_OTG_FS->GINTSTS |= USB_OTG_GINTSTS_OTGINT | USB_OTG_GINTSTS_MMIS | \
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USB_OTG_FS->GINTSTS |= USB_OTG_GINTSTS_OTGINT | USB_OTG_GINTSTS_MMIS | \
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USB_OTG_GINTSTS_USBRST | USB_OTG_GINTSTS_ENUMDNE | \
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USB_OTG_GINTSTS_ESUSP | USB_OTG_GINTSTS_USBSUSP | USB_OTG_GINTSTS_SOF;
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// Required as part of core initialization. Disable OTGINT as we don't use
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// it right now. TODO: How should mode mismatch be handled? It will cause
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// the core to stop working/require reset.
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USB2_OTG_FS->GINTMSK |= /* USB_OTG_GINTMSK_OTGINT | */ USB_OTG_GINTMSK_MMISM;
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USB_OTG_FS->GINTMSK |= /* USB_OTG_GINTMSK_OTGINT | */ USB_OTG_GINTMSK_MMISM;
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USB_OTG_DeviceTypeDef * dev = DEVICE_BASE;
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@ -162,17 +167,18 @@ void dcd_init (uint8_t rhport)
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// (non zero-length packet), send STALL back and discard. Full speed.
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dev->DCFG |= USB_OTG_DCFG_NZLSOHSK | (3 << USB_OTG_DCFG_DSPD_Pos);
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USB2_OTG_FS->GINTMSK |= USB_OTG_GINTMSK_USBRST | USB_OTG_GINTMSK_ENUMDNEM | \
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USB_OTG_FS->GINTMSK |= USB_OTG_GINTMSK_USBRST | USB_OTG_GINTMSK_ENUMDNEM | \
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USB_OTG_GINTMSK_SOFM | USB_OTG_GINTMSK_RXFLVLM /* SB_OTG_GINTMSK_ESUSPM | \
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USB_OTG_GINTMSK_USBSUSPM */;
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// Enable pullup, enable peripheral.
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// Enable VBUS hardware sensing, enable pullup, enable peripheral.
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#ifdef USB_OTG_GCCFG_VBDEN
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USB2_OTG_FS->GCCFG |= USB_OTG_GCCFG_VBDEN | USB_OTG_GCCFG_PWRDWN;
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USB_OTG_FS->GCCFG |= USB_OTG_GCCFG_VBDEN | USB_OTG_GCCFG_PWRDWN;
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#else
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USB2_OTG_FS->GCCFG |= USB_OTG_GCCFG_VBUSBSEN | USB_OTG_GCCFG_PWRDWN;
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USB_OTG_FS->GCCFG |= USB_OTG_GCCFG_VBUSBSEN | USB_OTG_GCCFG_PWRDWN;
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#endif
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// Soft Connect -> Enable pullup on D+/D-.
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// This step does not appear to be specified in the programmer's model.
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dev->DCTL &= ~USB_OTG_DCTL_SDIS;
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}
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@ -227,7 +233,7 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt)
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uint8_t const dir = tu_edpt_dir(desc_edpt->bEndpointAddress);
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// Unsupported endpoint numbers/size.
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if((desc_edpt->wMaxPacketSize.size > 64) || (epnum > 7)) {
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if((desc_edpt->wMaxPacketSize.size > 64) || (epnum > EP_MAX)) {
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return false;
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}
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@ -240,24 +246,27 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt)
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desc_edpt->wMaxPacketSize.size << USB_OTG_DOEPCTL_MPSIZ_Pos;
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dev->DAINTMSK |= (1 << (USB_OTG_DAINTMSK_OEPM_Pos + epnum));
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} else {
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// Peripheral FIFO architecture (Rev6 RM 56.11.1)
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// "USB Data FIFOs" section in reference manual
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// Peripheral FIFO architecture
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//
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// --------------- 1024 ( 4096 bytes )
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// | IN FIFO 7 |
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// --------------- 320 or 1024 ( 1280 or 4096 bytes )
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// | IN FIFO MAX |
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// ---------------
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// | ... |
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// | ... |
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// --------------- y + x + 16 + GRXFSIZ
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// | IN FIFO 2 |
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// | IN FIFO 2 |
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// --------------- x + 16 + GRXFSIZ
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// | IN FIFO 1 |
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// | IN FIFO 1 |
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// --------------- 16 + GRXFSIZ
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// | IN FIFO 0 |
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// | IN FIFO 0 |
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// --------------- GRXFSIZ
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// | OUT FIFO |
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// | ( Shared ) |
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// | OUT FIFO |
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// | ( Shared ) |
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// --------------- 0
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//
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// Since OUT FIFO = 50, FIFO 0 = 16, average of FIFOx = (1024-50-16) / 7 = 136 ~ 130
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// Since OUT FIFO = GRXFSIZ, FIFO 0 = 16, for simplicity, we equally allocated for the rest of endpoints
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// - Size : (FIFO_SIZE/4 - GRXFSIZ - 16) / (EP_MAX-1)
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// - Offset: GRXFSIZ + 16 + Size*(epnum-1)
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in_ep[epnum].DIEPCTL |= (1 << USB_OTG_DIEPCTL_USBAEP_Pos) | \
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(epnum - 1) << USB_OTG_DIEPCTL_TXFNUM_Pos | \
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@ -267,9 +276,10 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt)
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dev->DAINTMSK |= (1 << (USB_OTG_DAINTMSK_IEPM_Pos + epnum));
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// Both TXFD and TXSA are in unit of 32-bit words
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uint16_t const fifo_size = 130;
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uint32_t const fifo_offset = (USB2_OTG_FS->GRXFSIZ & 0x0000ffff) + 16 + fifo_size*(epnum-1);
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USB2_OTG_FS->DIEPTXF[epnum - 1] = (130 << USB_OTG_DIEPTXF_INEPTXFD_Pos) | fifo_offset;
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uint16_t const allocated_size = (USB_OTG_FS->GRXFSIZ & 0x0000ffff) + 16;
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uint16_t const fifo_size = (EP_FIFO_SIZE/4 - allocated_size) / (EP_MAX-1);
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uint32_t const fifo_offset = allocated_size + fifo_size*(epnum-1);
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USB_OTG_FS->DIEPTXF[epnum - 1] = (fifo_size << USB_OTG_DIEPTXF_INEPTXFD_Pos) | fifo_offset;
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}
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return true;
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@ -345,9 +355,9 @@ void dcd_edpt_stall (uint8_t rhport, uint8_t ep_addr)
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}
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// Flush the FIFO, and wait until we have confirmed it cleared.
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USB2_OTG_FS->GRSTCTL |= ((epnum - 1) << USB_OTG_GRSTCTL_TXFNUM_Pos);
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USB2_OTG_FS->GRSTCTL |= USB_OTG_GRSTCTL_TXFFLSH;
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while((USB2_OTG_FS->GRSTCTL & USB_OTG_GRSTCTL_TXFFLSH_Msk) != 0);
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USB_OTG_FS->GRSTCTL |= ((epnum - 1) << USB_OTG_GRSTCTL_TXFNUM_Pos);
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USB_OTG_FS->GRSTCTL |= USB_OTG_GRSTCTL_TXFFLSH;
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while((USB_OTG_FS->GRSTCTL & USB_OTG_GRSTCTL_TXFFLSH_Msk) != 0);
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} else {
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// Only disable currently enabled non-control endpoint
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if ( (epnum == 0) || !(out_ep[epnum].DOEPCTL & USB_OTG_DOEPCTL_EPENA) ){
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@ -358,7 +368,7 @@ void dcd_edpt_stall (uint8_t rhport, uint8_t ep_addr)
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// anyway, and it can't be cleared by user code. If this while loop never
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// finishes, we have bigger problems than just the stack.
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dev->DCTL |= USB_OTG_DCTL_SGONAK;
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while((USB2_OTG_FS->GINTSTS & USB_OTG_GINTSTS_BOUTNAKEFF_Msk) == 0);
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while((USB_OTG_FS->GINTSTS & USB_OTG_GINTSTS_BOUTNAKEFF_Msk) == 0);
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// Ditto here- disable the endpoint.
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out_ep[epnum].DOEPCTL |= (USB_OTG_DOEPCTL_STALL | USB_OTG_DOEPCTL_EPDIS);
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@ -512,7 +522,7 @@ static void read_rx_fifo(USB_OTG_OUTEndpointTypeDef * out_ep) {
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// Pop control word off FIFO (completed xfers will have 2 control words,
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// we only pop one ctl word each interrupt).
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uint32_t ctl_word = USB2_OTG_FS->GRXSTSP;
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uint32_t ctl_word = USB_OTG_FS->GRXSTSP;
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uint8_t pktsts = (ctl_word & USB_OTG_GRXSTSP_PKTSTS_Msk) >> USB_OTG_GRXSTSP_PKTSTS_Pos;
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uint8_t epnum = (ctl_word & USB_OTG_GRXSTSP_EPNUM_Msk) >> USB_OTG_GRXSTSP_EPNUM_Pos;
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uint16_t bcnt = (ctl_word & USB_OTG_GRXSTSP_BCNT_Msk) >> USB_OTG_GRXSTSP_BCNT_Pos;
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@ -551,7 +561,7 @@ static void read_rx_fifo(USB_OTG_OUTEndpointTypeDef * out_ep) {
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static void handle_epout_ints(USB_OTG_DeviceTypeDef * dev, USB_OTG_OUTEndpointTypeDef * out_ep) {
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// DAINT for a given EP clears when DOEPINTx is cleared.
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// OEPINT will be cleared when DAINT's out bits are cleared.
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for(int n = 0; n < 8; n++) {
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for(uint8_t n = 0; n < EP_MAX; n++) {
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xfer_ctl_t * xfer = XFER_CTL_BASE(n, TUSB_DIR_OUT);
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if(dev->DAINT & (1 << (USB_OTG_DAINT_OEPINT_Pos + n))) {
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@ -589,7 +599,7 @@ static void handle_epout_ints(USB_OTG_DeviceTypeDef * dev, USB_OTG_OUTEndpointTy
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static void handle_epin_ints(USB_OTG_DeviceTypeDef * dev, USB_OTG_INEndpointTypeDef * in_ep) {
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// DAINT for a given EP clears when DIEPINTx is cleared.
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// IEPINT will be cleared when DAINT's out bits are cleared.
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for(uint8_t n = 0; n < 8; n++) {
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for(uint8_t n = 0; n < EP_MAX; n++) {
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xfer_ctl_t * xfer = XFER_CTL_BASE(n, TUSB_DIR_IN);
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if(dev->DAINT & (1 << (USB_OTG_DAINT_IEPINT_Pos + n))) {
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@ -609,29 +619,30 @@ static void handle_epin_ints(USB_OTG_DeviceTypeDef * dev, USB_OTG_INEndpointType
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}
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}
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void OTG_FS_IRQHandler (void)
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{
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void OTG_FS_IRQHandler(void) {
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USB_OTG_DeviceTypeDef * dev = DEVICE_BASE;
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USB_OTG_OUTEndpointTypeDef * out_ep = OUT_EP_BASE;
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USB_OTG_INEndpointTypeDef * in_ep = IN_EP_BASE;
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uint32_t int_status = USB2_OTG_FS->GINTSTS;
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uint32_t int_status = USB_OTG_FS->GINTSTS;
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if(int_status & USB_OTG_GINTMSK_USBRST)
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{
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USB2_OTG_FS->GINTSTS = USB_OTG_GINTSTS_USBRST;
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if(int_status & USB_OTG_GINTSTS_USBRST) {
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// USBRST is start of reset.
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USB_OTG_FS->GINTSTS = USB_OTG_GINTSTS_USBRST;
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bus_reset();
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}
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if(int_status & USB_OTG_GINTMSK_ENUMDNEM)
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{
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USB2_OTG_FS->GINTSTS = USB_OTG_GINTMSK_ENUMDNEM;
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if(int_status & USB_OTG_GINTSTS_ENUMDNE) {
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// ENUMDNE detects speed of the link. For full-speed, we
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// always expect the same value. This interrupt is considered
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// the end of reset.
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USB_OTG_FS->GINTSTS = USB_OTG_GINTSTS_ENUMDNE;
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end_of_reset();
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dcd_event_bus_signal(0, DCD_EVENT_BUS_RESET, true);
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}
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if(int_status & USB_OTG_GINTSTS_SOF) {
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USB2_OTG_FS->GINTSTS = USB_OTG_GINTSTS_SOF;
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USB_OTG_FS->GINTSTS = USB_OTG_GINTSTS_SOF;
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||||
dcd_event_bus_signal(0, DCD_EVENT_SOF, true);
|
||||
}
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue