ea4357 build with makefile, add to travis
This commit is contained in:
hathach
parent
7bd16aaf9b
commit
3278a9765b
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@ -109,4 +109,4 @@ flash-jlink: $(BUILD)/$(BOARD)-firmware.hex
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@echo r >> $(BUILD)/$(BOARD).jlink
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@echo go >> $(BUILD)/$(BOARD).jlink
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@echo exit >> $(BUILD)/$(BOARD).jlink
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$(JLINKEXE) -device $(JLINK_DEVICE) -if $(JLINK_IF) -speed auto -CommandFile $(BUILD)/$(BOARD).jlink
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$(JLINKEXE) -device $(JLINK_DEVICE) -if $(JLINK_IF) -JTAGConf -1,-1 -speed auto -CommandFile $(BUILD)/$(BOARD).jlink
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@ -0,0 +1,41 @@
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CFLAGS += \
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-mthumb \
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-mabi=aapcs \
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-mcpu=cortex-m4 \
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-nostdlib \
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-DCORE_M4 \
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-DCFG_TUSB_MCU=OPT_MCU_LPC43XX \
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-D__USE_LPCOPEN
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# All source paths should be relative to the top level.
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LD_FILE = hw/bsp/ea4357/lpc4357.ld
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# TODO remove later
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SRC_C += src/portable/$(VENDOR)/$(CHIP_FAMILY)/hal_$(CHIP_FAMILY).c
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SRC_C += \
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hw/mcu/nxp/lpcopen/lpc_chip_43xx/src/chip_18xx_43xx.c \
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hw/mcu/nxp/lpcopen/lpc_chip_43xx/src/clock_18xx_43xx.c \
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hw/mcu/nxp/lpcopen/lpc_chip_43xx/src/gpio_18xx_43xx.c \
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hw/mcu/nxp/lpcopen/lpc_chip_43xx/src/sysinit_18xx_43xx.c \
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hw/mcu/nxp/lpcopen/lpc_chip_43xx/src/i2c_18xx_43xx.c \
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hw/mcu/nxp/lpcopen/lpc_chip_43xx/src/i2cm_18xx_43xx.c \
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hw/mcu/nxp/lpcopen/lpc_chip_43xx/src/uart_18xx_43xx.c
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INC += \
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$(TOP)/hw/mcu/nxp/lpcopen/lpc_chip_43xx/inc \
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$(TOP)/hw/mcu/nxp/lpcopen/lpc_chip_43xx/inc/config_43xx
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# For TinyUSB port source
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VENDOR = nxp
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CHIP_FAMILY = lpc18_43
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# For freeRTOS port source
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FREERTOS_PORT = ARM_CM4
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# For flash-jlink target
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JLINK_DEVICE = LPC4357
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JLINK_IF = jtag
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# flash using jlink
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flash: flash-jlink
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@ -0,0 +1,515 @@
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//*****************************************************************************
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// LPC43xx (Cortex-M4) Microcontroller Startup code for use with LPCXpresso IDE
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//
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// Version : 150706
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//*****************************************************************************
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//
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// Copyright(C) NXP Semiconductors, 2013-2015
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// All rights reserved.
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//
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// Software that is described herein is for illustrative purposes only
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// which provides customers with programming information regarding the
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// LPC products. This software is supplied "AS IS" without any warranties of
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// any kind, and NXP Semiconductors and its licensor disclaim any and
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// all warranties, express or implied, including all implied warranties of
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// merchantability, fitness for a particular purpose and non-infringement of
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// intellectual property rights. NXP Semiconductors assumes no responsibility
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// or liability for the use of the software, conveys no license or rights under any
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// patent, copyright, mask work right, or any other intellectual property rights in
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// or to any products. NXP Semiconductors reserves the right to make changes
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// in the software without notification. NXP Semiconductors also makes no
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// representation or warranty that such application will be suitable for the
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// specified use without further testing or modification.
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//
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// Permission to use, copy, modify, and distribute this software and its
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// documentation is hereby granted, under NXP Semiconductors' and its
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// licensor's relevant copyrights in the software, without fee, provided that it
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// is used in conjunction with NXP Semiconductors microcontrollers. This
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// copyright, permission, and disclaimer notice must appear in all copies of
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// this code.
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//*****************************************************************************
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#if defined (__cplusplus)
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#ifdef __REDLIB__
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#error Redlib does not support C++
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#else
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//*****************************************************************************
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//
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// The entry point for the C++ library startup
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//
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//*****************************************************************************
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extern "C" {
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extern void __libc_init_array(void);
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}
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#endif
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#endif
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#define WEAK __attribute__ ((weak))
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#define ALIAS(f) __attribute__ ((weak, alias (#f)))
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//*****************************************************************************
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#if defined (__cplusplus)
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extern "C" {
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#endif
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//*****************************************************************************
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#if defined (__USE_CMSIS) || defined (__USE_LPCOPEN)
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// Declaration of external SystemInit function
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extern void SystemInit(void);
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#endif
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//*****************************************************************************
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//
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// Forward declaration of the default handlers. These are aliased.
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// When the application defines a handler (with the same name), this will
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// automatically take precedence over these weak definitions
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//
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//*****************************************************************************
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void ResetISR(void);
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WEAK void NMI_Handler(void);
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WEAK void HardFault_Handler(void);
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WEAK void MemManage_Handler(void);
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WEAK void BusFault_Handler(void);
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WEAK void UsageFault_Handler(void);
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WEAK void SVC_Handler(void);
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WEAK void DebugMon_Handler(void);
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WEAK void PendSV_Handler(void);
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WEAK void SysTick_Handler(void);
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WEAK void IntDefaultHandler(void);
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//*****************************************************************************
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//
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// Forward declaration of the specific IRQ handlers. These are aliased
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// to the IntDefaultHandler, which is a 'forever' loop. When the application
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// defines a handler (with the same name), this will automatically take
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// precedence over these weak definitions
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//
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//*****************************************************************************
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void DAC_IRQHandler(void) ALIAS(IntDefaultHandler);
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#if defined (__USE_LPCOPEN)
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void M0APP_IRQHandler(void) ALIAS(IntDefaultHandler);
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#else
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void M0CORE_IRQHandler(void) ALIAS(IntDefaultHandler);
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#endif
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void DMA_IRQHandler(void) ALIAS(IntDefaultHandler);
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void FLASH_EEPROM_IRQHandler(void) ALIAS(IntDefaultHandler);
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void ETH_IRQHandler(void) ALIAS(IntDefaultHandler);
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void SDIO_IRQHandler(void) ALIAS(IntDefaultHandler);
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void LCD_IRQHandler(void) ALIAS(IntDefaultHandler);
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void USB0_IRQHandler(void) ALIAS(IntDefaultHandler);
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void USB1_IRQHandler(void) ALIAS(IntDefaultHandler);
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void SCT_IRQHandler(void) ALIAS(IntDefaultHandler);
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void RIT_IRQHandler(void) ALIAS(IntDefaultHandler);
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void TIMER0_IRQHandler(void) ALIAS(IntDefaultHandler);
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void TIMER1_IRQHandler(void) ALIAS(IntDefaultHandler);
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void TIMER2_IRQHandler(void) ALIAS(IntDefaultHandler);
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void TIMER3_IRQHandler(void) ALIAS(IntDefaultHandler);
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void MCPWM_IRQHandler(void) ALIAS(IntDefaultHandler);
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void ADC0_IRQHandler(void) ALIAS(IntDefaultHandler);
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void I2C0_IRQHandler(void) ALIAS(IntDefaultHandler);
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void SPI_IRQHandler(void) ALIAS(IntDefaultHandler);
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void I2C1_IRQHandler(void) ALIAS(IntDefaultHandler);
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void ADC1_IRQHandler(void) ALIAS(IntDefaultHandler);
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void SSP0_IRQHandler(void) ALIAS(IntDefaultHandler);
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void SSP1_IRQHandler(void) ALIAS(IntDefaultHandler);
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void UART0_IRQHandler(void) ALIAS(IntDefaultHandler);
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void UART1_IRQHandler(void) ALIAS(IntDefaultHandler);
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void UART2_IRQHandler(void) ALIAS(IntDefaultHandler);
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void UART3_IRQHandler(void) ALIAS(IntDefaultHandler);
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void I2S0_IRQHandler(void) ALIAS(IntDefaultHandler);
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void I2S1_IRQHandler(void) ALIAS(IntDefaultHandler);
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void SPIFI_IRQHandler(void) ALIAS(IntDefaultHandler);
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void SGPIO_IRQHandler(void) ALIAS(IntDefaultHandler);
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void GPIO0_IRQHandler(void) ALIAS(IntDefaultHandler);
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void GPIO1_IRQHandler(void) ALIAS(IntDefaultHandler);
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void GPIO2_IRQHandler(void) ALIAS(IntDefaultHandler);
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void GPIO3_IRQHandler(void) ALIAS(IntDefaultHandler);
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void GPIO4_IRQHandler(void) ALIAS(IntDefaultHandler);
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void GPIO5_IRQHandler(void) ALIAS(IntDefaultHandler);
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void GPIO6_IRQHandler(void) ALIAS(IntDefaultHandler);
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void GPIO7_IRQHandler(void) ALIAS(IntDefaultHandler);
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void GINT0_IRQHandler(void) ALIAS(IntDefaultHandler);
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void GINT1_IRQHandler(void) ALIAS(IntDefaultHandler);
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void EVRT_IRQHandler(void) ALIAS(IntDefaultHandler);
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void CAN1_IRQHandler(void) ALIAS(IntDefaultHandler);
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#if defined (__USE_LPCOPEN)
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void ADCHS_IRQHandler(void) ALIAS(IntDefaultHandler);
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#else
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void VADC_IRQHandler(void) ALIAS(IntDefaultHandler);
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#endif
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void ATIMER_IRQHandler(void) ALIAS(IntDefaultHandler);
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void RTC_IRQHandler(void) ALIAS(IntDefaultHandler);
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void WDT_IRQHandler(void) ALIAS(IntDefaultHandler);
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void M0SUB_IRQHandler(void) ALIAS(IntDefaultHandler);
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void CAN0_IRQHandler(void) ALIAS(IntDefaultHandler);
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void QEI_IRQHandler(void) ALIAS(IntDefaultHandler);
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//*****************************************************************************
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//
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// The entry point for the application.
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// __main() is the entry point for Redlib based applications
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// main() is the entry point for Newlib based applications
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//
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//*****************************************************************************
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#if defined (__REDLIB__)
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extern void __main(void);
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#endif
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extern int main(void);
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//*****************************************************************************
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//
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// External declaration for the pointer to the stack top from the Linker Script
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//
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//*****************************************************************************
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extern void _vStackTop(void);
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//*****************************************************************************
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//
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// External declaration for LPC MCU vector table checksum from Linker Script
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//
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//*****************************************************************************
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WEAK extern void __valid_user_code_checksum(void);
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//*****************************************************************************
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#if defined (__cplusplus)
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} // extern "C"
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#endif
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//*****************************************************************************
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//
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// The vector table.
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// This relies on the linker script to place at correct location in memory.
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//
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//*****************************************************************************
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extern void (* const g_pfnVectors[])(void);
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__attribute__ ((used,section(".isr_vector")))
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void (* const g_pfnVectors[])(void) = {
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// Core Level - CM4
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&_vStackTop, // The initial stack pointer
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ResetISR, // The reset handler
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NMI_Handler, // The NMI handler
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HardFault_Handler, // The hard fault handler
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MemManage_Handler, // The MPU fault handler
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BusFault_Handler, // The bus fault handler
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UsageFault_Handler, // The usage fault handler
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__valid_user_code_checksum, // LPC MCU Checksum
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0, // Reserved
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0, // Reserved
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0, // Reserved
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SVC_Handler, // SVCall handler
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DebugMon_Handler, // Debug monitor handler
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0, // Reserved
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PendSV_Handler, // The PendSV handler
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SysTick_Handler, // The SysTick handler
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// Chip Level - LPC43 (M4)
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DAC_IRQHandler, // 16
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#if defined (__USE_LPCOPEN)
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M0APP_IRQHandler, // 17 CortexM4/M0 (LPC43XX ONLY)
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#else
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M0CORE_IRQHandler, // 17
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#endif
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DMA_IRQHandler, // 18
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0, // 19
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FLASH_EEPROM_IRQHandler, // 20 ORed flash Bank A, flash Bank B, EEPROM interrupts
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ETH_IRQHandler, // 21
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SDIO_IRQHandler, // 22
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LCD_IRQHandler, // 23
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USB0_IRQHandler, // 24
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USB1_IRQHandler, // 25
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SCT_IRQHandler, // 26
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RIT_IRQHandler, // 27
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TIMER0_IRQHandler, // 28
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TIMER1_IRQHandler, // 29
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TIMER2_IRQHandler, // 30
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TIMER3_IRQHandler, // 31
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MCPWM_IRQHandler, // 32
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ADC0_IRQHandler, // 33
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I2C0_IRQHandler, // 34
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I2C1_IRQHandler, // 35
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SPI_IRQHandler, // 36
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ADC1_IRQHandler, // 37
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SSP0_IRQHandler, // 38
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SSP1_IRQHandler, // 39
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UART0_IRQHandler, // 40
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UART1_IRQHandler, // 41
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UART2_IRQHandler, // 42
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UART3_IRQHandler, // 43
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I2S0_IRQHandler, // 44
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I2S1_IRQHandler, // 45
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SPIFI_IRQHandler, // 46
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SGPIO_IRQHandler, // 47
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GPIO0_IRQHandler, // 48
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GPIO1_IRQHandler, // 49
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GPIO2_IRQHandler, // 50
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GPIO3_IRQHandler, // 51
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GPIO4_IRQHandler, // 52
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GPIO5_IRQHandler, // 53
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GPIO6_IRQHandler, // 54
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GPIO7_IRQHandler, // 55
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GINT0_IRQHandler, // 56
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GINT1_IRQHandler, // 57
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EVRT_IRQHandler, // 58
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CAN1_IRQHandler, // 59
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0, // 60
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#if defined (__USE_LPCOPEN)
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ADCHS_IRQHandler, // 61 ADCHS combined interrupt
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#else
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VADC_IRQHandler, // 61
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#endif
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ATIMER_IRQHandler, // 62
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RTC_IRQHandler, // 63
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0, // 64
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WDT_IRQHandler, // 65
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M0SUB_IRQHandler, // 66
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CAN0_IRQHandler, // 67
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QEI_IRQHandler, // 68
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};
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//*****************************************************************************
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// Functions to carry out the initialization of RW and BSS data sections. These
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// are written as separate functions rather than being inlined within the
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// ResetISR() function in order to cope with MCUs with multiple banks of
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// memory.
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//*****************************************************************************
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__attribute__((section(".after_vectors"
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)))
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void data_init(unsigned int romstart, unsigned int start, unsigned int len) {
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unsigned int *pulDest = (unsigned int*) start;
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unsigned int *pulSrc = (unsigned int*) romstart;
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unsigned int loop;
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for (loop = 0; loop < len; loop = loop + 4)
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*pulDest++ = *pulSrc++;
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}
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__attribute__ ((section(".after_vectors")))
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void bss_init(unsigned int start, unsigned int len) {
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unsigned int *pulDest = (unsigned int*) start;
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unsigned int loop;
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for (loop = 0; loop < len; loop = loop + 4)
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*pulDest++ = 0;
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}
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//*****************************************************************************
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// The following symbols are constructs generated by the linker, indicating
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// the location of various points in the "Global Section Table". This table is
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// created by the linker via the Code Red managed linker script mechanism. It
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// contains the load address, execution address and length of each RW data
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// section and the execution and length of each BSS (zero initialized) section.
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//*****************************************************************************
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extern unsigned int __data_section_table;
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extern unsigned int __data_section_table_end;
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extern unsigned int __bss_section_table;
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extern unsigned int __bss_section_table_end;
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//*****************************************************************************
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// Reset entry point for your code.
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// Sets up a simple runtime environment and initializes the C/C++
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// library.
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//
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//*****************************************************************************
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void ResetISR(void) {
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// *************************************************************
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// The following conditional block of code manually resets as
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// much of the peripheral set of the LPC43 as possible. This is
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// done because the LPC43 does not provide a means of triggering
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// a full system reset under debugger control, which can cause
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// problems in certain circumstances when debugging.
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//
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// You can prevent this code block being included if you require
|
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// (for example when creating a final executable which you will
|
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// not debug) by setting the define 'DONT_RESET_ON_RESTART'.
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//
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#ifndef DONT_RESET_ON_RESTART
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// Disable interrupts
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__asm volatile ("cpsid i");
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// equivalent to CMSIS '__disable_irq()' function
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unsigned int *RESET_CONTROL = (unsigned int *) 0x40053100;
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// LPC_RGU->RESET_CTRL0 @ 0x40053100
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// LPC_RGU->RESET_CTRL1 @ 0x40053104
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// Note that we do not use the CMSIS register access mechanism,
|
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// as there is no guarantee that the project has been configured
|
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// to use CMSIS.
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||||
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// Write to LPC_RGU->RESET_CTRL0
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*(RESET_CONTROL + 0) = 0x10DF1000;
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// GPIO_RST|AES_RST|ETHERNET_RST|SDIO_RST|DMA_RST|
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// USB1_RST|USB0_RST|LCD_RST|M0_SUB_RST
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// Write to LPC_RGU->RESET_CTRL1
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*(RESET_CONTROL + 1) = 0x01DFF7FF;
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// M0APP_RST|CAN0_RST|CAN1_RST|I2S_RST|SSP1_RST|SSP0_RST|
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// I2C1_RST|I2C0_RST|UART3_RST|UART1_RST|UART1_RST|UART0_RST|
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// DAC_RST|ADC1_RST|ADC0_RST|QEI_RST|MOTOCONPWM_RST|SCT_RST|
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// RITIMER_RST|TIMER3_RST|TIMER2_RST|TIMER1_RST|TIMER0_RST
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// Clear all pending interrupts in the NVIC
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volatile unsigned int *NVIC_ICPR = (unsigned int *) 0xE000E280;
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unsigned int irqpendloop;
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for (irqpendloop = 0; irqpendloop < 8; irqpendloop++) {
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*(NVIC_ICPR + irqpendloop) = 0xFFFFFFFF;
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}
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// Reenable interrupts
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__asm volatile ("cpsie i");
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// equivalent to CMSIS '__enable_irq()' function
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#endif // ifndef DONT_RESET_ON_RESTART
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||||
// *************************************************************
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||||
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#if defined (__USE_LPCOPEN)
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SystemInit();
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||||
#endif
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//
|
||||
// Copy the data sections from flash to SRAM.
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||||
//
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unsigned int LoadAddr, ExeAddr, SectionLen;
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unsigned int *SectionTableAddr;
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// Load base address of Global Section Table
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SectionTableAddr = &__data_section_table;
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||||
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||||
// Copy the data sections from flash to SRAM.
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||||
while (SectionTableAddr < &__data_section_table_end) {
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||||
LoadAddr = *SectionTableAddr++;
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||||
ExeAddr = *SectionTableAddr++;
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||||
SectionLen = *SectionTableAddr++;
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data_init(LoadAddr, ExeAddr, SectionLen);
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||||
}
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||||
// At this point, SectionTableAddr = &__bss_section_table;
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||||
// Zero fill the bss segment
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||||
while (SectionTableAddr < &__bss_section_table_end) {
|
||||
ExeAddr = *SectionTableAddr++;
|
||||
SectionLen = *SectionTableAddr++;
|
||||
bss_init(ExeAddr, SectionLen);
|
||||
}
|
||||
|
||||
#if !defined (__USE_LPCOPEN)
|
||||
// LPCOpen init code deals with FP and VTOR initialisation
|
||||
#if defined (__VFP_FP__) && !defined (__SOFTFP__)
|
||||
/*
|
||||
* Code to enable the Cortex-M4 FPU only included
|
||||
* if appropriate build options have been selected.
|
||||
* Code taken from Section 7.1, Cortex-M4 TRM (DDI0439C)
|
||||
*/
|
||||
// CPACR is located at address 0xE000ED88
|
||||
asm("LDR.W R0, =0xE000ED88");
|
||||
// Read CPACR
|
||||
asm("LDR R1, [R0]");
|
||||
// Set bits 20-23 to enable CP10 and CP11 coprocessors
|
||||
asm(" ORR R1, R1, #(0xF << 20)");
|
||||
// Write back the modified value to the CPACR
|
||||
asm("STR R1, [R0]");
|
||||
#endif // (__VFP_FP__) && !(__SOFTFP__)
|
||||
// ******************************
|
||||
// Check to see if we are running the code from a non-zero
|
||||
// address (eg RAM, external flash), in which case we need
|
||||
// to modify the VTOR register to tell the CPU that the
|
||||
// vector table is located at a non-0x0 address.
|
||||
|
||||
// Note that we do not use the CMSIS register access mechanism,
|
||||
// as there is no guarantee that the project has been configured
|
||||
// to use CMSIS.
|
||||
unsigned int * pSCB_VTOR = (unsigned int *) 0xE000ED08;
|
||||
if ((unsigned int *) g_pfnVectors != (unsigned int *) 0x00000000) {
|
||||
// CMSIS : SCB->VTOR = <address of vector table>
|
||||
*pSCB_VTOR = (unsigned int) g_pfnVectors;
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined (__USE_CMSIS)
|
||||
SystemInit();
|
||||
#endif
|
||||
|
||||
#if defined (__cplusplus)
|
||||
//
|
||||
// Call C++ library initialisation
|
||||
//
|
||||
__libc_init_array();
|
||||
#endif
|
||||
|
||||
#if defined (__REDLIB__)
|
||||
// Call the Redlib library, which in turn calls main()
|
||||
__main();
|
||||
#else
|
||||
main();
|
||||
#endif
|
||||
|
||||
//
|
||||
// main() shouldn't return, but if it does, we'll just enter an infinite loop
|
||||
//
|
||||
while (1) {
|
||||
;
|
||||
}
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
// Default exception handlers. Override the ones here by defining your own
|
||||
// handler routines in your application code.
|
||||
//*****************************************************************************
|
||||
__attribute__ ((section(".after_vectors")))
|
||||
void NMI_Handler(void) {
|
||||
while (1) {
|
||||
}
|
||||
}
|
||||
__attribute__ ((section(".after_vectors")))
|
||||
void HardFault_Handler(void) {
|
||||
while (1) {
|
||||
}
|
||||
}
|
||||
__attribute__ ((section(".after_vectors")))
|
||||
void MemManage_Handler(void) {
|
||||
while (1) {
|
||||
}
|
||||
}
|
||||
__attribute__ ((section(".after_vectors")))
|
||||
void BusFault_Handler(void) {
|
||||
while (1) {
|
||||
}
|
||||
}
|
||||
__attribute__ ((section(".after_vectors")))
|
||||
void UsageFault_Handler(void) {
|
||||
while (1) {
|
||||
}
|
||||
}
|
||||
__attribute__ ((section(".after_vectors")))
|
||||
void SVC_Handler(void) {
|
||||
while (1) {
|
||||
}
|
||||
}
|
||||
__attribute__ ((section(".after_vectors")))
|
||||
void DebugMon_Handler(void) {
|
||||
while (1) {
|
||||
}
|
||||
}
|
||||
__attribute__ ((section(".after_vectors")))
|
||||
void PendSV_Handler(void) {
|
||||
while (1) {
|
||||
}
|
||||
}
|
||||
__attribute__ ((section(".after_vectors")))
|
||||
void SysTick_Handler(void) {
|
||||
while (1) {
|
||||
}
|
||||
}
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Processor ends up here if an unexpected interrupt occurs or a specific
|
||||
// handler is not present in the application code.
|
||||
//
|
||||
//*****************************************************************************
|
||||
__attribute__ ((section(".after_vectors")))
|
||||
void IntDefaultHandler(void) {
|
||||
while (1) {
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,324 @@
|
|||
/*
|
||||
* GENERATED FILE - DO NOT EDIT
|
||||
* (c) Code Red Technologies Ltd, 2008-2013
|
||||
* (c) NXP Semiconductors 2013-2019
|
||||
* Generated linker script file for LPC4357
|
||||
* Created from linkscript.ldt by FMCreateLinkLibraries
|
||||
* Using Freemarker v2.3.23
|
||||
* MCUXpresso IDE v10.2.1 [Build 795] [2018-07-25] on May 15, 2019 5:48:43 PM
|
||||
*/
|
||||
|
||||
MEMORY
|
||||
{
|
||||
/* Define each memory region */
|
||||
MFlashA512 (rx) : ORIGIN = 0x1a000000, LENGTH = 0x80000 /* 512K bytes (alias Flash) */
|
||||
MFlashB512 (rx) : ORIGIN = 0x1b000000, LENGTH = 0x80000 /* 512K bytes (alias Flash2) */
|
||||
RamLoc32 (rwx) : ORIGIN = 0x10000000, LENGTH = 0x8000 /* 32K bytes (alias RAM) */
|
||||
RamLoc40 (rwx) : ORIGIN = 0x10080000, LENGTH = 0xa000 /* 40K bytes (alias RAM2) */
|
||||
RamAHB32 (rwx) : ORIGIN = 0x20000000, LENGTH = 0x8000 /* 32K bytes (alias RAM3) */
|
||||
RamAHB16 (rwx) : ORIGIN = 0x20008000, LENGTH = 0x4000 /* 16K bytes (alias RAM4) */
|
||||
RamAHB_ETB16 (rwx) : ORIGIN = 0x2000c000, LENGTH = 0x4000 /* 16K bytes (alias RAM5) */
|
||||
}
|
||||
|
||||
/* Define a symbol for the top of each memory region */
|
||||
__base_MFlashA512 = 0x1a000000 ; /* MFlashA512 */
|
||||
__base_Flash = 0x1a000000 ; /* Flash */
|
||||
__top_MFlashA512 = 0x1a000000 + 0x80000 ; /* 512K bytes */
|
||||
__top_Flash = 0x1a000000 + 0x80000 ; /* 512K bytes */
|
||||
__base_MFlashB512 = 0x1b000000 ; /* MFlashB512 */
|
||||
__base_Flash2 = 0x1b000000 ; /* Flash2 */
|
||||
__top_MFlashB512 = 0x1b000000 + 0x80000 ; /* 512K bytes */
|
||||
__top_Flash2 = 0x1b000000 + 0x80000 ; /* 512K bytes */
|
||||
__base_RamLoc32 = 0x10000000 ; /* RamLoc32 */
|
||||
__base_RAM = 0x10000000 ; /* RAM */
|
||||
__top_RamLoc32 = 0x10000000 + 0x8000 ; /* 32K bytes */
|
||||
__top_RAM = 0x10000000 + 0x8000 ; /* 32K bytes */
|
||||
__base_RamLoc40 = 0x10080000 ; /* RamLoc40 */
|
||||
__base_RAM2 = 0x10080000 ; /* RAM2 */
|
||||
__top_RamLoc40 = 0x10080000 + 0xa000 ; /* 40K bytes */
|
||||
__top_RAM2 = 0x10080000 + 0xa000 ; /* 40K bytes */
|
||||
__base_RamAHB32 = 0x20000000 ; /* RamAHB32 */
|
||||
__base_RAM3 = 0x20000000 ; /* RAM3 */
|
||||
__top_RamAHB32 = 0x20000000 + 0x8000 ; /* 32K bytes */
|
||||
__top_RAM3 = 0x20000000 + 0x8000 ; /* 32K bytes */
|
||||
__base_RamAHB16 = 0x20008000 ; /* RamAHB16 */
|
||||
__base_RAM4 = 0x20008000 ; /* RAM4 */
|
||||
__top_RamAHB16 = 0x20008000 + 0x4000 ; /* 16K bytes */
|
||||
__top_RAM4 = 0x20008000 + 0x4000 ; /* 16K bytes */
|
||||
__base_RamAHB_ETB16 = 0x2000c000 ; /* RamAHB_ETB16 */
|
||||
__base_RAM5 = 0x2000c000 ; /* RAM5 */
|
||||
__top_RamAHB_ETB16 = 0x2000c000 + 0x4000 ; /* 16K bytes */
|
||||
__top_RAM5 = 0x2000c000 + 0x4000 ; /* 16K bytes */
|
||||
|
||||
|
||||
ENTRY(ResetISR)
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
.text_Flash2 : ALIGN(4)
|
||||
{
|
||||
FILL(0xff)
|
||||
*(.text_Flash2*) /* for compatibility with previous releases */
|
||||
*(.text_MFlashB512*) /* for compatibility with previous releases */
|
||||
*(.text.$Flash2*)
|
||||
*(.text.$MFlashB512*)
|
||||
*(.rodata.$Flash2*)
|
||||
*(.rodata.$MFlashB512*)
|
||||
} > MFlashB512
|
||||
|
||||
/* MAIN TEXT SECTION */
|
||||
.text : ALIGN(4)
|
||||
{
|
||||
FILL(0xff)
|
||||
__vectors_start__ = ABSOLUTE(.) ;
|
||||
KEEP(*(.isr_vector))
|
||||
/* Global Section Table */
|
||||
. = ALIGN(4) ;
|
||||
__section_table_start = .;
|
||||
__data_section_table = .;
|
||||
LONG(LOADADDR(.data));
|
||||
LONG( ADDR(.data));
|
||||
LONG( SIZEOF(.data));
|
||||
LONG(LOADADDR(.data_RAM2));
|
||||
LONG( ADDR(.data_RAM2));
|
||||
LONG( SIZEOF(.data_RAM2));
|
||||
LONG(LOADADDR(.data_RAM3));
|
||||
LONG( ADDR(.data_RAM3));
|
||||
LONG( SIZEOF(.data_RAM3));
|
||||
LONG(LOADADDR(.data_RAM4));
|
||||
LONG( ADDR(.data_RAM4));
|
||||
LONG( SIZEOF(.data_RAM4));
|
||||
LONG(LOADADDR(.data_RAM5));
|
||||
LONG( ADDR(.data_RAM5));
|
||||
LONG( SIZEOF(.data_RAM5));
|
||||
__data_section_table_end = .;
|
||||
__bss_section_table = .;
|
||||
LONG( ADDR(.bss));
|
||||
LONG( SIZEOF(.bss));
|
||||
LONG( ADDR(.bss_RAM2));
|
||||
LONG( SIZEOF(.bss_RAM2));
|
||||
LONG( ADDR(.bss_RAM3));
|
||||
LONG( SIZEOF(.bss_RAM3));
|
||||
LONG( ADDR(.bss_RAM4));
|
||||
LONG( SIZEOF(.bss_RAM4));
|
||||
LONG( ADDR(.bss_RAM5));
|
||||
LONG( SIZEOF(.bss_RAM5));
|
||||
__bss_section_table_end = .;
|
||||
__section_table_end = . ;
|
||||
/* End of Global Section Table */
|
||||
|
||||
*(.after_vectors*)
|
||||
|
||||
} > MFlashA512
|
||||
|
||||
.text : ALIGN(4)
|
||||
{
|
||||
*(.text*)
|
||||
*(.rodata .rodata.* .constdata .constdata.*)
|
||||
. = ALIGN(4);
|
||||
} > MFlashA512
|
||||
/*
|
||||
* for exception handling/unwind - some Newlib functions (in common
|
||||
* with C++ and STDC++) use this.
|
||||
*/
|
||||
.ARM.extab : ALIGN(4)
|
||||
{
|
||||
*(.ARM.extab* .gnu.linkonce.armextab.*)
|
||||
} > MFlashA512
|
||||
|
||||
__exidx_start = .;
|
||||
|
||||
.ARM.exidx : ALIGN(4)
|
||||
{
|
||||
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
|
||||
} > MFlashA512
|
||||
__exidx_end = .;
|
||||
|
||||
_etext = .;
|
||||
|
||||
/* DATA section for RamLoc40 */
|
||||
|
||||
.data_RAM2 : ALIGN(4)
|
||||
{
|
||||
FILL(0xff)
|
||||
PROVIDE(__start_data_RAM2 = .) ;
|
||||
*(.ramfunc.$RAM2)
|
||||
*(.ramfunc.$RamLoc40)
|
||||
*(.data.$RAM2*)
|
||||
*(.data.$RamLoc40*)
|
||||
. = ALIGN(4) ;
|
||||
PROVIDE(__end_data_RAM2 = .) ;
|
||||
} > RamLoc40 AT>MFlashA512
|
||||
/* DATA section for RamAHB32 */
|
||||
|
||||
.data_RAM3 : ALIGN(4)
|
||||
{
|
||||
FILL(0xff)
|
||||
PROVIDE(__start_data_RAM3 = .) ;
|
||||
*(.ramfunc.$RAM3)
|
||||
*(.ramfunc.$RamAHB32)
|
||||
*(.data.$RAM3*)
|
||||
*(.data.$RamAHB32*)
|
||||
. = ALIGN(4) ;
|
||||
PROVIDE(__end_data_RAM3 = .) ;
|
||||
} > RamAHB32 AT>MFlashA512
|
||||
/* DATA section for RamAHB16 */
|
||||
|
||||
.data_RAM4 : ALIGN(4)
|
||||
{
|
||||
FILL(0xff)
|
||||
PROVIDE(__start_data_RAM4 = .) ;
|
||||
*(.ramfunc.$RAM4)
|
||||
*(.ramfunc.$RamAHB16)
|
||||
*(.data.$RAM4*)
|
||||
*(.data.$RamAHB16*)
|
||||
. = ALIGN(4) ;
|
||||
PROVIDE(__end_data_RAM4 = .) ;
|
||||
} > RamAHB16 AT>MFlashA512
|
||||
/* DATA section for RamAHB_ETB16 */
|
||||
|
||||
.data_RAM5 : ALIGN(4)
|
||||
{
|
||||
FILL(0xff)
|
||||
PROVIDE(__start_data_RAM5 = .) ;
|
||||
*(.ramfunc.$RAM5)
|
||||
*(.ramfunc.$RamAHB_ETB16)
|
||||
*(.data.$RAM5*)
|
||||
*(.data.$RamAHB_ETB16*)
|
||||
. = ALIGN(4) ;
|
||||
PROVIDE(__end_data_RAM5 = .) ;
|
||||
} > RamAHB_ETB16 AT>MFlashA512
|
||||
/* MAIN DATA SECTION */
|
||||
.uninit_RESERVED : ALIGN(4)
|
||||
{
|
||||
KEEP(*(.bss.$RESERVED*))
|
||||
. = ALIGN(4) ;
|
||||
_end_uninit_RESERVED = .;
|
||||
} > RamLoc32
|
||||
|
||||
/* Main DATA section (RamLoc32) */
|
||||
.data : ALIGN(4)
|
||||
{
|
||||
FILL(0xff)
|
||||
_data = . ;
|
||||
*(vtable)
|
||||
*(.ramfunc*)
|
||||
*(.data*)
|
||||
. = ALIGN(4) ;
|
||||
_edata = . ;
|
||||
} > RamLoc32 AT>MFlashA512
|
||||
|
||||
/* BSS section for RamLoc40 */
|
||||
.bss_RAM2 : ALIGN(4)
|
||||
{
|
||||
PROVIDE(__start_bss_RAM2 = .) ;
|
||||
*(.bss.$RAM2*)
|
||||
*(.bss.$RamLoc40*)
|
||||
. = ALIGN (. != 0 ? 4 : 1) ; /* avoid empty segment */
|
||||
PROVIDE(__end_bss_RAM2 = .) ;
|
||||
} > RamLoc40
|
||||
|
||||
/* BSS section for RamAHB32 */
|
||||
.bss_RAM3 : ALIGN(4)
|
||||
{
|
||||
PROVIDE(__start_bss_RAM3 = .) ;
|
||||
*(.bss.$RAM3*)
|
||||
*(.bss.$RamAHB32*)
|
||||
. = ALIGN (. != 0 ? 4 : 1) ; /* avoid empty segment */
|
||||
PROVIDE(__end_bss_RAM3 = .) ;
|
||||
} > RamAHB32
|
||||
|
||||
/* BSS section for RamAHB16 */
|
||||
.bss_RAM4 : ALIGN(4)
|
||||
{
|
||||
PROVIDE(__start_bss_RAM4 = .) ;
|
||||
*(.bss.$RAM4*)
|
||||
*(.bss.$RamAHB16*)
|
||||
. = ALIGN (. != 0 ? 4 : 1) ; /* avoid empty segment */
|
||||
PROVIDE(__end_bss_RAM4 = .) ;
|
||||
} > RamAHB16
|
||||
|
||||
/* BSS section for RamAHB_ETB16 */
|
||||
.bss_RAM5 : ALIGN(4)
|
||||
{
|
||||
PROVIDE(__start_bss_RAM5 = .) ;
|
||||
*(.bss.$RAM5*)
|
||||
*(.bss.$RamAHB_ETB16*)
|
||||
. = ALIGN (. != 0 ? 4 : 1) ; /* avoid empty segment */
|
||||
PROVIDE(__end_bss_RAM5 = .) ;
|
||||
} > RamAHB_ETB16
|
||||
|
||||
/* MAIN BSS SECTION */
|
||||
.bss : ALIGN(4)
|
||||
{
|
||||
_bss = .;
|
||||
*(.bss*)
|
||||
*(COMMON)
|
||||
. = ALIGN(4) ;
|
||||
_ebss = .;
|
||||
PROVIDE(end = .);
|
||||
} > RamLoc32
|
||||
|
||||
/* NOINIT section for RamLoc40 */
|
||||
.noinit_RAM2 (NOLOAD) : ALIGN(4)
|
||||
{
|
||||
*(.noinit.$RAM2*)
|
||||
*(.noinit.$RamLoc40*)
|
||||
. = ALIGN(4) ;
|
||||
} > RamLoc40
|
||||
|
||||
/* NOINIT section for RamAHB32 */
|
||||
.noinit_RAM3 (NOLOAD) : ALIGN(4)
|
||||
{
|
||||
*(.noinit.$RAM3*)
|
||||
*(.noinit.$RamAHB32*)
|
||||
. = ALIGN(4) ;
|
||||
} > RamAHB32
|
||||
|
||||
/* NOINIT section for RamAHB16 */
|
||||
.noinit_RAM4 (NOLOAD) : ALIGN(4)
|
||||
{
|
||||
*(.noinit.$RAM4*)
|
||||
*(.noinit.$RamAHB16*)
|
||||
. = ALIGN(4) ;
|
||||
} > RamAHB16
|
||||
|
||||
/* NOINIT section for RamAHB_ETB16 */
|
||||
.noinit_RAM5 (NOLOAD) : ALIGN(4)
|
||||
{
|
||||
*(.noinit.$RAM5*)
|
||||
*(.noinit.$RamAHB_ETB16*)
|
||||
. = ALIGN(4) ;
|
||||
} > RamAHB_ETB16
|
||||
|
||||
/* DEFAULT NOINIT SECTION */
|
||||
.noinit (NOLOAD): ALIGN(4)
|
||||
{
|
||||
_noinit = .;
|
||||
*(.noinit*)
|
||||
. = ALIGN(4) ;
|
||||
_end_noinit = .;
|
||||
} > RamLoc32
|
||||
PROVIDE(_pvHeapStart = DEFINED(__user_heap_base) ? __user_heap_base : .);
|
||||
PROVIDE(_vStackTop = DEFINED(__user_stack_top) ? __user_stack_top : __top_RamLoc32 - 0);
|
||||
|
||||
/* ## Create checksum value (used in startup) ## */
|
||||
PROVIDE(__valid_user_code_checksum = 0 -
|
||||
(_vStackTop
|
||||
+ (ResetISR + 1)
|
||||
+ (NMI_Handler + 1)
|
||||
+ (HardFault_Handler + 1)
|
||||
+ (( DEFINED(MemManage_Handler) ? MemManage_Handler : 0 ) + 1) /* MemManage_Handler may not be defined */
|
||||
+ (( DEFINED(BusFault_Handler) ? BusFault_Handler : 0 ) + 1) /* BusFault_Handler may not be defined */
|
||||
+ (( DEFINED(UsageFault_Handler) ? UsageFault_Handler : 0 ) + 1) /* UsageFault_Handler may not be defined */
|
||||
) );
|
||||
|
||||
/* Provide basic symbols giving location and size of main text
|
||||
* block, including initial values of RW data sections. Note that
|
||||
* these will need extending to give a complete picture with
|
||||
* complex images (e.g multiple Flash banks).
|
||||
*/
|
||||
_image_start = LOADADDR(.text);
|
||||
_image_end = LOADADDR(.data) + SIZEOF(.data);
|
||||
_image_size = _image_end - _image_start;
|
||||
}
|
||||
|
|
@ -13,7 +13,7 @@ fail_count = 0
|
|||
exit_status = 0
|
||||
|
||||
all_device_example = ["cdc_msc_hid", "msc_dual_lun", "hid_generic_inout"]
|
||||
all_boards = ["metro_m0_express", "metro_m4_express", "pca10056", "feather_nrf52840_express", "stm32f407g_disc1", "lpcxpresso11u68", "lpcxpresso1347", "lpcxpresso1769", "mcb1800", "ea4088qs"]
|
||||
all_boards = ["metro_m0_express", "metro_m4_express", "pca10056", "feather_nrf52840_express", "stm32f407g_disc1", "lpcxpresso11u68", "lpcxpresso1347", "lpcxpresso1769", "mcb1800", "ea4088qs", "ea4357"]
|
||||
|
||||
def build_example(example, board):
|
||||
subprocess.run("make -C examples/device/{} BOARD={} clean".format(example, board), shell=True, stdout=subprocess.PIPE, stderr=subprocess.STDOUT)
|
||||
|
|
|
|||
Loading…
Reference in New Issue