able to complete 1st get device descriptor and set address
This commit is contained in:
hathach
parent
e3f3179924
commit
2c237b1ae4
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@ -156,7 +156,7 @@ enum {
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};
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enum {
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DEFAULT_HIEN = HIRQ_CONDET_IRQ | HIRQ_FRAME_IRQ | HIRQ_HXFRDN_IRQ
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DEFAULT_HIEN = HIRQ_CONDET_IRQ | HIRQ_FRAME_IRQ | HIRQ_HXFRDN_IRQ | HIRQ_RCVDAV_IRQ
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};
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//--------------------------------------------------------------------+
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@ -178,6 +178,8 @@ typedef struct {
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// cached register
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uint8_t sndbc;
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uint8_t hirq;
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uint8_t hien;
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uint8_t mode;
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uint8_t peraddr;
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uint8_t hxfr;
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@ -203,60 +205,86 @@ bool tuh_max3421_spi_xfer_api(uint8_t rhport, uint8_t const * tx_buf, size_t tx_
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//--------------------------------------------------------------------+
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static void fifo_write(uint8_t reg, uint8_t const * buffer, uint16_t len) {
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uint8_t const rhport = 0;
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uint8_t hirq;
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reg |= CMDBYTE_WRITE;
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tuh_max3421_spi_cs_api(0, true);
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tuh_max3421_spi_cs_api(rhport, true);
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tuh_max3421_spi_xfer_api(0, ®, 1, NULL, 0);
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tuh_max3421_spi_xfer_api(0, buffer, len, NULL, 0);
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tuh_max3421_spi_xfer_api(rhport, ®, 1, &hirq, 1);
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_hcd_data.hirq = hirq;
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tuh_max3421_spi_xfer_api(rhport, buffer, len, NULL, 0);
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tuh_max3421_spi_cs_api(rhport, false);
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tuh_max3421_spi_cs_api(0, false);
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}
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// return HIRQ register since we are in full-duplex mode
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static uint8_t reg_write(uint8_t reg, uint8_t data) {
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static void fifo_read(uint8_t * buffer, uint16_t len) {
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uint8_t const rhport = 0;
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uint8_t hirq;
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uint8_t const reg = RCVVFIFO_ADDR;
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tuh_max3421_spi_cs_api(rhport, true);
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tuh_max3421_spi_xfer_api(rhport, ®, 1, &hirq, 0);
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_hcd_data.hirq = hirq;
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tuh_max3421_spi_xfer_api(rhport, NULL, 0, buffer, len);
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tuh_max3421_spi_cs_api(rhport, false);
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}
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static void reg_write(uint8_t reg, uint8_t data) {
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uint8_t const rhport = 0;
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uint8_t tx_buf[2] = {reg | CMDBYTE_WRITE, data};
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uint8_t rx_buf[2] = {0, 0};
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tuh_max3421_spi_cs_api(0, true);
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tuh_max3421_spi_xfer_api(0, tx_buf, 2, rx_buf, 2);
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tuh_max3421_spi_cs_api(0, false);
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tuh_max3421_spi_cs_api(rhport, true);
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tuh_max3421_spi_xfer_api(rhport, tx_buf, 2, rx_buf, 2);
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tuh_max3421_spi_cs_api(rhport, false);
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TU_LOG2("HIRQ: %02X\r\n", rx_buf[0]);
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return rx_buf[0];
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// HIRQ register since we are in full-duplex mode
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_hcd_data.hirq = rx_buf[0];
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TU_LOG3_HEX(_hcd_data.hirq);
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}
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static uint8_t reg_read(uint8_t reg) {
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uint8_t const rhport = 0;
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uint8_t tx_buf[2] = {reg, 0};
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uint8_t rx_buf[2] = {0, 0};
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tuh_max3421_spi_cs_api(0, true);
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bool ret = tuh_max3421_spi_xfer_api(0, tx_buf, 2, rx_buf, 2);
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tuh_max3421_spi_cs_api(0, false);
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tuh_max3421_spi_cs_api(rhport, true);
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bool ret = tuh_max3421_spi_xfer_api(rhport, tx_buf, 2, rx_buf, 2);
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tuh_max3421_spi_cs_api(rhport, false);
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_hcd_data.hirq = rx_buf[0];
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return ret ? rx_buf[1] : 0;
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}
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static inline uint8_t mode_write(uint8_t data) {
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_hcd_data.mode = data;
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return reg_write(MODE_ADDR, data);
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static inline void hien_write(uint8_t data) {
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_hcd_data.hien = data;
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reg_write(HIEN_ADDR, data);
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}
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static inline uint8_t peraddr_write(uint8_t data) {
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if ( _hcd_data.peraddr == data ) return 0; // no need to change address
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static inline void mode_write(uint8_t data) {
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_hcd_data.mode = data;
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reg_write(MODE_ADDR, data);
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}
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static inline void peraddr_write(uint8_t data) {
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if ( _hcd_data.peraddr == data ) return; // no need to change address
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_hcd_data.peraddr = data;
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return reg_write(PERADDR_ADDR, data);
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reg_write(PERADDR_ADDR, data);
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}
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static inline uint8_t hxfr_write(uint8_t data) {
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static inline void hxfr_write(uint8_t data) {
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_hcd_data.hxfr = data;
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return reg_write(HXFR_ADDR, data);
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reg_write(HXFR_ADDR, data);
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}
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static inline uint8_t sndbc_write(uint8_t data) {
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static inline void sndbc_write(uint8_t data) {
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_hcd_data.sndbc = data;
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return reg_write(SNDBC_ADDR, data);
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reg_write(SNDBC_ADDR, data);
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}
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@ -335,16 +363,16 @@ bool hcd_init(uint8_t rhport) {
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// Mode: Host and DP/DM pull down
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mode_write(MODE_DPPULLDN | MODE_DMPULLDN | MODE_HOST);
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// bus reset, this will trigger CONDET IRQ if device is already connected
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reg_write(HCTL_ADDR, HCTL_BUSRST);
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// frame reset & bus reset, this will trigger CONDET IRQ if device is already connected
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reg_write(HCTL_ADDR, HCTL_BUSRST | HCTL_FRMRST);
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// clear all previously pending IRQ
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reg_write(HIRQ_ADDR, 0xff);
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_hcd_data.inited = true;
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// Enable Connection IRQ
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reg_write(HIEN_ADDR, DEFAULT_HIEN);
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// Enable IRQ
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hien_write(DEFAULT_HIEN);
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// Enable Interrupt pin
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reg_write(CPUCTL_ADDR, CPUCTL_IE);
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@ -383,8 +411,8 @@ bool hcd_port_connect_status(uint8_t rhport) {
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void hcd_port_reset(uint8_t rhport) {
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(void) rhport;
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// Bus reset will also trigger CONDET IRQ, disable it
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uint8_t hien = DEFAULT_HIEN & ~HIRQ_CONDET_IRQ;
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reg_write(HIEN_ADDR, hien);
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uint8_t const hien = DEFAULT_HIEN & ~HIRQ_CONDET_IRQ;
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hien_write(hien);
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reg_write(HCTL_ADDR, HCTL_BUSRST);
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}
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@ -396,7 +424,7 @@ void hcd_port_reset_end(uint8_t rhport) {
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// Bus reset will also trigger CONDET IRQ, clear and re-enable it after reset
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reg_write(HIRQ_ADDR, HIRQ_CONDET_IRQ);
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reg_write(HIEN_ADDR, DEFAULT_HIEN);
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hien_write(DEFAULT_HIEN);
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}
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// Get port link speed
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@ -426,6 +454,10 @@ bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const
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_hcd_data.ep[ep_num][ep_dir].packet_size = tu_edpt_packet_size(ep_desc);
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if (ep_desc->bEndpointAddress == 0) {
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_hcd_data.ep[ep_num][1].packet_size = tu_edpt_packet_size(ep_desc);
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}
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return true;
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}
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@ -442,15 +474,18 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t daddr, uint8_t ep_addr, uint8_t * buf
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ep->total_len = buflen;
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ep->xferred_len = 0;
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uint8_t hirq = peraddr_write(daddr);
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peraddr_write(daddr);
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uint8_t hctl = 0;
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uint8_t hxfr = ep_num;
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if ( ep_num == 0 ) {
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ep->data_toggle = 1;
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if ( buffer == NULL || buflen == 0 ) {
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// ZLP for ACK stage
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// ZLP for ACK stage, use HS
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hxfr |= HXFR_HS;
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hxfr |= (ep_dir ? 0 : HXFR_OUT_NIN);
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hxfr_write(hxfr);
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return true;
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}
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} else if ( ep->xfer_type == TUSB_XFER_ISOCHRONOUS ) {
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hxfr |= HXFR_ISO;
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@ -458,7 +493,7 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t daddr, uint8_t ep_addr, uint8_t * buf
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if ( 0 == ep_dir ) {
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// Page 12: Programming BULK-OUT Transfers
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TU_ASSERT(hirq & HIRQ_RCVDAV_IRQ);
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TU_ASSERT(_hcd_data.hirq & HIRQ_SNDBAV_IRQ);
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uint8_t const xact_len = (uint8_t) tu_min16(buflen, ep->packet_size);
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fifo_write(SNDFIFO_ADDR, buffer, xact_len);
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@ -516,7 +551,7 @@ static void handle_xfer_done(uint8_t rhport) {
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uint8_t const hrsl = reg_read(HRSL_ADDR);
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uint8_t const result = hrsl & HRSL_RESULT_MASK;
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uint8_t xfer_result;
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xfer_result_t xfer_result;
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TU_LOG3("HRSL: %02X\r\n", hrsl);
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switch(result) {
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@ -537,18 +572,21 @@ static void handle_xfer_done(uint8_t rhport) {
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break;
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}
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uint8_t ep_dir = 0;
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uint8_t ep_num = _hcd_data.hxfr & HXFR_EPNUM_MASK;
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uint8_t const xfer_type = _hcd_data.hxfr & 0xf0;
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hcd_ep_t * ep;
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if ( (xfer_type & HXFR_SETUP) || (xfer_type & HXFR_OUT_NIN) ) {
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// SETUP or OUT transfer
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ep_dir = 0;
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ep = &_hcd_data.ep[ep_num][ep_dir];
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hcd_ep_t *ep = &_hcd_data.ep[ep_num][0];
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uint8_t xact_len;
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if (xfer_type & HXFR_SETUP) {
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xact_len = 8;
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} else if ( xfer_type & HXFR_HS ) {
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xact_len = 0;
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} else {
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xact_len = _hcd_data.sndbc;
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}
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uint8_t const xact_len = (xfer_type & HXFR_SETUP) ? 8 : _hcd_data.sndbc;
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ep->xferred_len += xact_len;
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if ( xact_len < ep->packet_size || ep->xferred_len >= ep->total_len ) {
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@ -558,10 +596,27 @@ static void handle_xfer_done(uint8_t rhport) {
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}
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} else {
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// IN transfer
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ep_dir = 1;
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ep = &_hcd_data.ep[ep_num][ep_dir];
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uint8_t const xact_len = reg_read(RCVBC_ADDR);
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ep->xferred_len += xact_len;
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hcd_ep_t *ep = &_hcd_data.ep[ep_num][1];
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uint8_t xact_len;
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if ( xfer_type & HXFR_HS ) {
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xact_len = 0;
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} else {
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// RCVDAV_IRQ can trigger 2 times (dual buffered)
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while ( _hcd_data.hirq & HIRQ_RCVDAV_IRQ ) {
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uint8_t rcvbc = reg_read(RCVBC_ADDR);
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xact_len = (uint8_t) tu_min16(rcvbc, ep->total_len - ep->xferred_len);
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if ( xact_len ) {
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fifo_read(ep->buf, xact_len);
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ep->buf += xact_len;
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ep->xferred_len += xact_len;
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}
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// ack RCVDVAV IRQ
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reg_write(HIRQ_ADDR, HIRQ_RCVDAV_IRQ);
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_hcd_data.hirq = reg_read(HIRQ_ADDR);
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}
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}
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// short packet or all bytes transferred
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if ( xact_len < ep->packet_size || ep->xferred_len >= ep->total_len ) {
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@ -572,13 +627,35 @@ static void handle_xfer_done(uint8_t rhport) {
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}
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}
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#if CFG_TUSB_DEBUG >= 3
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void print_hirq(uint8_t hirq) {
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TU_LOG3_HEX(hirq);
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if (hirq & HIRQ_HXFRDN_IRQ) TU_LOG3(" HXFRDN");
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if (hirq & HIRQ_FRAME_IRQ) TU_LOG3(" FRAME");
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if (hirq & HIRQ_CONDET_IRQ) TU_LOG3(" CONDET");
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if (hirq & HIRQ_SUSDN_IRQ) TU_LOG3(" SUSDN");
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if (hirq & HIRQ_SNDBAV_IRQ) TU_LOG3(" SNDBAV");
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if (hirq & HIRQ_RCVDAV_IRQ) TU_LOG3(" RCVDAV");
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if (hirq & HIRQ_RWU_IRQ) TU_LOG3(" RWU");
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if (hirq & HIRQ_BUSEVENT_IRQ) TU_LOG3(" BUSEVENT");
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TU_LOG3("\r\n");
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}
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#else
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#define print_hirq(hirq)
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#endif
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// Interrupt Handler
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void hcd_int_handler(uint8_t rhport) {
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// not initialized, do nothing
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if ( !_hcd_data.inited ) return;
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uint8_t hirq = reg_read(HIRQ_ADDR);
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TU_LOG3_HEX(hirq);
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uint8_t hirq = reg_read(HIRQ_ADDR) & _hcd_data.hien;
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if (!hirq) return;
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print_hirq(hirq);
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if (hirq & HIRQ_FRAME_IRQ) {
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_hcd_data.frame_count++;
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@ -598,13 +675,8 @@ void hcd_int_handler(uint8_t rhport) {
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handle_xfer_done(rhport);
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}
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if ( hirq & HIRQ_RCVDAV_IRQ ) {
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TU_LOG3("RCVDAV\r\n");
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TU_LOG3_INT(reg_read(RCVBC_ADDR));
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}
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// clear all interrupt execept SNDBAV_IRQ
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hirq &= ~HIRQ_SNDBAV_IRQ;
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// clear all interrupt except SNDBAV_IRQ and RCVDAV_IRQ must be clear after pulling data from FIFO
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hirq &= ~ (HIRQ_SNDBAV_IRQ | HIRQ_RCVDAV_IRQ);
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if ( hirq ) {
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reg_write(HIRQ_ADDR, hirq);
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}
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