refractor dcd lpc43xx control xfer (with int on complete)
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055285c559
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@ -351,20 +351,35 @@ void dcd_pipe_control_stall(uint8_t coreid)
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}
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// control transfer does not need to use qtd find function
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tusb_error_t dcd_pipe_control_xfer(uint8_t coreid, tusb_direction_t dir, void * buffer, uint16_t length)
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tusb_error_t dcd_pipe_control_xfer(uint8_t coreid, tusb_direction_t dir, void * p_buffer, uint16_t length, bool int_on_complete)
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{
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LPC_USB0_Type* const lpc_usb = LPC_USB[coreid];
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dcd_data_t* p_dcd = dcd_data_ptr[coreid];
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dcd_data_t* const p_dcd = dcd_data_ptr[coreid];
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uint8_t const ep_id = dir; // IN : 1, OUT = 0
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// determine Endpoint where Data & Status phase occurred (IN or OUT)
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uint8_t const ep_data = (dir == TUSB_DIR_DEV_TO_HOST) ? 1 : 0;
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uint8_t const ep_status = 1 - ep_data;
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ASSERT_FALSE(p_dcd->qhd[ep_id].qtd_overlay.active, TUSB_ERROR_FAILED);
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ASSERT_FALSE(p_dcd->qhd[0].qtd_overlay.active || p_dcd->qhd[1].qtd_overlay.active, TUSB_ERROR_FAILED);
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dcd_qtd_t* p_qtd = &p_dcd->qtd[ep_id];
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qtd_init(p_qtd, buffer, length);
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p_dcd->qhd[ep_id].qtd_overlay.next = (uint32_t) p_qtd;
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//------------- Data Phase -------------//
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if (length)
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{
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dcd_qtd_t* p_qtd_data = &p_dcd->qtd[0];
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qtd_init(p_qtd_data, p_buffer, length);
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p_dcd->qhd[ep_data].qtd_overlay.next = (uint32_t) p_qtd_data;
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lpc_usb->ENDPTPRIME = BIT_( edpt_phy2pos(ep_id) );
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lpc_usb->ENDPTPRIME = BIT_( edpt_phy2pos(ep_data) );
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}
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//------------- Status Phase -------------//
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dcd_qtd_t* p_qtd_status = &p_dcd->qtd[1];
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qtd_init(p_qtd_status, NULL, 0); // zero length xfer
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p_qtd_status->int_on_complete = int_on_complete ? 1 : 0;
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p_dcd->qhd[ep_status].qtd_overlay.next = (uint32_t) p_qtd_status;
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LPC_USB0->ENDPTPRIME |= BIT_( edpt_phy2pos(ep_status) );
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return TUSB_ERROR_NONE;
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}
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@ -565,32 +580,47 @@ void dcd_isr(uint8_t coreid)
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if (int_status & INT_MASK_USB)
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{
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uint32_t const edpt_complete = lpc_usb->ENDPTCOMPLETE;
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lpc_usb->ENDPTCOMPLETE = edpt_complete; // acknowledge
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dcd_data_t* const p_dcd = dcd_data_ptr[coreid];
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//------------- Set up Received -------------//
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if (lpc_usb->ENDPTSETUPSTAT)
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{ // 23.10.10.2 Operational model for setup transfers
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dcd_data_t* p_dcd = dcd_data_ptr[coreid];
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tusb_control_request_t control_request = p_dcd->qhd[0].setup_request;
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lpc_usb->ENDPTSETUPSTAT = lpc_usb->ENDPTSETUPSTAT;
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//------------- Flush if previous transfer is not done -------------//
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if (p_dcd->qhd[0].qtd_overlay.active || p_dcd->qhd[1].qtd_overlay.active)
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{
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do
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{
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lpc_usb->ENDPTFLUSH = BIT_(0) | BIT_(16);
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while(lpc_usb->ENDPTFLUSH) {} // TODO refractor later
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}while( lpc_usb->ENDPTSTAT & (BIT_(0) | BIT_(16)) );
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p_dcd->qhd[0].qtd_overlay.active = p_dcd->qhd[1].qtd_overlay.active = 0;
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}
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// if (p_dcd->qhd[0].qtd_overlay.active || p_dcd->qhd[1].qtd_overlay.active)
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// {
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// do
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// {
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// lpc_usb->ENDPTFLUSH = BIT_(0) | BIT_(16);
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// while(lpc_usb->ENDPTFLUSH) {} // TODO refractor later
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// }while( lpc_usb->ENDPTSTAT & (BIT_(0) | BIT_(16)) );
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//
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// p_dcd->qhd[0].qtd_overlay.active = p_dcd->qhd[1].qtd_overlay.active = 0;
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// }
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usbd_setup_received_isr(coreid, &control_request);
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}else if ( edpt_complete & 0x03 )
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{ // only either of Endpoint Control is set with interrupt on complete flag
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endpoint_handle_t edpt_hdl =
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{
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.coreid = coreid,
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.index = 0,
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.class_code = 0
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};
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dcd_qtd_t * const p_qtd = &p_dcd->qhd[ (edpt_complete & BIT_(0)) ? 0 : 1 ].qtd_overlay;
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tusb_event_t event = ( p_qtd->xact_err || p_qtd->halted || p_qtd->buffer_err ) ? TUSB_EVENT_XFER_ERROR : TUSB_EVENT_XFER_COMPLETE;
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usbd_xfer_isr(edpt_hdl, event, 0); // TODO xferred bytes for control xfer is not needed yet !!!!
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}
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//------------- Transfer Complete -------------//
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uint32_t edpt_complete = lpc_usb->ENDPTCOMPLETE;
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lpc_usb->ENDPTCOMPLETE = edpt_complete; // acknowledge
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if (edpt_complete)
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{
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