more multiple ports update
This commit is contained in:
hathach
parent
95b77a0e73
commit
1eefc2b3ef
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@ -63,22 +63,11 @@
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// MACRO TYPEDEF CONSTANT ENUM
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//--------------------------------------------------------------------+
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/* LINK core registers */
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#if defined(__CCRX__)
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#define RUSB2 ((rusb2_reg_t __evenaccess*) RUSB2_REG_BASE)
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#elif defined(__RX__)
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#define RUSB2 ((rusb2_reg_t*) RUSB2_REG_BASE)
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#elif (CFG_TUSB_RHPORT1_MODE & OPT_MODE_DEVICE)
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#define RUSB2 ((R_USB_HS0_Type*)R_USB_HS0_BASE)
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#else
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#define RUSB2 ((R_USB_FS0_Type*)R_USB_FS0_BASE)
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#endif
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/* Start of definition of packed structs (used by the CCRX toolchain) */
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TU_ATTR_PACKED_BEGIN
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TU_ATTR_BIT_FIELD_ORDER_BEGIN
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typedef struct TU_ATTR_PACKED {
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typedef struct TU_ATTR_PACKED _ccrx_evenaccess {
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union {
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struct {
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uint16_t : 8;
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@ -186,52 +175,53 @@ static unsigned find_pipe(unsigned xfer)
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return 0;
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}
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static volatile uint16_t* get_pipectr(unsigned num)
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static volatile uint16_t* get_pipectr(rusb2_reg_t *rusb, unsigned num)
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{
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if (num) {
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return (volatile uint16_t*)&(RUSB2->PIPE_CTR[num - 1]);
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return (volatile uint16_t*)&(rusb->PIPE_CTR[num - 1]);
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} else {
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return (volatile uint16_t*)&(RUSB2->DCPCTR);
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return (volatile uint16_t*)&(rusb->DCPCTR);
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}
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}
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static volatile reg_pipetre_t* get_pipetre(unsigned num)
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static volatile reg_pipetre_t* get_pipetre(rusb2_reg_t *rusb, unsigned num)
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{
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volatile reg_pipetre_t* tre = NULL;
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if ((1 <= num) && (num <= 5)) {
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tre = (volatile reg_pipetre_t*)&(RUSB2->PIPE_TR[num - 1].E);
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tre = (volatile reg_pipetre_t*)&(rusb->PIPE_TR[num - 1].E);
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}
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return tre;
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}
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static volatile uint16_t* ep_addr_to_pipectr(uint8_t rhport, unsigned ep_addr)
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{
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(void)rhport;
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rusb2_reg_t *rusb = RUSB2_REG(rhport);
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const unsigned epn = tu_edpt_number(ep_addr);
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if (epn) {
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const unsigned dir = tu_edpt_dir(ep_addr);
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const unsigned num = _dcd.ep[dir][epn];
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return get_pipectr(num);
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return get_pipectr(rusb, num);
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} else {
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return get_pipectr(0);
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return get_pipectr(rusb, 0);
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}
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}
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static unsigned edpt0_max_packet_size(void)
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static uint16_t edpt0_max_packet_size(rusb2_reg_t* rusb)
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{
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return RUSB2->DCPMAXP_b.MXPS;
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return rusb->DCPMAXP_b.MXPS;
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}
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static unsigned edpt_max_packet_size(unsigned num)
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static uint16_t edpt_max_packet_size(rusb2_reg_t *rusb, unsigned num)
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{
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RUSB2->PIPESEL = num;
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return RUSB2->PIPEMAXP;
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rusb->PIPESEL = num;
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return rusb->PIPEMAXP;
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}
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static inline void pipe_wait_for_ready(unsigned num)
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static inline void pipe_wait_for_ready(rusb2_reg_t * rusb, unsigned num)
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{
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while (RUSB2->D0FIFOSEL_b.CURPIPE != num) ;
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while (!RUSB2->D0FIFOCTR_b.FRDY) ;
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while ( rusb->D0FIFOSEL_b.CURPIPE != num ) {}
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while ( !rusb->D0FIFOCTR_b.FRDY ) {}
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}
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static void pipe_write_packet(void *buf, volatile void *fifo, unsigned len)
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@ -284,61 +274,70 @@ static void pipe_read_write_packet_ff(tu_fifo_t *f, volatile void *fifo, unsigne
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ops[dir].tu_fifo_advance(f, total_len - rem);
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}
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static bool pipe0_xfer_in(void)
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static bool pipe0_xfer_in(rusb2_reg_t* rusb)
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{
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pipe_state_t *pipe = &_dcd.pipe[0];
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const unsigned rem = pipe->remaining;
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if (!rem) {
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pipe->buf = NULL;
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return true;
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}
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const unsigned mps = edpt0_max_packet_size();
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const unsigned len = TU_MIN(mps, rem);
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const uint16_t mps = edpt0_max_packet_size(rusb);
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const uint16_t len = tu_min16(mps, rem);
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void *buf = pipe->buf;
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if (len) {
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if (pipe->ff) {
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pipe_read_write_packet_ff((tu_fifo_t*)buf, (volatile void*)&RUSB2->CFIFO, len, TUSB_DIR_IN);
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pipe_read_write_packet_ff((tu_fifo_t*)buf, (volatile void*)&rusb->CFIFO, len, TUSB_DIR_IN);
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} else {
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pipe_write_packet(buf, (volatile void*)&RUSB2->CFIFO, len);
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pipe_write_packet(buf, (volatile void*)&rusb->CFIFO, len);
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pipe->buf = (uint8_t*)buf + len;
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}
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}
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if (len < mps) {
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RUSB2->CFIFOCTR = RUSB2_CFIFOCTR_BVAL_Msk;
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rusb->CFIFOCTR = RUSB2_CFIFOCTR_BVAL_Msk;
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}
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pipe->remaining = rem - len;
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return false;
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}
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static bool pipe0_xfer_out(void)
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static bool pipe0_xfer_out(rusb2_reg_t* rusb)
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{
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pipe_state_t *pipe = &_dcd.pipe[0];
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const unsigned rem = pipe->remaining;
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const unsigned mps = edpt0_max_packet_size();
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const unsigned vld = RUSB2->CFIFOCTR_b.DTLN;
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const unsigned len = TU_MIN(TU_MIN(rem, mps), vld);
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const uint16_t mps = edpt0_max_packet_size(rusb);
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const uint16_t vld = rusb->CFIFOCTR_b.DTLN;
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const uint16_t len = tu_min16(tu_min16(rem, mps), vld);
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void *buf = pipe->buf;
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if (len) {
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if (pipe->ff) {
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pipe_read_write_packet_ff((tu_fifo_t*)buf, (volatile void*)&RUSB2->CFIFO, len, TUSB_DIR_OUT);
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pipe_read_write_packet_ff((tu_fifo_t*)buf, (volatile void*)&rusb->CFIFO, len, TUSB_DIR_OUT);
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} else {
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pipe_read_packet(buf, (volatile void*)&RUSB2->CFIFO, len);
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pipe_read_packet(buf, (volatile void*)&rusb->CFIFO, len);
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pipe->buf = (uint8_t*)buf + len;
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}
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}
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if (len < mps) {
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RUSB2->CFIFOCTR = RUSB2_CFIFOCTR_BCLR_Msk;
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rusb->CFIFOCTR = RUSB2_CFIFOCTR_BCLR_Msk;
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}
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pipe->remaining = rem - len;
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if ((len < mps) || (rem == len)) {
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pipe->buf = NULL;
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return true;
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}
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return false;
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}
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static bool pipe_xfer_in(unsigned num)
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static bool pipe_xfer_in(rusb2_reg_t* rusb, unsigned num)
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{
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pipe_state_t *pipe = &_dcd.pipe[num];
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const unsigned rem = pipe->remaining;
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@ -348,119 +347,141 @@ static bool pipe_xfer_in(unsigned num)
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return true;
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}
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RUSB2->D0FIFOSEL = num | RUSB2_FIFOSEL_MBW_16BIT | (TU_BYTE_ORDER == TU_BIG_ENDIAN ? RUSB2_FIFOSEL_BIGEND : 0);
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const unsigned mps = edpt_max_packet_size(num);
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pipe_wait_for_ready(num);
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const unsigned len = TU_MIN(rem, mps);
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rusb->D0FIFOSEL = num | RUSB2_FIFOSEL_MBW_16BIT | (TU_BYTE_ORDER == TU_BIG_ENDIAN ? RUSB2_FIFOSEL_BIGEND : 0);
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const uint16_t mps = edpt_max_packet_size(rusb, num);
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pipe_wait_for_ready(rusb, num);
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const uint16_t len = tu_min16(rem, mps);
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void *buf = pipe->buf;
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if (len) {
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if (pipe->ff) {
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pipe_read_write_packet_ff((tu_fifo_t*)buf, (volatile void*)&RUSB2->D0FIFO, len, TUSB_DIR_IN);
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pipe_read_write_packet_ff((tu_fifo_t*)buf, (volatile void*)&rusb->D0FIFO, len, TUSB_DIR_IN);
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} else {
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pipe_write_packet(buf, (volatile void*)&RUSB2->D0FIFO, len);
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pipe_write_packet(buf, (volatile void*)&rusb->D0FIFO, len);
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pipe->buf = (uint8_t*)buf + len;
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}
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}
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if (len < mps) {
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RUSB2->D0FIFOCTR = RUSB2_CFIFOCTR_BVAL_Msk;
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rusb->D0FIFOCTR = RUSB2_CFIFOCTR_BVAL_Msk;
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}
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RUSB2->D0FIFOSEL = 0;
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while (RUSB2->D0FIFOSEL_b.CURPIPE) {} /* if CURPIPE bits changes, check written value */
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rusb->D0FIFOSEL = 0;
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while (rusb->D0FIFOSEL_b.CURPIPE) {} /* if CURPIPE bits changes, check written value */
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pipe->remaining = rem - len;
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return false;
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}
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static bool pipe_xfer_out(unsigned num)
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static bool pipe_xfer_out(rusb2_reg_t* rusb, unsigned num)
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{
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pipe_state_t *pipe = &_dcd.pipe[num];
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const unsigned rem = pipe->remaining;
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const uint16_t rem = pipe->remaining;
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RUSB2->D0FIFOSEL = num | RUSB2_FIFOSEL_MBW_8BIT;
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const unsigned mps = edpt_max_packet_size(num);
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pipe_wait_for_ready(num);
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const unsigned vld = RUSB2->D0FIFOCTR_b.DTLN;
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const unsigned len = TU_MIN(TU_MIN(rem, mps), vld);
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rusb->D0FIFOSEL = num | RUSB2_FIFOSEL_MBW_8BIT;
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const uint16_t mps = edpt_max_packet_size(rusb, num);
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pipe_wait_for_ready(rusb, num);
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const uint16_t vld = rusb->D0FIFOCTR_b.DTLN;
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const uint16_t len = tu_min16(tu_min16(rem, mps), vld);
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void *buf = pipe->buf;
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if (len) {
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if (pipe->ff) {
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pipe_read_write_packet_ff((tu_fifo_t*)buf, (volatile void*)&RUSB2->D0FIFO, len, TUSB_DIR_OUT);
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pipe_read_write_packet_ff((tu_fifo_t*)buf, (volatile void*)&rusb->D0FIFO, len, TUSB_DIR_OUT);
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} else {
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pipe_read_packet(buf, (volatile void*)&RUSB2->D0FIFO, len);
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pipe_read_packet(buf, (volatile void*)&rusb->D0FIFO, len);
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pipe->buf = (uint8_t*)buf + len;
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}
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}
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if (len < mps) {
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RUSB2->D0FIFOCTR = RUSB2_CFIFOCTR_BCLR_Msk;
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rusb->D0FIFOCTR = RUSB2_CFIFOCTR_BCLR_Msk;
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}
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RUSB2->D0FIFOSEL = 0;
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while (RUSB2->D0FIFOSEL_b.CURPIPE) {} /* if CURPIPE bits changes, check written value */
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rusb->D0FIFOSEL = 0;
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while (rusb->D0FIFOSEL_b.CURPIPE) {} /* if CURPIPE bits changes, check written value */
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pipe->remaining = rem - len;
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if ((len < mps) || (rem == len)) {
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pipe->buf = NULL;
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return NULL != buf;
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}
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return false;
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}
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static void process_setup_packet(uint8_t rhport)
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{
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uint16_t setup_packet[4];
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if (0 == (RUSB2->INTSTS0 & RUSB2_INTSTS0_VALID_Msk)) return;
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RUSB2->CFIFOCTR = RUSB2_CFIFOCTR_BCLR_Msk;
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setup_packet[0] = tu_le16toh(RUSB2->USBREQ);
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setup_packet[1] = RUSB2->USBVAL;
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setup_packet[2] = RUSB2->USBINDX;
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setup_packet[3] = RUSB2->USBLENG;
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RUSB2->INTSTS0 = ~((uint16_t)RUSB2_INTSTS0_VALID_Msk);
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rusb2_reg_t* rusb = RUSB2_REG(rhport);
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if (0 == (rusb->INTSTS0 & RUSB2_INTSTS0_VALID_Msk)) return;
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rusb->CFIFOCTR = RUSB2_CFIFOCTR_BCLR_Msk;
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uint16_t setup_packet[4] = {
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tu_htole16(rusb->USBREQ),
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tu_htole16(rusb->USBVAL),
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tu_htole16(rusb->USBINDX),
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tu_htole16(rusb->USBLENG)
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};
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rusb->INTSTS0 = ~((uint16_t) RUSB2_INTSTS0_VALID_Msk);
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dcd_event_setup_received(rhport, (const uint8_t*)&setup_packet[0], true);
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}
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static void process_status_completion(uint8_t rhport)
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{
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rusb2_reg_t* rusb = RUSB2_REG(rhport);
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uint8_t ep_addr;
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/* Check the data stage direction */
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if (RUSB2->CFIFOSEL & RUSB2_CFIFOSEL_ISEL_WRITE) {
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if (rusb->CFIFOSEL & RUSB2_CFIFOSEL_ISEL_WRITE) {
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/* IN transfer. */
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ep_addr = tu_edpt_addr(0, TUSB_DIR_IN);
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} else {
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/* OUT transfer. */
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ep_addr = tu_edpt_addr(0, TUSB_DIR_OUT);
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}
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dcd_event_xfer_complete(rhport, ep_addr, 0, XFER_RESULT_SUCCESS, true);
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}
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static bool process_pipe0_xfer(int buffer_type, uint8_t ep_addr, void* buffer, uint16_t total_bytes)
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static bool process_pipe0_xfer(rusb2_reg_t* rusb, int buffer_type, uint8_t ep_addr, void* buffer, uint16_t total_bytes)
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{
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/* configure fifo direction and access unit settings */
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if (ep_addr) { /* IN, 2 bytes */
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RUSB2->CFIFOSEL = RUSB2_CFIFOSEL_ISEL_WRITE | RUSB2_FIFOSEL_MBW_16BIT |
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(TU_BYTE_ORDER == TU_BIG_ENDIAN ? RUSB2_FIFOSEL_BIGEND : 0);
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while (!(RUSB2->CFIFOSEL & RUSB2_CFIFOSEL_ISEL_WRITE)) ;
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} else { /* OUT, a byte */
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RUSB2->CFIFOSEL = RUSB2_FIFOSEL_MBW_8BIT;
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while (RUSB2->CFIFOSEL & RUSB2_CFIFOSEL_ISEL_WRITE) ;
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if ( ep_addr ) {
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/* IN, 2 bytes */
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rusb->CFIFOSEL = RUSB2_CFIFOSEL_ISEL_WRITE | RUSB2_FIFOSEL_MBW_16BIT |
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(TU_BYTE_ORDER == TU_BIG_ENDIAN ? RUSB2_FIFOSEL_BIGEND : 0);
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while ( !(rusb->CFIFOSEL & RUSB2_CFIFOSEL_ISEL_WRITE) ) {}
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} else {
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/* OUT, a byte */
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rusb->CFIFOSEL = RUSB2_FIFOSEL_MBW_8BIT;
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while ( rusb->CFIFOSEL & RUSB2_CFIFOSEL_ISEL_WRITE ) {}
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}
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pipe_state_t *pipe = &_dcd.pipe[0];
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pipe->ff = buffer_type;
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pipe->length = total_bytes;
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pipe->remaining = total_bytes;
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if (total_bytes) {
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pipe->buf = buffer;
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if (ep_addr) { /* IN */
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TU_ASSERT(RUSB2->DCPCTR_b.BSTS && (RUSB2->USBREQ & 0x80));
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pipe0_xfer_in();
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if ( total_bytes ) {
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pipe->buf = buffer;
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if ( ep_addr ) {
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/* IN */
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TU_ASSERT(rusb->DCPCTR_b.BSTS && (rusb->USBREQ & 0x80));
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pipe0_xfer_in(rusb);
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}
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RUSB2->DCPCTR = RUSB2_PIPE_CTR_PID_BUF;
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rusb->DCPCTR = RUSB2_PIPE_CTR_PID_BUF;
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} else {
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/* ZLP */
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pipe->buf = NULL;
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RUSB2->DCPCTR = RUSB2_DCPCTR_CCPL_Msk | RUSB2_PIPE_CTR_PID_BUF;
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pipe->buf = NULL;
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rusb->DCPCTR = RUSB2_DCPCTR_CCPL_Msk | RUSB2_PIPE_CTR_PID_BUF;
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}
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return true;
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}
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static bool process_pipe_xfer(int buffer_type, uint8_t ep_addr, void* buffer, uint16_t total_bytes)
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static bool process_pipe_xfer(rusb2_reg_t* rusb, int buffer_type, uint8_t ep_addr, void* buffer, uint16_t total_bytes)
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{
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const unsigned epn = tu_edpt_number(ep_addr);
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const unsigned dir = tu_edpt_dir(ep_addr);
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@ -473,49 +494,55 @@ static bool process_pipe_xfer(int buffer_type, uint8_t ep_addr, void* buffer, ui
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pipe->buf = buffer;
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pipe->length = total_bytes;
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pipe->remaining = total_bytes;
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if (dir) { /* IN */
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if (dir) {
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/* IN */
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if (total_bytes) {
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pipe_xfer_in(num);
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} else { /* ZLP */
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RUSB2->D0FIFOSEL = num;
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pipe_wait_for_ready(num);
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RUSB2->D0FIFOCTR = RUSB2_CFIFOCTR_BVAL_Msk;
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RUSB2->D0FIFOSEL = 0;
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while (RUSB2->D0FIFOSEL_b.CURPIPE) ; /* if CURPIPE bits changes, check written value */
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pipe_xfer_in(rusb, num);
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} else {
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/* ZLP */
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rusb->D0FIFOSEL = num;
|
||||
pipe_wait_for_ready(rusb, num);
|
||||
rusb->D0FIFOCTR = RUSB2_CFIFOCTR_BVAL_Msk;
|
||||
rusb->D0FIFOSEL = 0;
|
||||
/* if CURPIPE bits changes, check written value */
|
||||
while (rusb->D0FIFOSEL_b.CURPIPE) {}
|
||||
}
|
||||
} else {
|
||||
#if defined(__CCRX__)
|
||||
__evenaccess volatile reg_pipetre_t *pt = get_pipetre(num);
|
||||
#else
|
||||
volatile reg_pipetre_t *pt = get_pipetre(num);
|
||||
#endif
|
||||
// OUT
|
||||
volatile reg_pipetre_t *pt = get_pipetre(rusb, num);
|
||||
|
||||
if (pt) {
|
||||
const unsigned mps = edpt_max_packet_size(num);
|
||||
volatile uint16_t *ctr = get_pipectr(num);
|
||||
const uint16_t mps = edpt_max_packet_size(rusb, num);
|
||||
volatile uint16_t *ctr = get_pipectr(rusb, num);
|
||||
|
||||
if (*ctr & 0x3) *ctr = RUSB2_PIPE_CTR_PID_NAK;
|
||||
|
||||
pt->TRE = TU_BIT(8);
|
||||
pt->TRN = (total_bytes + mps - 1) / mps;
|
||||
pt->TRENB = 1;
|
||||
*ctr = RUSB2_PIPE_CTR_PID_BUF;
|
||||
}
|
||||
}
|
||||
// TU_LOG1("X %x %d %d\r\n", ep_addr, total_bytes, buffer_type);
|
||||
|
||||
// TU_LOG2("X %x %d %d\r\n", ep_addr, total_bytes, buffer_type);
|
||||
return true;
|
||||
}
|
||||
|
||||
static bool process_edpt_xfer(int buffer_type, uint8_t ep_addr, void* buffer, uint16_t total_bytes)
|
||||
static bool process_edpt_xfer(rusb2_reg_t* rusb, int buffer_type, uint8_t ep_addr, void* buffer, uint16_t total_bytes)
|
||||
{
|
||||
const unsigned epn = tu_edpt_number(ep_addr);
|
||||
if (0 == epn) {
|
||||
return process_pipe0_xfer(buffer_type, ep_addr, buffer, total_bytes);
|
||||
return process_pipe0_xfer(rusb, buffer_type, ep_addr, buffer, total_bytes);
|
||||
} else {
|
||||
return process_pipe_xfer(buffer_type, ep_addr, buffer, total_bytes);
|
||||
return process_pipe_xfer(rusb, buffer_type, ep_addr, buffer, total_bytes);
|
||||
}
|
||||
}
|
||||
|
||||
static void process_pipe0_bemp(uint8_t rhport)
|
||||
{
|
||||
bool completed = pipe0_xfer_in();
|
||||
rusb2_reg_t* rusb = RUSB2_REG(rhport);
|
||||
bool completed = pipe0_xfer_in(rusb);
|
||||
if (completed) {
|
||||
pipe_state_t *pipe = &_dcd.pipe[0];
|
||||
dcd_event_xfer_complete(rhport, tu_edpt_addr(0, TUSB_DIR_IN),
|
||||
|
|
@ -525,17 +552,20 @@ static void process_pipe0_bemp(uint8_t rhport)
|
|||
|
||||
static void process_pipe_brdy(uint8_t rhport, unsigned num)
|
||||
{
|
||||
rusb2_reg_t* rusb = RUSB2_REG(rhport);
|
||||
pipe_state_t *pipe = &_dcd.pipe[num];
|
||||
const unsigned dir = tu_edpt_dir(pipe->ep);
|
||||
bool completed;
|
||||
|
||||
if (dir) { /* IN */
|
||||
completed = pipe_xfer_in(num);
|
||||
if (dir) {
|
||||
/* IN */
|
||||
completed = pipe_xfer_in(rusb, num);
|
||||
} else {
|
||||
// OUT
|
||||
if (num) {
|
||||
completed = pipe_xfer_out(num);
|
||||
completed = pipe_xfer_out(rusb, num);
|
||||
} else {
|
||||
completed = pipe0_xfer_out();
|
||||
completed = pipe0_xfer_out(rusb);
|
||||
}
|
||||
}
|
||||
if (completed) {
|
||||
|
|
@ -606,8 +636,10 @@ static void process_bus_reset(uint8_t rhport)
|
|||
|
||||
static void process_set_address(uint8_t rhport)
|
||||
{
|
||||
const uint32_t addr = RUSB2->USBADDR & 0xFF;
|
||||
rusb2_reg_t* rusb = RUSB2_REG(rhport);
|
||||
const uint32_t addr = rusb->USBADDR & 0xFF;
|
||||
if (!addr) return;
|
||||
|
||||
const tusb_control_request_t setup_packet = {
|
||||
#if defined(__CCRX__)
|
||||
.bmRequestType = { 0 }, /* Note: CCRX needs the braces over this struct member */
|
||||
|
|
@ -618,8 +650,9 @@ static void process_set_address(uint8_t rhport)
|
|||
.wValue = addr,
|
||||
.wIndex = 0,
|
||||
.wLength = 0,
|
||||
};
|
||||
dcd_event_setup_received(rhport, (const uint8_t*)&setup_packet, true);
|
||||
};
|
||||
|
||||
dcd_event_setup_received(rhport, (const uint8_t *) &setup_packet, true);
|
||||
}
|
||||
|
||||
/*------------------------------------------------------------------*/
|
||||
|
|
@ -704,7 +737,7 @@ void dcd_init(uint8_t rhport)
|
|||
rusb->INTSTS0 = 0;
|
||||
rusb->INTENB0 = RUSB2_INTSTS0_VBINT_Msk | RUSB2_INTSTS0_BRDY_Msk | RUSB2_INTSTS0_BEMP_Msk |
|
||||
RUSB2_INTSTS0_DVST_Msk | RUSB2_INTSTS0_CTRT_Msk | (USE_SOF ? RUSB2_INTSTS0_SOFR_Msk : 0) |
|
||||
RUSB2_INTSTS0_RESM_Msk | RUSB2_INTSTS0_NRDY_Msk;
|
||||
RUSB2_INTSTS0_RESM_Msk;
|
||||
rusb->BEMPENB = 1;
|
||||
rusb->BRDYENB = 1;
|
||||
|
||||
|
|
@ -766,33 +799,43 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * ep_desc)
|
|||
{
|
||||
(void)rhport;
|
||||
|
||||
rusb2_reg_t * rusb = RUSB2_REG(rhport);
|
||||
const unsigned ep_addr = ep_desc->bEndpointAddress;
|
||||
const unsigned epn = tu_edpt_number(ep_addr);
|
||||
const unsigned dir = tu_edpt_dir(ep_addr);
|
||||
const unsigned xfer = ep_desc->bmAttributes.xfer;
|
||||
|
||||
const unsigned mps = tu_edpt_packet_size(ep_desc);
|
||||
if (xfer == TUSB_XFER_ISOCHRONOUS && mps > 256) {
|
||||
/* USBa supports up to 256 bytes */
|
||||
return false;
|
||||
|
||||
if (xfer == TUSB_XFER_ISOCHRONOUS) {
|
||||
// Fullspeed ISO is limit to 256 bytes
|
||||
if ( !is_highspeed(rhport) && mps > 256) {
|
||||
return false;
|
||||
}
|
||||
}
|
||||
|
||||
const unsigned num = find_pipe(xfer);
|
||||
if (!num) return false;
|
||||
TU_ASSERT(num);
|
||||
|
||||
_dcd.pipe[num].ep = ep_addr;
|
||||
_dcd.ep[dir][epn] = num;
|
||||
|
||||
/* setup pipe */
|
||||
dcd_int_disable(rhport);
|
||||
#if (CFG_TUSB_RHPORT1_MODE & OPT_MODE_DEVICE)
|
||||
RUSB2->PIPEBUF = 0x7C08;
|
||||
#endif
|
||||
RUSB2->PIPESEL = num;
|
||||
RUSB2->PIPEMAXP = mps;
|
||||
volatile uint16_t *ctr = get_pipectr(num);
|
||||
|
||||
if ( is_highspeed(rhport) ) {
|
||||
// FIXME shouldn't be after pipe selection and config, also the BUFNMB should be changed
|
||||
// depending on the allocation scheme
|
||||
rusb->PIPEBUF = 0x7C08;
|
||||
}
|
||||
|
||||
rusb->PIPESEL = num;
|
||||
rusb->PIPEMAXP = mps;
|
||||
volatile uint16_t *ctr = get_pipectr(rusb, num);
|
||||
*ctr = RUSB2_PIPE_CTR_ACLRM_Msk | RUSB2_PIPE_CTR_SQCLR_Msk;
|
||||
*ctr = 0;
|
||||
unsigned cfg = (dir << 4) | epn;
|
||||
|
||||
if (xfer == TUSB_XFER_BULK) {
|
||||
cfg |= (RUSB2_PIPECFG_TYPE_BULK | RUSB2_PIPECFG_SHTNAK_Msk | RUSB2_PIPECFG_DBLB_Msk);
|
||||
} else if (xfer == TUSB_XFER_INTERRUPT) {
|
||||
|
|
@ -800,13 +843,16 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * ep_desc)
|
|||
} else {
|
||||
cfg |= (RUSB2_PIPECFG_TYPE_ISO | RUSB2_PIPECFG_DBLB_Msk);
|
||||
}
|
||||
RUSB2->PIPECFG = cfg;
|
||||
RUSB2->BRDYSTS = 0x1FFu ^ TU_BIT(num);
|
||||
RUSB2->BRDYENB |= TU_BIT(num);
|
||||
|
||||
rusb->PIPECFG = cfg;
|
||||
rusb->BRDYSTS = 0x1FFu ^ TU_BIT(num);
|
||||
rusb->BRDYENB |= TU_BIT(num);
|
||||
|
||||
if (dir || (xfer != TUSB_XFER_BULK)) {
|
||||
*ctr = RUSB2_PIPE_CTR_PID_BUF;
|
||||
}
|
||||
// TU_LOG1("O %d %x %x\r\n", RUSB2->PIPESEL, RUSB2->PIPECFG, RUSB2->PIPEMAXP);
|
||||
|
||||
// TU_LOG1("O %d %x %x\r\n", rusb->PIPESEL, rusb->PIPECFG, rusb->PIPEMAXP);
|
||||
dcd_int_enable(rhport);
|
||||
|
||||
return true;
|
||||
|
|
@ -826,26 +872,28 @@ void dcd_edpt_close_all(uint8_t rhport)
|
|||
|
||||
void dcd_edpt_close(uint8_t rhport, uint8_t ep_addr)
|
||||
{
|
||||
(void)rhport;
|
||||
rusb2_reg_t * rusb = RUSB2_REG(rhport);
|
||||
const unsigned epn = tu_edpt_number(ep_addr);
|
||||
const unsigned dir = tu_edpt_dir(ep_addr);
|
||||
const unsigned num = _dcd.ep[dir][epn];
|
||||
|
||||
RUSB2->BRDYENB &= ~TU_BIT(num);
|
||||
volatile uint16_t *ctr = get_pipectr(num);
|
||||
rusb->BRDYENB &= ~TU_BIT(num);
|
||||
volatile uint16_t *ctr = get_pipectr(rusb, num);
|
||||
*ctr = 0;
|
||||
RUSB2->PIPESEL = num;
|
||||
RUSB2->PIPECFG = 0;
|
||||
rusb->PIPESEL = num;
|
||||
rusb->PIPECFG = 0;
|
||||
_dcd.pipe[num].ep = 0;
|
||||
_dcd.ep[dir][epn] = 0;
|
||||
}
|
||||
|
||||
bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t* buffer, uint16_t total_bytes)
|
||||
{
|
||||
bool r;
|
||||
rusb2_reg_t* rusb = RUSB2_REG(rhport);
|
||||
|
||||
dcd_int_disable(rhport);
|
||||
r = process_edpt_xfer(0, ep_addr, buffer, total_bytes);
|
||||
bool r = process_edpt_xfer(rusb, 0, ep_addr, buffer, total_bytes);
|
||||
dcd_int_enable(rhport);
|
||||
|
||||
return r;
|
||||
}
|
||||
|
||||
|
|
@ -853,10 +901,12 @@ bool dcd_edpt_xfer_fifo(uint8_t rhport, uint8_t ep_addr, tu_fifo_t * ff, uint16_
|
|||
{
|
||||
// USB buffers always work in bytes so to avoid unnecessary divisions we demand item_size = 1
|
||||
TU_ASSERT(ff->item_size == 1);
|
||||
bool r;
|
||||
rusb2_reg_t* rusb = RUSB2_REG(rhport);
|
||||
|
||||
dcd_int_disable(rhport);
|
||||
r = process_edpt_xfer(1, ep_addr, ff, total_bytes);
|
||||
bool r = process_edpt_xfer(rusb, 1, ep_addr, ff, total_bytes);
|
||||
dcd_int_enable(rhport);
|
||||
|
||||
return r;
|
||||
}
|
||||
|
||||
|
|
@ -873,8 +923,10 @@ void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr)
|
|||
|
||||
void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr)
|
||||
{
|
||||
rusb2_reg_t * rusb = RUSB2_REG(rhport);
|
||||
volatile uint16_t *ctr = ep_addr_to_pipectr(rhport, ep_addr);
|
||||
if (!ctr) return;
|
||||
|
||||
dcd_int_disable(rhport);
|
||||
*ctr = RUSB2_PIPE_CTR_SQCLR_Msk;
|
||||
|
||||
|
|
@ -882,8 +934,8 @@ void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr)
|
|||
*ctr = RUSB2_PIPE_CTR_PID_BUF;
|
||||
} else {
|
||||
const unsigned num = _dcd.ep[0][tu_edpt_number(ep_addr)];
|
||||
RUSB2->PIPESEL = num;
|
||||
if (RUSB2->PIPECFG_b.TYPE != 1) {
|
||||
rusb->PIPESEL = num;
|
||||
if (rusb->PIPECFG_b.TYPE != 1) {
|
||||
*ctr = RUSB2_PIPE_CTR_PID_BUF;
|
||||
}
|
||||
}
|
||||
|
|
@ -953,9 +1005,9 @@ void dcd_int_handler(uint8_t rhport)
|
|||
}
|
||||
}
|
||||
|
||||
if ( is0 & RUSB2_INTSTS0_NRDY_Msk ) {
|
||||
rusb->NRDYSTS = 0;
|
||||
}
|
||||
// if ( is0 & RUSB2_INTSTS0_NRDY_Msk ) {
|
||||
// rusb->NRDYSTS = 0;
|
||||
// }
|
||||
|
||||
// Control transfer stage changes
|
||||
if ( is0 & RUSB2_INTSTS0_CTRT_Msk ) {
|
||||
|
|
@ -970,7 +1022,7 @@ void dcd_int_handler(uint8_t rhport)
|
|||
|
||||
// Buffer empty
|
||||
if ( is0 & RUSB2_INTSTS0_BEMP_Msk ) {
|
||||
const unsigned s = rusb->BEMPSTS;
|
||||
const uint16_t s = rusb->BEMPSTS;
|
||||
rusb->BEMPSTS = 0;
|
||||
if ( s & 1 ) {
|
||||
process_pipe0_bemp(rhport);
|
||||
|
|
|
|||
|
|
@ -37,6 +37,8 @@ extern "C" {
|
|||
|
||||
#define RUSB2_REG_BASE (0x000A0000)
|
||||
|
||||
#define RUSB2_REG(_p) ((rusb2_reg_t *) RUSB2_REG_BASE)
|
||||
|
||||
// Start/Stop MSTP TODO implement later
|
||||
TU_ATTR_ALWAYS_INLINE static inline void rusb2_module_start(uint8_t rhport, bool start) {
|
||||
(void) rhport;
|
||||
|
|
|
|||
|
|
@ -33,6 +33,13 @@
|
|||
extern "C" {
|
||||
#endif
|
||||
|
||||
// CCRX specific attribute to generate a Code that Accesses Variables in the Declared Size
|
||||
#ifdef __CCRX__
|
||||
#define _ccrx_evenaccess __evenaccess
|
||||
#else
|
||||
#define _ccrx_evenaccess
|
||||
#endif
|
||||
|
||||
/*--------------------------------------------------------------------*/
|
||||
/* Register Definitions */
|
||||
/*--------------------------------------------------------------------*/
|
||||
|
|
@ -64,7 +71,7 @@ typedef struct {
|
|||
|
||||
|
||||
/* RUSB2 Registers Structure */
|
||||
typedef struct {
|
||||
typedef struct _ccrx_evenaccess {
|
||||
union {
|
||||
volatile uint16_t SYSCFG; /* (@ 0x00000000) System Configuration Control Register */
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue