- Add Full Speed switch
- Add DMA support - Add Dual bank support Signed-off-by: HiFiPhile <admin@hifiphile.com>
This commit is contained in:
HiFiPhile
MasterPhi
parent
4f4a33b378
commit
1dafcd1132
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@ -34,7 +34,6 @@
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#include "device/dcd.h"
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#include "sam.h"
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//--------------------------------------------------------------------+
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// MACRO TYPEDEF CONSTANT ENUM DECLARATION
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//--------------------------------------------------------------------+
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@ -42,17 +41,29 @@
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// Since TinyUSB doesn't use SOF for now, and this interrupt too often (1ms interval)
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// We disable SOF for now until needed later on
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#ifndef USE_SOF
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# define USE_SOF 0
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# define USE_SOF 0
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#endif
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#ifndef USBHS_RAM_ADDR
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# define USBHS_RAM_ADDR 0xA0100000u
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// Dual bank can imporve performance, but need 2 times bigger packet buffer
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// As SAME70 has only 4KB packet buffer, use with caution !
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// Enable in FS mode as packets are smaller
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#ifndef USE_DUAL_BANK
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# if TUD_OPT_HIGH_SPEED
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# define USE_DUAL_BANK 0
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# else
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# define USE_DUAL_BANK 1
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# endif
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#endif
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#define get_ep_fifo_ptr(ep, scale) (((TU_XSTRCAT(TU_STRCAT(uint, scale),_t) (*)[0x8000 / ((scale) / 8)])USBHS_RAM_ADDR)[(ep)])
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#define EP_MAX 10
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#define USBHS_RAM_ADDR 0xA0100000u
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#define EP_GET_FIFO_PTR(ep, scale) (((TU_XSTRCAT(TU_STRCAT(uint, scale),_t) (*)[0x8000 / ((scale) / 8)])USBHS_RAM_ADDR)[(ep)])
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// Errata: The DMA feature is not available for Pipe/Endpoint 7
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#define EP_DMA_SUPPORT(epnum) (epnum >= 1 && epnum <= 6)
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typedef struct {
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uint8_t * buffer;
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uint16_t total_len;
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@ -82,9 +93,12 @@ void dcd_init (uint8_t rhport)
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PMC->CKGR_UCKR = CKGR_UCKR_UPLLEN | CKGR_UCKR_UPLLCOUNT(0x3fU);
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// Wait until USB UTMI stabilize
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while (!(PMC->PMC_SR & PMC_SR_LOCKU));
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#if !TUD_OPT_HIGH_SPEED
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// Enable USB FS clk
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PMC->PMC_MCKR &= ~PMC_MCKR_UPLLDIV2;
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PMC->PMC_USB = PMC_USB_USBS | PMC_USB_USBDIV(10 - 1);
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PMC->PMC_SCER = PMC_SCER_USBCLK;
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#endif
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dcd_connect(rhport);
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}
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@ -128,10 +142,12 @@ void dcd_connect(uint8_t rhport)
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PMC->PMC_PCER1 = 1 << (ID_USBHS - 32);
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// Enable the USB controller in device mode
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USBHS->USBHS_CTRL = USBHS_CTRL_UIMOD | USBHS_CTRL_USBE;
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// Wait to unfreeze clock
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while(USBHS_SR_CLKUSABLE != (USBHS->USBHS_SR & USBHS_SR_CLKUSABLE));
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// Attach the device
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USBHS->USBHS_DEVCTRL &= ~USBHS_DEVCTRL_DETACH;
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while (USBHS_SR_CLKUSABLE != (USBHS->USBHS_SR & USBHS_SR_CLKUSABLE));
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#if TUD_OPT_HIGH_SPEED
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USBHS->USBHS_DEVCTRL &= ~USBHS_DEVCTRL_SPDCONF_Msk;
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#else
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USBHS->USBHS_DEVCTRL |= USBHS_DEVCTRL_SPDCONF_LOW_POWER;
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#endif
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// Enable the End Of Reset, Suspend & Wakeup interrupts
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USBHS->USBHS_DEVIER = (USBHS_DEVIER_EORSTES | USBHS_DEVIER_SUSPES | USBHS_DEVIER_WAKEUPES);
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#if USE_SOF
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@ -143,6 +159,8 @@ void dcd_connect(uint8_t rhport)
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USBHS->USBHS_DEVIFR |= USBHS_DEVIFR_SUSPS;
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// Ack the Wakeup Interrupt
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USBHS->USBHS_DEVICR = USBHS_DEVICR_WAKEUPC;
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// Attach the device
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USBHS->USBHS_DEVCTRL &= ~USBHS_DEVCTRL_DETACH;
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// Freeze USB clock
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USBHS->USBHS_CTRL |= USBHS_CTRL_FRZCLK;
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__set_PRIMASK(irq_state);
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@ -158,7 +176,6 @@ void dcd_disconnect(uint8_t rhport)
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USBHS->USBHS_DEVEPT &= ~(0x3FF << USBHS_DEVEPT_EPEN0_Pos);
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// Unfreeze USB clock
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USBHS->USBHS_CTRL &= ~USBHS_CTRL_FRZCLK;
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// Wait to unfreeze clock
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while (USBHS_SR_CLKUSABLE != (USBHS->USBHS_SR & USBHS_SR_CLKUSABLE));
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// Clear all the pending interrupts
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USBHS->USBHS_DEVICR = USBHS_DEVICR_Msk;
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@ -195,7 +212,7 @@ static void dcd_ep_handler(uint8_t ep_ix)
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// Setup packet should always be 8 bytes. If not, ignore it, and try again.
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if (count == 8)
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{
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uint8_t *ptr = get_ep_fifo_ptr(0,8);
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uint8_t *ptr = EP_GET_FIFO_PTR(0,8);
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dcd_event_setup_received(0, ptr, true);
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}
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// Acknowledge the interrupt
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@ -204,7 +221,7 @@ static void dcd_ep_handler(uint8_t ep_ix)
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if (int_status & USBHS_DEVEPTISR_RXOUTI) {
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xfer_ctl_t *xfer = &xfer_status[0];
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if (count) {
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uint8_t *ptr = get_ep_fifo_ptr(0,8);
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uint8_t *ptr = EP_GET_FIFO_PTR(0,8);
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for (int i = 0; i < count; i++) {
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xfer->buffer[xfer->queued_len + i] = ptr[i];
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}
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@ -230,7 +247,7 @@ static void dcd_ep_handler(uint8_t ep_ix)
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}
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else {
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// TX complete
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dcd_event_xfer_complete(0, (uint8_t)(0x80 + 0), xfer->total_len, XFER_RESULT_SUCCESS, true);
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dcd_event_xfer_complete(0, 0x80 + 0, xfer->total_len, XFER_RESULT_SUCCESS, true);
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}
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}
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}
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@ -238,7 +255,7 @@ static void dcd_ep_handler(uint8_t ep_ix)
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if (int_status & USBHS_DEVEPTISR_RXOUTI) {
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xfer_ctl_t *xfer = &xfer_status[ep_ix];
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if (count) {
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uint8_t *ptr = get_ep_fifo_ptr(ep_ix,8);
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uint8_t *ptr = EP_GET_FIFO_PTR(ep_ix,8);
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memcpy(xfer->buffer + xfer->queued_len, ptr, count);
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xfer->queued_len = (uint16_t)(xfer->queued_len + count);
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}
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@ -264,12 +281,34 @@ static void dcd_ep_handler(uint8_t ep_ix)
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}
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else {
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// TX complete
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dcd_event_xfer_complete(0, (uint8_t)(0x80 + ep_ix), xfer->total_len, XFER_RESULT_SUCCESS, true);
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dcd_event_xfer_complete(0, 0x80 + ep_ix, xfer->total_len, XFER_RESULT_SUCCESS, true);
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USBHS->USBHS_DEVEPTIDR[ep_ix] = USBHS_DEVEPTIDR_TXINEC;
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}
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}
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}
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}
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static void dcd_dma_handler(uint8_t ep_ix)
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{
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uint32_t status = USBHS->UsbhsDevdma[ep_ix - 1].USBHS_DEVDMASTATUS;
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if (status & USBHS_DEVDMASTATUS_CHANN_ENB) {
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return; // Ignore EOT_STA interrupt
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}
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// Disable DMA interrupt
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USBHS->USBHS_DEVIDR = USBHS_DEVIDR_DMA_1 << (ep_ix - 1);
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xfer_ctl_t *xfer = &xfer_status[ep_ix];
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uint16_t count = xfer->total_len - ((status & USBHS_DEVDMASTATUS_BUFF_COUNT_Msk) >> USBHS_DEVDMASTATUS_BUFF_COUNT_Pos);
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if(USBHS->USBHS_DEVEPTCFG[ep_ix] & USBHS_DEVEPTCFG_EPDIR)
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{
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dcd_event_xfer_complete(0, 0x80 + ep_ix, count, XFER_RESULT_SUCCESS, true);
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}
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else
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{
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dcd_event_xfer_complete(0, ep_ix, count, XFER_RESULT_SUCCESS, true);
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}
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}
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void dcd_int_handler(uint8_t rhport)
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{
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(void) rhport;
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@ -337,10 +376,18 @@ void dcd_int_handler(uint8_t rhport)
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#endif
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// Endpoints interrupt
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for (int ep_ix = 0; ep_ix < EP_MAX; ep_ix++) {
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if (int_status & (1 << (USBHS_DEVISR_PEP_0_Pos + ep_ix))) {
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if (int_status & (USBHS_DEVISR_PEP_0 << ep_ix)) {
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dcd_ep_handler(ep_ix);
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}
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}
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// Endpoints DMA interrupt
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for (int ep_ix = 0; ep_ix < EP_MAX; ep_ix++) {
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if (EP_DMA_SUPPORT(ep_ix)) {
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if (int_status & (USBHS_DEVISR_DMA_1 << (ep_ix - 1))) {
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dcd_dma_handler(ep_ix);
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}
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}
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}
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}
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//--------------------------------------------------------------------+
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@ -415,26 +462,27 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * ep_desc)
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USBHS->USBHS_DEVEPT |= ((0x01 << epnum) << USBHS_DEVEPT_EPEN0_Pos);
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// Set up the maxpacket size, fifo start address fifosize
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// and enable the interrupt. CLear the data toggle.
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// AUTOSW is needed for DMA ack !
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USBHS->USBHS_DEVEPTCFG[epnum] =
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(
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USBHS_DEVEPTCFG_EPSIZE(fifoSize) |
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USBHS_DEVEPTCFG_EPTYPE(eptype) |
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USBHS_DEVEPTCFG_EPBK(USBHS_DEVEPTCFG_EPBK_1_BANK) |
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USBHS_DEVEPTCFG_AUTOSW |
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((dir & 0x01) << USBHS_DEVEPTCFG_EPDIR_Pos)
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);
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if (eptype == TUSB_XFER_ISOCHRONOUS){
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USBHS->USBHS_DEVEPTCFG[epnum] |= USBHS_DEVEPTCFG_NBTRANS(1) | USBHS_DEVEPTCFG_EPBK_2_BANK;
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USBHS->USBHS_DEVEPTCFG[epnum] |= USBHS_DEVEPTCFG_NBTRANS(1);
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}
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#if USE_DUAL_BANK
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if (eptype == TUSB_XFER_ISOCHRONOUS || eptype == TUSB_XFER_BULK){
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USBHS->USBHS_DEVEPTCFG[epnum] |= USBHS_DEVEPTCFG_EPBK_2_BANK;
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}
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#endif
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USBHS->USBHS_DEVEPTCFG[epnum] |= USBHS_DEVEPTCFG_ALLOC;
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USBHS->USBHS_DEVEPTIER[epnum] = USBHS_DEVEPTIER_RSTDTS;
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USBHS->USBHS_DEVEPTIDR[epnum] = USBHS_DEVEPTIDR_STALLRQC;
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if (USBHS_DEVEPTISR_CFGOK == (USBHS->USBHS_DEVEPTISR[epnum] & USBHS_DEVEPTISR_CFGOK)) {
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// Endpoint configuration is successful. Enable Endpoint Interrupts
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if (dir == TUSB_DIR_IN) {
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USBHS->USBHS_DEVEPTICR[epnum] = USBHS_DEVEPTICR_TXINIC;
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USBHS->USBHS_DEVEPTIER[epnum] = USBHS_DEVEPTIER_TXINES;
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}
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USBHS->USBHS_DEVIER = ((0x01 << epnum) << USBHS_DEVIER_PEP_0_Pos);
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return true;
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}
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@ -453,28 +501,26 @@ static void dcd_transmit_packet(xfer_ctl_t * xfer, uint8_t ep_ix)
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len = xfer->max_packet_size;
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}
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uint8_t *ptr = get_ep_fifo_ptr(ep_ix,8);
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uint8_t *ptr = EP_GET_FIFO_PTR(ep_ix,8);
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memcpy(ptr, xfer->buffer + xfer->queued_len, len);
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xfer->queued_len = (uint16_t)(xfer->queued_len + len);
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if (ep_ix == 0U) {
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// Control endpoint: clear the interrupt flag to send the data,
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// and re-enable the interrupts to trigger an interrupt at the
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// end of the transfer.
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// Control endpoint: clear the interrupt flag to send the data
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USBHS->USBHS_DEVEPTICR[0] = USBHS_DEVEPTICR_TXINIC;
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USBHS->USBHS_DEVEPTIER[0] = USBHS_DEVEPTIER_TXINES;
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} else {
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// Other endpoint types: clear the FIFO control flag to send the data.
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// Other endpoint types: clear the FIFO control flag to send the data
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USBHS->USBHS_DEVEPTIDR[ep_ix] = USBHS_DEVEPTIDR_FIFOCONC;
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}
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USBHS->USBHS_DEVEPTIER[ep_ix] = USBHS_DEVEPTIER_TXINES;
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}
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// Submit a transfer, When complete dcd_event_xfer_complete() is invoked to notify the stack
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bool dcd_edpt_xfer (uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t total_bytes)
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{
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(void) rhport;
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uint8_t const epnum = tu_edpt_number(ep_addr);
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uint8_t const dir = tu_edpt_dir(ep_addr);
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@ -486,11 +532,42 @@ bool dcd_edpt_xfer (uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t
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xfer->total_len = total_bytes;
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xfer->queued_len = 0;
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if (dir == TUSB_DIR_OUT){
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USBHS->USBHS_DEVEPTIER[epnum] = USBHS_DEVEPTIER_RXOUTES;
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if(EP_DMA_SUPPORT(epnum) && total_bytes != 0) {
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uint32_t udd_dma_ctrl = 0;
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udd_dma_ctrl = USBHS_DEVDMACONTROL_BUFF_LENGTH(total_bytes);
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if (dir == TUSB_DIR_OUT){
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udd_dma_ctrl |= USBHS_DEVDMACONTROL_END_TR_IT | USBHS_DEVDMACONTROL_END_TR_EN;
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}
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else {
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udd_dma_ctrl |= USBHS_DEVDMACONTROL_END_B_EN;
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}
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// Start USB DMA to fill or read fifo of the selected endpoint
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USBHS->UsbhsDevdma[epnum - 1].USBHS_DEVDMAADDRESS = (uint32_t)buffer;
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udd_dma_ctrl |= USBHS_DEVDMACONTROL_END_BUFFIT | USBHS_DEVDMACONTROL_CHANN_ENB;
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// Disable IRQs to have a short sequence
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// between read of EOT_STA and DMA enable
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uint32_t irq_state = __get_PRIMASK();
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__disable_irq();
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if (!(USBHS->UsbhsDevdma[epnum - 1].USBHS_DEVDMASTATUS & USBHS_DEVDMASTATUS_END_TR_ST)) {
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USBHS->UsbhsDevdma[epnum - 1].USBHS_DEVDMACONTROL = udd_dma_ctrl;
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USBHS->USBHS_DEVIER = USBHS_DEVIER_DMA_1 << (epnum - 1);
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__set_PRIMASK(irq_state);
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return true;
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}
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__set_PRIMASK(irq_state);
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// Here a ZLP has been recieved
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// and the DMA transfer must be not started.
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// It is the end of transfer
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return false;
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}
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else {
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dcd_transmit_packet(xfer,epnum);
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if (dir == TUSB_DIR_OUT){
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USBHS->USBHS_DEVEPTIER[epnum] = USBHS_DEVEPTIER_RXOUTES;
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}
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else {
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dcd_transmit_packet(xfer,epnum);
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}
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}
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return true;
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}
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