remove bcm files
This commit is contained in:
Scott Shawcroft
parent
0a6ca65e3f
commit
0932d502c7
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@ -1,172 +0,0 @@
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.section ".text.boot" // Make sure the linker puts this at the start of the kernel image
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.global _start // Execution starts here
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_start:
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// Check processor ID is zero (executing on main core), else hang
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mrs x1, mpidr_el1
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and x1, x1, #3
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cbz x1, 2f
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// We're not on the main core, so hang in an infinite wait loop
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1: wfe
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b 1b
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2: // We're on the main core!
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// Set stack to start below our code
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ldr x1, =_start
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mov sp, x1
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adr x0, vectors // load VBAR_EL1 with virtual
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// msr vbar_el3, x0 // vector table address
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msr vbar_el1, x0 // vector table address
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msr vbar_el2, x0 // vector table address
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isb
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// Clean the BSS section
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ldr x1, =__bss_start // Start address
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ldr w2, =__bss_size // Size of the section
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3: cbz w2, 4f // Quit loop if zero
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str xzr, [x1], #8
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sub w2, w2, #1
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cbnz w2, 3b // Loop if non-zero
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// Jump to our main() routine in C (make sure it doesn't return)
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4: bl main
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// In case it does return, halt the master core too
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b 1b
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.macro ventry label
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.align 7
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b \label
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.endm
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.macro handle_invalid_entry type
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irq_entry
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mov x0, #\type
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mrs x1, esr_el1
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mrs x2, elr_el1
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mrs x3, esr_el2
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mrs x4, elr_el2
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b err_hang
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.endm
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.macro irq_entry
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sub sp, sp, #272
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stp x0, x1, [sp, #16 * 0]
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stp x2, x3, [sp, #16 * 1]
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stp x4, x5, [sp, #16 * 2]
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stp x6, x7, [sp, #16 * 3]
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stp x8, x9, [sp, #16 * 4]
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stp x10, x11, [sp, #16 * 5]
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stp x12, x13, [sp, #16 * 6]
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stp x14, x15, [sp, #16 * 7]
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stp x16, x17, [sp, #16 * 8]
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stp x18, x19, [sp, #16 * 9]
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stp x20, x21, [sp, #16 * 10]
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stp x22, x23, [sp, #16 * 11]
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stp x24, x25, [sp, #16 * 12]
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stp x26, x27, [sp, #16 * 13]
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stp x28, x29, [sp, #16 * 14]
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str x30, [sp, #16 * 15]
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.endm
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.macro irq_exit
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ldp x0, x1, [sp, #16 * 0]
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ldp x2, x3, [sp, #16 * 1]
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ldp x4, x5, [sp, #16 * 2]
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ldp x6, x7, [sp, #16 * 3]
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ldp x8, x9, [sp, #16 * 4]
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ldp x10, x11, [sp, #16 * 5]
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ldp x12, x13, [sp, #16 * 6]
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ldp x14, x15, [sp, #16 * 7]
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ldp x16, x17, [sp, #16 * 8]
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ldp x18, x19, [sp, #16 * 9]
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ldp x20, x21, [sp, #16 * 10]
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ldp x22, x23, [sp, #16 * 11]
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ldp x24, x25, [sp, #16 * 12]
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ldp x26, x27, [sp, #16 * 13]
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ldp x28, x29, [sp, #16 * 14]
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ldr x30, [sp, #16 * 15]
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add sp, sp, #272
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eret
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.endm
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/*
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* Exception vectors.
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*/
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.align 11
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.globl vectors
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vectors:
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ventry sync_invalid_el1t // Synchronous EL1t
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ventry irq_invalid_el1t // IRQ EL1t
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ventry fiq_invalid_el1t // FIQ EL1t
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ventry error_invalid_el1t // Error EL1t
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ventry sync_invalid_el1h // Synchronous EL1h
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ventry el1_irq // IRQ EL1h
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ventry fiq_invalid_el1h // FIQ EL1h
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ventry error_invalid_el1h // Error EL1h
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ventry sync_invalid_el0_64 // Synchronous 64-bit EL0
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ventry irq_invalid_el0_64 // IRQ 64-bit EL0
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ventry fiq_invalid_el0_64 // FIQ 64-bit EL0
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ventry error_invalid_el0_64 // Error 64-bit EL0
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ventry sync_invalid_el0_32 // Synchronous 32-bit EL0
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ventry irq_invalid_el0_32 // IRQ 32-bit EL0
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ventry fiq_invalid_el0_32 // FIQ 32-bit EL0
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ventry error_invalid_el0_32 // Error 32-bit EL0
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sync_invalid_el1t:
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handle_invalid_entry 0
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irq_invalid_el1t:
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handle_invalid_entry 1
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fiq_invalid_el1t:
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handle_invalid_entry 2
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error_invalid_el1t:
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handle_invalid_entry 3
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sync_invalid_el1h:
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handle_invalid_entry 4
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fiq_invalid_el1h:
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handle_invalid_entry 5
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error_invalid_el1h:
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handle_invalid_entry 6
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sync_invalid_el0_64:
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handle_invalid_entry 7
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irq_invalid_el0_64:
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handle_invalid_entry 8
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fiq_invalid_el0_64:
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handle_invalid_entry 9
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error_invalid_el0_64:
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handle_invalid_entry 10
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sync_invalid_el0_32:
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handle_invalid_entry 11
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irq_invalid_el0_32:
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handle_invalid_entry 12
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fiq_invalid_el0_32:
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handle_invalid_entry 13
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error_invalid_el0_32:
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handle_invalid_entry 14
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el1_irq:
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irq_entry
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bl handle_irq
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irq_exit
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.globl err_hang
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err_hang: b err_hang
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@ -1,26 +0,0 @@
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#include <stdbool.h>
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#include <stdint.h>
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void disable_async_interrupts(void) {
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}
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void enable_async_interrupts(void) {
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}
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void Default_Handler(void) {
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while (true) {}
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}
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__attribute__((weak)) void handle_irq(void) {
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unsigned int irq = *((volatile uint32_t*) 0x3F00B204);
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switch (irq) {
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// case (SYSTEM_TIMER_IRQ_1):
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// handle_timer_irq();
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// break;
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default:
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// printf("Unknown pending irq: %x\r\n", irq);
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Default_Handler();
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}
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}
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@ -1,8 +0,0 @@
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#pragma once
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void disable_async_interrupts(void);
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void enable_async_interrupts(void);
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#define GIC_BASE 0x4c0040000
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#define NUM_CPUS 4
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#define NUM_SPIS 192
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@ -1,170 +0,0 @@
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// From: https://github.com/isometimes/rpi4-osdev/blob/master/part4-miniuart/io.c
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// CC-0 License
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// GPIO
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// Pi 4 base address: 0xFE000000
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// Pi 3 base address: 0x3F000000
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enum {
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PERIPHERAL_BASE = 0xFE000000,
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GPFSEL0 = PERIPHERAL_BASE + 0x200000,
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GPSET0 = PERIPHERAL_BASE + 0x20001C,
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GPCLR0 = PERIPHERAL_BASE + 0x200028,
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GPPUPPDN0 = PERIPHERAL_BASE + 0x2000E4
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};
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enum {
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GPIO_MAX_PIN = 53,
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GPIO_FUNCTION_OUT = 1,
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GPIO_FUNCTION_ALT5 = 2,
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GPIO_FUNCTION_ALT3 = 7
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};
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enum {
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Pull_None = 0,
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Pull_Down = 1, // Are down and up the right way around?
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Pull_Up = 2
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};
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void mmio_write(long reg, unsigned int val) { *(volatile unsigned int *)reg = val; }
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unsigned int mmio_read(long reg) { return *(volatile unsigned int *)reg; }
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unsigned int gpio_call(unsigned int pin_number, unsigned int value, unsigned int base, unsigned int field_size, unsigned int field_max) {
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unsigned int field_mask = (1 << field_size) - 1;
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if (pin_number > field_max) return 0;
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if (value > field_mask) return 0;
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unsigned int num_fields = 32 / field_size;
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unsigned int reg = base + ((pin_number / num_fields) * 4);
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unsigned int shift = (pin_number % num_fields) * field_size;
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unsigned int curval = mmio_read(reg);
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curval &= ~(field_mask << shift);
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curval |= value << shift;
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mmio_write(reg, curval);
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return 1;
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}
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unsigned int gpio_set (unsigned int pin_number, unsigned int value) { return gpio_call(pin_number, value, GPSET0, 1, GPIO_MAX_PIN); }
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unsigned int gpio_clear (unsigned int pin_number, unsigned int value) { return gpio_call(pin_number, value, GPCLR0, 1, GPIO_MAX_PIN); }
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unsigned int gpio_pull (unsigned int pin_number, unsigned int value) { return gpio_call(pin_number, value, GPPUPPDN0, 2, GPIO_MAX_PIN); }
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unsigned int gpio_function(unsigned int pin_number, unsigned int value) { return gpio_call(pin_number, value, GPFSEL0, 3, GPIO_MAX_PIN); }
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void gpio_useAsAlt3(unsigned int pin_number) {
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gpio_pull(pin_number, Pull_None);
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gpio_function(pin_number, GPIO_FUNCTION_ALT3);
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}
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void gpio_useAsAlt5(unsigned int pin_number) {
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gpio_pull(pin_number, Pull_None);
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gpio_function(pin_number, GPIO_FUNCTION_ALT5);
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}
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void gpio_initOutputPinWithPullNone(unsigned int pin_number) {
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gpio_pull(pin_number, Pull_None);
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gpio_function(pin_number, GPIO_FUNCTION_OUT);
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}
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void gpio_setPinOutputBool(unsigned int pin_number, unsigned int onOrOff) {
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if (onOrOff) {
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gpio_set(pin_number, 1);
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} else {
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gpio_clear(pin_number, 1);
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}
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}
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// UART
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enum {
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AUX_BASE = PERIPHERAL_BASE + 0x215000,
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AUX_IRQ = AUX_BASE,
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AUX_ENABLES = AUX_BASE + 4,
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AUX_MU_IO_REG = AUX_BASE + 64,
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AUX_MU_IER_REG = AUX_BASE + 68,
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AUX_MU_IIR_REG = AUX_BASE + 72,
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AUX_MU_LCR_REG = AUX_BASE + 76,
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AUX_MU_MCR_REG = AUX_BASE + 80,
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AUX_MU_LSR_REG = AUX_BASE + 84,
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AUX_MU_MSR_REG = AUX_BASE + 88,
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AUX_MU_SCRATCH = AUX_BASE + 92,
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AUX_MU_CNTL_REG = AUX_BASE + 96,
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AUX_MU_STAT_REG = AUX_BASE + 100,
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AUX_MU_BAUD_REG = AUX_BASE + 104,
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AUX_UART_CLOCK = 500000000,
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UART_MAX_QUEUE = 16 * 1024
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};
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#define AUX_MU_BAUD(baud) ((AUX_UART_CLOCK/(baud*8))-1)
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unsigned char uart_output_queue[UART_MAX_QUEUE];
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unsigned int uart_output_queue_write = 0;
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unsigned int uart_output_queue_read = 0;
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void uart_init(void) {
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mmio_write(AUX_ENABLES, 1); //enable UART1
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mmio_write(AUX_MU_IER_REG, 0);
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mmio_write(AUX_MU_CNTL_REG, 0);
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mmio_write(AUX_MU_LCR_REG, 3); //8 bits
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mmio_write(AUX_MU_MCR_REG, 0);
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mmio_write(AUX_MU_IER_REG, 0);
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mmio_write(AUX_MU_IIR_REG, 0xC6); //disable interrupts
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mmio_write(AUX_MU_BAUD_REG, AUX_MU_BAUD(115200));
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gpio_useAsAlt5(14);
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gpio_useAsAlt5(15);
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mmio_write(AUX_MU_CNTL_REG, 3); //enable RX/TX
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}
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unsigned int uart_isOutputQueueEmpty(void) {
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return uart_output_queue_read == uart_output_queue_write;
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}
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unsigned int uart_isReadByteReady(void) { return mmio_read(AUX_MU_LSR_REG) & 0x01; }
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unsigned int uart_isWriteByteReady(void) { return mmio_read(AUX_MU_LSR_REG) & 0x20; }
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unsigned char uart_readByte(void) {
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while (!uart_isReadByteReady());
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return (unsigned char)mmio_read(AUX_MU_IO_REG);
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}
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void uart_writeByteBlockingActual(unsigned char ch) {
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while (!uart_isWriteByteReady());
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mmio_write(AUX_MU_IO_REG, (unsigned int)ch);
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}
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void uart_loadOutputFifo(void) {
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while (!uart_isOutputQueueEmpty() && uart_isWriteByteReady()) {
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uart_writeByteBlockingActual(uart_output_queue[uart_output_queue_read]);
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uart_output_queue_read = (uart_output_queue_read + 1) & (UART_MAX_QUEUE - 1); // Don't overrun
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}
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}
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void uart_writeByteBlocking(unsigned char ch) {
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unsigned int next = (uart_output_queue_write + 1) & (UART_MAX_QUEUE - 1); // Don't overrun
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while (next == uart_output_queue_read) uart_loadOutputFifo();
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uart_output_queue[uart_output_queue_write] = ch;
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uart_output_queue_write = next;
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}
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void uart_writeText(const char *buffer) {
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while (*buffer) {
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if (*buffer == '\n') uart_writeByteBlocking('\r');
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uart_writeByteBlocking(*buffer++);
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}
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}
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void uart_drainOutputQueue(void) {
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while (!uart_isOutputQueueEmpty()) uart_loadOutputFifo();
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}
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void uart_update(void) {
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uart_loadOutputFifo();
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if (uart_isReadByteReady()) {
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unsigned char ch = uart_readByte();
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if (ch == '\r') uart_writeText("\n"); else uart_writeByteBlocking(ch);
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}
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}
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@ -1,13 +0,0 @@
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// From: https://github.com/isometimes/rpi4-osdev/blob/master/part4-miniuart/io.h
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// CC-0 License
|
||||
|
||||
void uart_init(void);
|
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void uart_writeText(const char *buffer);
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void uart_loadOutputFifo(void);
|
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unsigned char uart_readByte(void);
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unsigned int uart_isReadByteReady(void);
|
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void uart_writeByteBlocking(unsigned char ch);
|
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void uart_update(void);
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void gpio_setPinOutputBool(unsigned int pin_number, unsigned int onOrOff);
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void uart_writeByteBlockingActual(unsigned char ch);
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void gpio_initOutputPinWithPullNone(unsigned int pin_number);
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|
|
@ -1,28 +0,0 @@
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SECTIONS
|
||||
{
|
||||
. = 0x80000; /* Kernel load address for AArch64 */
|
||||
.text : {
|
||||
KEEP(*(.text.boot))
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||||
*(.text .text.* .gnu.linkonce.t*)
|
||||
}
|
||||
.rodata : {
|
||||
. = ALIGN(4096);
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||||
*(.rodata .rodata.* .gnu.linkonce.r*)
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||||
}
|
||||
PROVIDE(_data = .);
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||||
.data : {
|
||||
. = ALIGN(4096);
|
||||
*(.data .data.* .gnu.linkonce.d*)
|
||||
}
|
||||
.bss (NOLOAD) : {
|
||||
__bss_start = .;
|
||||
*(.bss .bss.*)
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||||
*(COMMON)
|
||||
__bss_end = .;
|
||||
}
|
||||
_end = .;
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||||
end = .;
|
||||
|
||||
/DISCARD/ : { *(.comment) *(.gnu*) *(.note*) *(.eh_frame*) }
|
||||
}
|
||||
__bss_size = (__bss_end - __bss_start)>>3;
|
||||
|
|
@ -1,62 +0,0 @@
|
|||
#include <stdbool.h>
|
||||
#include <stdint.h>
|
||||
|
||||
|
||||
#include "mmu.h"
|
||||
|
||||
// Each entry is a gig.
|
||||
volatile uint64_t level_1_table[512] __attribute__((aligned(4096)));
|
||||
|
||||
// Third gig has peripherals
|
||||
uint64_t level_2_0x0_c000_0000_to_0x1_0000_0000[512] __attribute__((aligned(4096)));
|
||||
|
||||
void setup_mmu_flat_map(void) {
|
||||
// Set the first gig to regular access.
|
||||
level_1_table[0] = 0x0000000000000000 |
|
||||
MM_DESCRIPTOR_MAIR_INDEX(MT_NORMAL_NC) |
|
||||
MM_DESCRIPTOR_ACCESS_FLAG |
|
||||
MM_DESCRIPTOR_BLOCK |
|
||||
MM_DESCRIPTOR_VALID;
|
||||
level_1_table[3] = ((uint64_t) level_2_0x0_c000_0000_to_0x1_0000_0000) |
|
||||
MM_DESCRIPTOR_TABLE |
|
||||
MM_DESCRIPTOR_VALID;
|
||||
// Set peripherals to register access.
|
||||
for (uint64_t i = 480; i < 512; i++) {
|
||||
level_2_0x0_c000_0000_to_0x1_0000_0000[i] = (0x00000000c0000000 + (i << 21)) |
|
||||
MM_DESCRIPTOR_EXECUTE_NEVER |
|
||||
MM_DESCRIPTOR_MAIR_INDEX(MT_DEVICE_nGnRnE) |
|
||||
MM_DESCRIPTOR_ACCESS_FLAG |
|
||||
MM_DESCRIPTOR_BLOCK |
|
||||
MM_DESCRIPTOR_VALID;
|
||||
}
|
||||
uint64_t mair = MAIR_VALUE;
|
||||
uint64_t tcr = TCR_VALUE;
|
||||
uint64_t ttbr0 = ((uint64_t) level_1_table) | MM_TTBR_CNP;
|
||||
uint64_t sctlr = 0;
|
||||
__asm__ volatile (
|
||||
// Set MAIR
|
||||
"MSR MAIR_EL2, %[mair]\n\t"
|
||||
// Set TTBR0
|
||||
"MSR TTBR0_EL2, %[ttbr0]\n\t"
|
||||
// Set TCR
|
||||
"MSR TCR_EL2, %[tcr]\n\t"
|
||||
// The ISB forces these changes to be seen before the MMU is enabled.
|
||||
"ISB\n\t"
|
||||
// Read System Control Register configuration data
|
||||
"MRS %[sctlr], SCTLR_EL2\n\t"
|
||||
// Write System Control Register configuration data
|
||||
"ORR %[sctlr], %[sctlr], #1\n\t"
|
||||
// Set [M] bit and enable the MMU.
|
||||
"MSR SCTLR_EL2, %[sctlr]\n\t"
|
||||
// The ISB forces these changes to be seen by the next instruction
|
||||
"ISB\n\t"
|
||||
// "AT S1EL2R %[ttbr0]"
|
||||
: /* No outputs. */
|
||||
: [mair] "r" (mair),
|
||||
[tcr] "r" (tcr),
|
||||
[ttbr0] "r" (ttbr0),
|
||||
[sctlr] "r" (sctlr)
|
||||
);
|
||||
//__asm__ ("brk #123");
|
||||
//while (true) {}
|
||||
}
|
||||
|
|
@ -1,45 +0,0 @@
|
|||
#pragma once
|
||||
|
||||
|
||||
// From: https://github.com/s-matyukevich/raspberry-pi-os/blob/master/docs/lesson06/rpi-os.md
|
||||
/*
|
||||
* Memory region attributes:
|
||||
*
|
||||
* n = AttrIndx[2:0]
|
||||
* n MAIR
|
||||
* DEVICE_nGnRnE 000 00000000
|
||||
* NORMAL_NC 001 01000100
|
||||
*/
|
||||
#define MT_DEVICE_nGnRnE 0x0
|
||||
#define MT_NORMAL_NC 0x1
|
||||
#define MT_DEVICE_nGnRnE_FLAGS 0x00
|
||||
#define MT_NORMAL_NC_FLAGS 0xff
|
||||
#define MAIR_VALUE (MT_DEVICE_nGnRnE_FLAGS << (8 * MT_DEVICE_nGnRnE)) | (MT_NORMAL_NC_FLAGS << (8 * MT_NORMAL_NC))
|
||||
|
||||
|
||||
#define TCR_T0SZ (64 - 36)
|
||||
#define TCR_PS (0x01 << 16) // 36-bit physical address
|
||||
#define TCR_TG0_4K (0 << 14)
|
||||
#define TCR_SH0_OUTER_SHAREABLE (0x2 << 12)
|
||||
#define TCR_VALUE (TCR_T0SZ | TCR_PS | TCR_TG0_4K | TCR_SH0_OUTER_SHAREABLE)
|
||||
|
||||
#define ENTRY_TYPE_TABLE_DESCRIPTOR 0x11
|
||||
#define ENTRY_TYPE_BLOCK_ENTRY 0x01
|
||||
#define ENTRY_TYPE_TABLE_ENTRY 0x11
|
||||
#define ENTRY_TYPE_INVALID 0x00
|
||||
|
||||
#define MM_DESCRIPTOR_VALID (0x1)
|
||||
|
||||
#define MM_DESCRIPTOR_BLOCK (0x0 << 1)
|
||||
#define MM_DESCRIPTOR_TABLE (0x1 << 1)
|
||||
|
||||
// Block attributes
|
||||
#define MM_DESCRIPTOR_EXECUTE_NEVER (0x1ull << 54)
|
||||
#define MM_DESCRIPTOR_CONTIGUOUS (0x1ull << 52)
|
||||
#define MM_DESCRIPTOR_ACCESS_FLAG (0x1ull << 10)
|
||||
|
||||
#define MM_DESCRIPTOR_MAIR_INDEX(index) (index << 2)
|
||||
|
||||
#define MM_TTBR_CNP (0x1)
|
||||
|
||||
void setup_mmu_flat_map(void);
|
||||
Loading…
Reference in New Issue