143 lines
3.3 KiB
C
143 lines
3.3 KiB
C
#define __16f1847
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#include <pic16f1847.h>
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#include <stdint.h>
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#include "I2C.h"
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/* set clock high (default state) */
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#define release_SCL() LATB |= SCL
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/* set clock low */
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#define hold_SCL() LATB &= ~SCL
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/* set data high (default state) */
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#define release_SDA() LATB |= SDA
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/* set data low */
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#define hold_SDA() LATB &= ~SDA
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/* a small delay for better clock */
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#define delay() __asm\
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nop\
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nop\
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nop\
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nop\
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__endasm
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/* read SDA
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* set SDA as input in the begining
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* set SDA as output in the end
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*/
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uint8_t read_ack(void)
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{
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uint8_t ack;
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hold_SCL(); /* set clock to low for SDA to change */
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TRISB |= SDA; /* set as input */
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delay(); /* wait for SDA to change */
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release_SCL(); /* SDA should be valid when clock is high */
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delay();
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/* we don't verify the SCL state as only we can drive it */
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if (PORTB&SDA) { /* read bit */
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ack = 1;
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} else {
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ack = 0;
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}
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hold_SCL(); /* put clock to low, as safe state */
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release_SDA(); /* set data to default state */
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TRISB &= ~SDA; /* set back to output */
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/* leave the output value as it is */
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return ack;
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}
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/* sent start condition
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* falling SDA while SCL is high
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*/
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void send_start(void)
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{
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release_SCL(); /* endure SCL is high */
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delay();
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release_SDA(); /* ensure SDA is high to be able to start */
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delay();
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hold_SDA(); /* send start signal */
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}
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/* send stop condition
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* rising SDA while SCL is high
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*/
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void send_stop(void)
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{
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hold_SDA(); /* be sure SDA is low for rising edge */
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delay();
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release_SCL(); /* be sure SCL is high */
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delay();
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release_SDA(); /* set SDA high while SCL is high */
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}
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/* send byte and get ack (0=ack) */
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uint8_t send_byte(uint8_t byte)
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{
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uint8_t bit, ack;
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/* send every bit, MSb first */
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for (bit = 0; bit < 8; bit++) {
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hold_SCL(); /* value can change when SCL is low */
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delay();
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if (byte&0x80) {
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release_SDA(); /* set high for 1 */
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} else {
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hold_SDA(); /* set low for 0 */
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}
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delay();
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release_SCL(); /* set clock high to indicate valid value */
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byte <<= 1;
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}
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/* read ack */
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delay();
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hold_SCL(); /* set clock to low for SDA to change */
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TRISB |= SDA; /* set as input */
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delay(); /* wait for SDA to change */
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delay();
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delay();
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release_SCL(); /* SDA should be valid when clock is high */
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delay();
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/* we don't verify the SCL state as only we can drive it */
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if (PORTB&SDA) { /* read bit */
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ack = 1;
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} else {
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ack = 0;
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}
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hold_SCL(); /* put clock to low, as safe state */
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delay();
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release_SDA(); /* set output to high (default) */
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TRISB &= ~SDA; /* set back to output */
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return ack;
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}
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/* read one byte and send an ack
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* send an ack if you want to read more bytes
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* send a nack if this is the last byte read
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*/
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uint8_t read_byte(uint8_t ack)
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{
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uint8_t byte = 0;
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uint8_t bit;
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hold_SCL(); /* set clock to low for SDA to change */
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TRISB |= SDA; /* set as input */
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for (bit=0; bit<8; bit++) {
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delay(); /* wait for SDA to change */
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release_SCL(); /* SDA should be valid when clock is high */
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byte <<= 1; /* make place to save the next bit */
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if (PORTB&SDA) { /* read bit */
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byte += 1;
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} else {
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byte += 0;
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}
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hold_SCL(); /* set clock to low for SDA to change */
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}
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if (ack) {
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hold_SDA(); /* set low for ack */
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} else {
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release_SDA(); /* set high for nack */
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}
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TRISB &= ~SDA; /* set back to output */
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delay();
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release_SCL(); /* set clock high to indicate valid value */
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delay();
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hold_SCL(); /* set clock to low for SDA to change */
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return byte;
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}
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