425 lines
19 KiB
C
425 lines
19 KiB
C
/*
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* @brief LPC18xx/43xx General Purpose DMA driver
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*
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* @note
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* Copyright(C) NXP Semiconductors, 2012
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* All rights reserved.
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*
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* @par
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* Software that is described herein is for illustrative purposes only
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* which provides customers with programming information regarding the
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* LPC products. This software is supplied "AS IS" without any warranties of
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* any kind, and NXP Semiconductors and its licensor disclaim any and
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* all warranties, express or implied, including all implied warranties of
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* merchantability, fitness for a particular purpose and non-infringement of
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* intellectual property rights. NXP Semiconductors assumes no responsibility
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* or liability for the use of the software, conveys no license or rights under any
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* patent, copyright, mask work right, or any other intellectual property rights in
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* or to any products. NXP Semiconductors reserves the right to make changes
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* in the software without notification. NXP Semiconductors also makes no
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* representation or warranty that such application will be suitable for the
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* specified use without further testing or modification.
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*
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* @par
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* Permission to use, copy, modify, and distribute this software and its
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* documentation is hereby granted, under NXP Semiconductors' and its
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* licensor's relevant copyrights in the software, without fee, provided that it
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* is used in conjunction with NXP Semiconductors microcontrollers. This
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* copyright, permission, and disclaimer notice must appear in all copies of
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* this code.
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*/
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#ifndef __GPDMA_18XX_43XX_H_
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#define __GPDMA_18XX_43XX_H_
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#ifdef __cplusplus
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extern "C" {
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#endif
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/** @defgroup GPDMA_18XX_43XX CHIP: LPC18xx/43xx General Purpose DMA driver
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* @ingroup CHIP_18XX_43XX_Drivers
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* @{
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*/
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/**
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* @brief Number of channels on GPDMA
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*/
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#define GPDMA_NUMBER_CHANNELS 8
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/**
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* @brief GPDMA Channel register block structure
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*/
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typedef struct {
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__IO uint32_t SRCADDR; /*!< DMA Channel Source Address Register */
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__IO uint32_t DESTADDR; /*!< DMA Channel Destination Address Register */
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__IO uint32_t LLI; /*!< DMA Channel Linked List Item Register */
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__IO uint32_t CONTROL; /*!< DMA Channel Control Register */
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__IO uint32_t CONFIG; /*!< DMA Channel Configuration Register */
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__I uint32_t RESERVED1[3];
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} GPDMA_CH_T;
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/**
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* @brief GPDMA register block
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*/
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typedef struct { /*!< GPDMA Structure */
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__I uint32_t INTSTAT; /*!< DMA Interrupt Status Register */
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__I uint32_t INTTCSTAT; /*!< DMA Interrupt Terminal Count Request Status Register */
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__O uint32_t INTTCCLEAR; /*!< DMA Interrupt Terminal Count Request Clear Register */
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__I uint32_t INTERRSTAT; /*!< DMA Interrupt Error Status Register */
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__O uint32_t INTERRCLR; /*!< DMA Interrupt Error Clear Register */
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__I uint32_t RAWINTTCSTAT; /*!< DMA Raw Interrupt Terminal Count Status Register */
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__I uint32_t RAWINTERRSTAT; /*!< DMA Raw Error Interrupt Status Register */
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__I uint32_t ENBLDCHNS; /*!< DMA Enabled Channel Register */
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__IO uint32_t SOFTBREQ; /*!< DMA Software Burst Request Register */
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__IO uint32_t SOFTSREQ; /*!< DMA Software Single Request Register */
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__IO uint32_t SOFTLBREQ; /*!< DMA Software Last Burst Request Register */
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__IO uint32_t SOFTLSREQ; /*!< DMA Software Last Single Request Register */
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__IO uint32_t CONFIG; /*!< DMA Configuration Register */
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__IO uint32_t SYNC; /*!< DMA Synchronization Register */
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__I uint32_t RESERVED0[50];
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GPDMA_CH_T CH[GPDMA_NUMBER_CHANNELS];
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} LPC_GPDMA_T;
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/**
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* @brief Macro defines for DMA channel control registers
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*/
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#define GPDMA_DMACCxControl_TransferSize(n) (((n & 0xFFF) << 0)) /*!< Transfer size*/
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#define GPDMA_DMACCxControl_SBSize(n) (((n & 0x07) << 12)) /*!< Source burst size*/
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#define GPDMA_DMACCxControl_DBSize(n) (((n & 0x07) << 15)) /*!< Destination burst size*/
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#define GPDMA_DMACCxControl_SWidth(n) (((n & 0x07) << 18)) /*!< Source transfer width*/
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#define GPDMA_DMACCxControl_DWidth(n) (((n & 0x07) << 21)) /*!< Destination transfer width*/
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#define GPDMA_DMACCxControl_SI ((1UL << 26)) /*!< Source increment*/
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#define GPDMA_DMACCxControl_DI ((1UL << 27)) /*!< Destination increment*/
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#define GPDMA_DMACCxControl_SrcTransUseAHBMaster1 ((1UL << 24)) /*!< Source AHB master select in 18xx43xx*/
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#define GPDMA_DMACCxControl_DestTransUseAHBMaster1 ((1UL << 25)) /*!< Destination AHB master select in 18xx43xx*/
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#define GPDMA_DMACCxControl_Prot1 ((1UL << 28)) /*!< Indicates that the access is in user mode or privileged mode*/
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#define GPDMA_DMACCxControl_Prot2 ((1UL << 29)) /*!< Indicates that the access is bufferable or not bufferable*/
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#define GPDMA_DMACCxControl_Prot3 ((1UL << 30)) /*!< Indicates that the access is cacheable or not cacheable*/
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#define GPDMA_DMACCxControl_I ((1UL << 31)) /*!< Terminal count interrupt enable bit */
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/**
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* @brief Macro defines for DMA Configuration register
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*/
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#define GPDMA_DMACConfig_E ((0x01)) /*!< DMA Controller enable*/
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#define GPDMA_DMACConfig_M ((0x02)) /*!< AHB Master endianness configuration*/
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#define GPDMA_DMACConfig_BITMASK ((0x03))
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/**
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* @brief Macro defines for DMA Channel Configuration registers
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*/
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#define GPDMA_DMACCxConfig_E ((1UL << 0)) /*!< DMA control enable*/
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#define GPDMA_DMACCxConfig_SrcPeripheral(n) (((n & 0x1F) << 1)) /*!< Source peripheral*/
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#define GPDMA_DMACCxConfig_DestPeripheral(n) (((n & 0x1F) << 6)) /*!< Destination peripheral*/
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#define GPDMA_DMACCxConfig_TransferType(n) (((n & 0x7) << 11)) /*!< This value indicates the type of transfer*/
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#define GPDMA_DMACCxConfig_IE ((1UL << 14)) /*!< Interrupt error mask*/
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#define GPDMA_DMACCxConfig_ITC ((1UL << 15)) /*!< Terminal count interrupt mask*/
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#define GPDMA_DMACCxConfig_L ((1UL << 16)) /*!< Lock*/
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#define GPDMA_DMACCxConfig_A ((1UL << 17)) /*!< Active*/
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#define GPDMA_DMACCxConfig_H ((1UL << 18)) /*!< Halt*/
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/**
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* @brief GPDMA Interrupt Clear Status
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*/
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typedef enum {
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GPDMA_STATCLR_INTTC, /*!< GPDMA Interrupt Terminal Count Request Clear */
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GPDMA_STATCLR_INTERR /*!< GPDMA Interrupt Error Clear */
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} GPDMA_STATECLEAR_T;
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/**
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* @brief GPDMA Type of Interrupt Status
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*/
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typedef enum {
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GPDMA_STAT_INT, /*!< GPDMA Interrupt Status */
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GPDMA_STAT_INTTC, /*!< GPDMA Interrupt Terminal Count Request Status */
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GPDMA_STAT_INTERR, /*!< GPDMA Interrupt Error Status */
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GPDMA_STAT_RAWINTTC, /*!< GPDMA Raw Interrupt Terminal Count Status */
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GPDMA_STAT_RAWINTERR, /*!< GPDMA Raw Error Interrupt Status */
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GPDMA_STAT_ENABLED_CH /*!< GPDMA Enabled Channel Status */
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} GPDMA_STATUS_T;
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/**
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* @brief GPDMA Type of DMA controller
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*/
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typedef enum {
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GPDMA_TRANSFERTYPE_M2M_CONTROLLER_DMA = ((0UL)), /*!< Memory to memory - DMA control */
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GPDMA_TRANSFERTYPE_M2P_CONTROLLER_DMA = ((1UL)), /*!< Memory to peripheral - DMA control */
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GPDMA_TRANSFERTYPE_P2M_CONTROLLER_DMA = ((2UL)), /*!< Peripheral to memory - DMA control */
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GPDMA_TRANSFERTYPE_P2P_CONTROLLER_DMA = ((3UL)), /*!< Source peripheral to destination peripheral - DMA control */
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GPDMA_TRANSFERTYPE_P2P_CONTROLLER_DestPERIPHERAL = ((4UL)), /*!< Source peripheral to destination peripheral - destination peripheral control */
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GPDMA_TRANSFERTYPE_M2P_CONTROLLER_PERIPHERAL = ((5UL)), /*!< Memory to peripheral - peripheral control */
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GPDMA_TRANSFERTYPE_P2M_CONTROLLER_PERIPHERAL = ((6UL)), /*!< Peripheral to memory - peripheral control */
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GPDMA_TRANSFERTYPE_P2P_CONTROLLER_SrcPERIPHERAL = ((7UL)) /*!< Source peripheral to destination peripheral - source peripheral control */
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} GPDMA_FLOW_CONTROL_T;
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/**
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* @brief GPDMA structure using for DMA configuration
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*/
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typedef struct {
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uint32_t ChannelNum; /*!< DMA channel number, should be in
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* range from 0 to 7.
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* Note: DMA channel 0 has the highest priority
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* and DMA channel 7 the lowest priority.
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*/
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uint32_t TransferSize; /*!< Length/Size of transfer */
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uint32_t TransferWidth; /*!< Transfer width - used for TransferType is GPDMA_TRANSFERTYPE_M2M only */
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uint32_t SrcAddr; /*!< Physical Source Address, used in case TransferType is chosen as
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* GPDMA_TRANSFERTYPE_M2M or GPDMA_TRANSFERTYPE_M2P */
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uint32_t DstAddr; /*!< Physical Destination Address, used in case TransferType is chosen as
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* GPDMA_TRANSFERTYPE_M2M or GPDMA_TRANSFERTYPE_P2M */
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uint32_t TransferType; /*!< Transfer Type, should be one of the following:
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* - GPDMA_TRANSFERTYPE_M2M: Memory to memory - DMA control
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* - GPDMA_TRANSFERTYPE_M2P: Memory to peripheral - DMA control
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* - GPDMA_TRANSFERTYPE_P2M: Peripheral to memory - DMA control
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* - GPDMA_TRANSFERTYPE_P2P: Source peripheral to destination peripheral - DMA control
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*/
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} GPDMA_CH_CFG_T;
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/**
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* @brief GPDMA request connections
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*/
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#define GPDMA_CONN_MEMORY ((0UL)) /**< MEMORY */
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#define GPDMA_CONN_MAT0_0 ((1UL)) /**< MAT0.0 */
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#define GPDMA_CONN_UART0_Tx ((2UL)) /**< UART0 Tx */
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#define GPDMA_CONN_MAT0_1 ((3UL)) /**< MAT0.1 */
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#define GPDMA_CONN_UART0_Rx ((4UL)) /**< UART0 Rx */
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#define GPDMA_CONN_MAT1_0 ((5UL)) /**< MAT1.0 */
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#define GPDMA_CONN_UART1_Tx ((6UL)) /**< UART1 Tx */
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#define GPDMA_CONN_MAT1_1 ((7UL)) /**< MAT1.1 */
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#define GPDMA_CONN_UART1_Rx ((8UL)) /**< UART1 Rx */
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#define GPDMA_CONN_MAT2_0 ((9UL)) /**< MAT2.0 */
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#define GPDMA_CONN_UART2_Tx ((10UL)) /**< UART2 Tx */
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#define GPDMA_CONN_MAT2_1 ((11UL)) /**< MAT2.1 */
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#define GPDMA_CONN_UART2_Rx ((12UL)) /**< UART2 Rx */
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#define GPDMA_CONN_MAT3_0 ((13UL)) /**< MAT3.0 */
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#define GPDMA_CONN_UART3_Tx ((14UL)) /**< UART3 Tx */
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#define GPDMA_CONN_SCT_0 ((15UL)) /**< SCT timer channel 0*/
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#define GPDMA_CONN_MAT3_1 ((16UL)) /**< MAT3.1 */
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#define GPDMA_CONN_UART3_Rx ((17UL)) /**< UART3 Rx */
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#define GPDMA_CONN_SCT_1 ((18UL)) /**< SCT timer channel 1*/
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#define GPDMA_CONN_SSP0_Rx ((19UL)) /**< SSP0 Rx */
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#define GPDMA_CONN_I2S_Tx_Channel_0 ((20UL)) /**< I2S0 Tx on channel 0 */
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#define GPDMA_CONN_SSP0_Tx ((21UL)) /**< SSP0 Tx */
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#define GPDMA_CONN_I2S_Rx_Channel_1 ((22UL)) /**< I2S0 Rx on channel 0 */
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#define GPDMA_CONN_SSP1_Rx ((23UL)) /**< SSP1 Rx */
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#define GPDMA_CONN_SSP1_Tx ((24UL)) /**< SSP1 Tx */
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#define GPDMA_CONN_ADC_0 ((25UL)) /**< ADC 0 */
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#define GPDMA_CONN_ADC_1 ((26UL)) /**< ADC 1 */
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#define GPDMA_CONN_DAC ((27UL)) /**< DAC */
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#define GPDMA_CONN_I2S1_Tx_Channel_0 ((28UL)) /**< I2S1 Tx on channel 0 */
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#define GPDMA_CONN_I2S1_Rx_Channel_1 ((29UL)) /**< I2S1 Rx on channel 0 */
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/**
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* @brief GPDMA Burst size in Source and Destination definitions
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*/
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#define GPDMA_BSIZE_1 ((0UL)) /*!< Burst size = 1 */
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#define GPDMA_BSIZE_4 ((1UL)) /*!< Burst size = 4 */
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#define GPDMA_BSIZE_8 ((2UL)) /*!< Burst size = 8 */
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#define GPDMA_BSIZE_16 ((3UL)) /*!< Burst size = 16 */
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#define GPDMA_BSIZE_32 ((4UL)) /*!< Burst size = 32 */
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#define GPDMA_BSIZE_64 ((5UL)) /*!< Burst size = 64 */
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#define GPDMA_BSIZE_128 ((6UL)) /*!< Burst size = 128 */
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#define GPDMA_BSIZE_256 ((7UL)) /*!< Burst size = 256 */
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/**
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* @brief Width in Source transfer width and Destination transfer width definitions
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*/
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#define GPDMA_WIDTH_BYTE ((0UL)) /*!< Width = 1 byte */
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#define GPDMA_WIDTH_HALFWORD ((1UL)) /*!< Width = 2 bytes */
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#define GPDMA_WIDTH_WORD ((2UL)) /*!< Width = 4 bytes */
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/**
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* @brief Flow control definitions
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*/
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#define DMA_CONTROLLER 0 /*!< Flow control is DMA controller*/
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#define SRC_PER_CONTROLLER 1 /*!< Flow control is Source peripheral controller*/
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#define DST_PER_CONTROLLER 2 /*!< Flow control is Destination peripheral controller*/
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/**
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* @brief DMA channel handle structure
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*/
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typedef struct {
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FunctionalState ChannelStatus; /*!< DMA channel status */
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} DMA_ChannelHandle_t;
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/**
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* @brief Transfer Descriptor structure typedef
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*/
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typedef struct DMA_TransferDescriptor {
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uint32_t src; /*!< Source address */
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uint32_t dst; /*!< Destination address */
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uint32_t lli; /*!< Pointer to next descriptor structure */
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uint32_t ctrl; /*!< Control word that has transfer size, type etc. */
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} DMA_TransferDescriptor_t;
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/**
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* @brief Initialize the GPDMA
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* @param pGPDMA : The base of GPDMA on the chip
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* @return Nothing
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*/
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void Chip_GPDMA_Init(LPC_GPDMA_T *pGPDMA);
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/**
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* @brief Shutdown the GPDMA
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* @param pGPDMA : The base of GPDMA on the chip
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* @return Nothing
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*/
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void Chip_GPDMA_DeInit(LPC_GPDMA_T *pGPDMA);
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/**
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* @brief Initialize channel configuration strucutre
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* @param pGPDMA : The base of GPDMA on the chip
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* @param GPDMACfg : Pointer to configuration structure to be initialized
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* @param ChannelNum : Channel used for transfer *must be obtained using Chip_GPDMA_GetFreeChannel()*
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* @param src : Address of Memory or one of @link #GPDMA_CONN_MEMORY
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* PeripheralConnection_ID @endlink, which is the source
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* @param dst : Address of Memory or one of @link #GPDMA_CONN_MEMORY
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* PeripheralConnection_ID @endlink, which is the destination
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* @param Size : The number of DMA transfers
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* @param TransferType : Select the transfer controller and the type of transfer. (See, #GPDMA_FLOW_CONTROL_T)
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* @return ERROR on error, SUCCESS on success
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*/
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int Chip_GPDMA_InitChannelCfg(LPC_GPDMA_T *pGPDMA,
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GPDMA_CH_CFG_T *GPDMACfg,
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uint8_t ChannelNum,
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uint32_t src,
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uint32_t dst,
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uint32_t Size,
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GPDMA_FLOW_CONTROL_T TransferType);
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/**
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* @brief Enable or Disable the GPDMA Channel
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* @param pGPDMA : The base of GPDMA on the chip
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* @param channelNum : The GPDMA channel : 0 - 7
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* @param NewState : ENABLE to enable GPDMA or DISABLE to disable GPDMA
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* @return Nothing
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*/
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void Chip_GPDMA_ChannelCmd(LPC_GPDMA_T *pGPDMA, uint8_t channelNum, FunctionalState NewState);
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/**
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* @brief Stop a stream DMA transfer
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* @param pGPDMA : The base of GPDMA on the chip
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* @param ChannelNum : Channel Number to be closed
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* @return Nothing
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*/
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void Chip_GPDMA_Stop(LPC_GPDMA_T *pGPDMA, uint8_t ChannelNum);
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/**
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* @brief The GPDMA stream interrupt status checking
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* @param pGPDMA : The base of GPDMA on the chip
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* @param ChannelNum : Channel Number to be checked on interruption
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* @return Status:
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* - SUCCESS : DMA transfer success
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* - ERROR : DMA transfer failed
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*/
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Status Chip_GPDMA_Interrupt(LPC_GPDMA_T *pGPDMA, uint8_t ChannelNum);
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/**
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* @brief Read the status from different registers according to the type
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* @param pGPDMA : The base of GPDMA on the chip
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* @param type : Status mode, should be:
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* - GPDMA_STAT_INT : GPDMA Interrupt Status
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* - GPDMA_STAT_INTTC : GPDMA Interrupt Terminal Count Request Status
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* - GPDMA_STAT_INTERR : GPDMA Interrupt Error Status
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* - GPDMA_STAT_RAWINTTC : GPDMA Raw Interrupt Terminal Count Status
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* - GPDMA_STAT_RAWINTERR : GPDMA Raw Error Interrupt Status
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* - GPDMA_STAT_ENABLED_CH : GPDMA Enabled Channel Status
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* @param channel : The GPDMA channel : 0 - 7
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* @return SET is interrupt is pending or RESET if not pending
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*/
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IntStatus Chip_GPDMA_IntGetStatus(LPC_GPDMA_T *pGPDMA, GPDMA_STATUS_T type, uint8_t channel);
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/**
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* @brief Clear the Interrupt Flag from different registers according to the type
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* @param pGPDMA : The base of GPDMA on the chip
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* @param type : Flag mode, should be:
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* - GPDMA_STATCLR_INTTC : GPDMA Interrupt Terminal Count Request
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* - GPDMA_STATCLR_INTERR : GPDMA Interrupt Error
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* @param channel : The GPDMA channel : 0 - 7
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* @return Nothing
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*/
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void Chip_GPDMA_ClearIntPending(LPC_GPDMA_T *pGPDMA, GPDMA_STATECLEAR_T type, uint8_t channel);
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/**
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* @brief Get a free GPDMA channel for one DMA connection
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* @param pGPDMA : The base of GPDMA on the chip
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* @param PeripheralConnection_ID : Some chip fix each peripheral DMA connection on a specified channel ( have not used in 17xx/40xx )
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* @return The channel number which is selected
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*/
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uint8_t Chip_GPDMA_GetFreeChannel(LPC_GPDMA_T *pGPDMA,
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uint32_t PeripheralConnection_ID);
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/**
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* @brief Do a DMA transfer M2M, M2P,P2M or P2P
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* @param pGPDMA : The base of GPDMA on the chip
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* @param ChannelNum : Channel used for transfer
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* @param src : Address of Memory or PeripheralConnection_ID which is the source
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* @param dst : Address of Memory or PeripheralConnection_ID which is the destination
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* @param TransferType: Select the transfer controller and the type of transfer. Should be:
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* - GPDMA_TRANSFERTYPE_M2M_CONTROLLER_DMA
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* - GPDMA_TRANSFERTYPE_M2P_CONTROLLER_DMA
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* - GPDMA_TRANSFERTYPE_P2M_CONTROLLER_DMA
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* - GPDMA_TRANSFERTYPE_P2P_CONTROLLER_DMA
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* - GPDMA_TRANSFERTYPE_P2P_CONTROLLER_DestPERIPHERAL
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* - GPDMA_TRANSFERTYPE_M2P_CONTROLLER_PERIPHERAL
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* - GPDMA_TRANSFERTYPE_P2M_CONTROLLER_PERIPHERAL
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* - GPDMA_TRANSFERTYPE_P2P_CONTROLLER_SrcPERIPHERAL
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* @param Size : The number of DMA transfers
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* @return ERROR on error, SUCCESS on success
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*/
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Status Chip_GPDMA_Transfer(LPC_GPDMA_T *pGPDMA,
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uint8_t ChannelNum,
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uint32_t src,
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uint32_t dst,
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GPDMA_FLOW_CONTROL_T TransferType,
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uint32_t Size);
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/**
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* @brief Do a DMA transfer using linked list of descriptors
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* @param pGPDMA : The base of GPDMA on the chip
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* @param ChannelNum : Channel used for transfer *must be obtained using Chip_GPDMA_GetFreeChannel()*
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* @param DMADescriptor : First node in the linked list of descriptors
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* @param TransferType : Select the transfer controller and the type of transfer. (See, #GPDMA_FLOW_CONTROL_T)
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* @return ERROR on error, SUCCESS on success
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*/
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Status Chip_GPDMA_SGTransfer(LPC_GPDMA_T *pGPDMA,
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uint8_t ChannelNum,
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const DMA_TransferDescriptor_t *DMADescriptor,
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GPDMA_FLOW_CONTROL_T TransferType);
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/**
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* @brief Prepare a single DMA descriptor
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* @param pGPDMA : The base of GPDMA on the chip
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* @param DMADescriptor : DMA Descriptor to be initialized
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* @param src : Address of Memory or one of @link #GPDMA_CONN_MEMORY
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* PeripheralConnection_ID @endlink, which is the source
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* @param dst : Address of Memory or one of @link #GPDMA_CONN_MEMORY
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* PeripheralConnection_ID @endlink, which is the destination
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* @param Size : The number of DMA transfers
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* @param TransferType : Select the transfer controller and the type of transfer. (See, #GPDMA_FLOW_CONTROL_T)
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* @param NextDescriptor : Pointer to next descriptor (0 if no more descriptors available)
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* @return ERROR on error, SUCCESS on success
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*/
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Status Chip_GPDMA_PrepareDescriptor(LPC_GPDMA_T *pGPDMA,
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DMA_TransferDescriptor_t *DMADescriptor,
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uint32_t src,
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uint32_t dst,
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uint32_t Size,
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GPDMA_FLOW_CONTROL_T TransferType,
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const DMA_TransferDescriptor_t *NextDescriptor);
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/**
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* @}
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*/
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#ifdef __cplusplus
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}
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#endif
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#endif /* __GPDMA_18XX_43XX_H_ */
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