292 lines
12 KiB
C
292 lines
12 KiB
C
/****************************************************************************************************//**
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* @file sdio.h
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*
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* @status EXPERIMENTAL
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*
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* @brief Header file for NXP LPC18xx/43xx SDIO driver
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*
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* @version V1.0
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* @date 02. November 2011
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*
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* Software that is described herein is for illustrative purposes only
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* which provides customers with programming information regarding the
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* products. This software is supplied "AS IS" without any warranties.
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* NXP Semiconductors assumes no responsibility or liability for the
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* use of the software, conveys no license or title under any patent,
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* copyright, or mask work right to the product. NXP Semiconductors
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* reserves the right to make changes in the software without
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* notification. NXP Semiconductors also make no representation or
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* warranty that such application will be suitable for the specified
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* use without further testing or modification.
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* Permission to use, copy, modify, and distribute this software and its
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* documentation is hereby granted, under NXP Semiconductors’
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* relevant copyright in the software, without fee, provided that it
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* is used in conjunction with NXP Semiconductors microcontrollers. This
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* copyright, permission, and disclaimer notice must appear in all copies of
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* this code.
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*
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*******************************************************************************************************/
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#ifndef __SDIO_H
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#define __SDIO_H
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/** \defgroup LPCSDMMC_Definitions LPC18xx_43xx SDIO definitions
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This file defines common definitions and values used for SDMMC:
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- Registers, bitfields, and structures
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- Commands and statuses
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- States
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@{
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*/
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/** \brief SDIO chained DMA descriptor
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*/
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typedef struct {
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volatile uint32_t des0; /*!< Control and status */
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volatile uint32_t des1; /*!< Buffer size(s) */
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volatile uint32_t des2; /*!< Buffer address pointer 1 */
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volatile uint32_t des3; /*!< Buffer address pointer 2 */
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} LPC_SDMMC_DMA_Type;
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/** \brief SDIO DMA descriptor control (des0) register defines
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*/
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#define MCI_DMADES0_OWN (1UL<<31) /*!< DMA owns descriptor bit */
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#define MCI_DMADES0_CES (1<<30) /*!< Card Error Summary bit */
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#define MCI_DMADES0_ER (1<<5) /*!< End of descriptopr ring bit */
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#define MCI_DMADES0_CH (1<<4) /*!< Second address chained bit */
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#define MCI_DMADES0_FS (1<<3) /*!< First descriptor bit */
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#define MCI_DMADES0_LD (1<<2) /*!< Last descriptor bit */
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#define MCI_DMADES0_DIC (1<<1) /*!< Disable interrupt on completion bit */
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/** \brief SDIO DMA descriptor size (des1) register defines
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*/
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#define MCI_DMADES1_BS1(x) (x) /*!< Size of buffer 1 */
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#define MCI_DMADES1_BS2(x) ((x) << 13) /*!< Size of buffer 2 */
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#define MCI_DMADES1_MAXTR 4096 /*!< Max transfer size per buffer */
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/** \brief SD/SDIO/MMC control register defines
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*/
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#define MCI_CTRL_USE_INT_DMAC (1<<25) /*!< Use internal DMA */
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#define MCI_CTRL_ENABLE_OD_PUP (1<<24) /*!< Enable external open-drain pullup */
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#define MCI_CTRL_CARDV_B_MASK 0xF00000 /*!< Card regulator-B voltage setting; */
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#define MCI_CTRL_CARDV_A_MASK 0xF0000 /*!< Card regulator-A voltage setting; */
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#define MCI_CTRL_CEATA_INT_EN (1<<11) /*!< Enable CE-ATA interrupts */
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#define MCI_CTRL_SEND_AS_CCSD (1<<10) /*!< Send auto-stop */
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#define MCI_CTRL_SEND_CCSD (1<<9) /*!< Send CCSD */
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#define MCI_CTRL_ABRT_READ_DATA (1<<8) /*!< Abort read data */
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#define MCI_CTRL_SEND_IRQ_RESP (1<<7) /*!< Send auto-IRQ response */
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#define MCI_CTRL_READ_WAIT (1<<6) /*!< Assert read-wait for SDIO */
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#define MCI_CTRL_DMA_ENABLE (1<<5) /*!< Enable DMA transfer mode */
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#define MCI_CTRL_INT_ENABLE (1<<4) /*!< Global interrupt enable */
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#define MCI_CTRL_DMA_RESET (1<<2) /*!< Reset internal DMA */
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#define MCI_CTRL_FIFO_RESET (1<<1) /*!< Reset data FIFO pointers */
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#define MCI_CTRL_RESET (1<<0) /*!< Reset controller */
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/** \brief Power Enable register defines
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*/
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#define MCI_POWER_ENABLE(slot) (1<<(slot)) /*!< Enable slot power signal */
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/** \brief Clock divider register defines
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*/
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#define MCI_CLOCK_DIVIDER(divnum, divby2) ((divby2)<<((divnum) * 8)) /*!< Set slot cklock divider */
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/** \brief Clock source register defines
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*/
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#define MCI_CLKSRC_CLKDIV0 0
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#define MCI_CLKSRC_CLKDIV1 1
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#define MCI_CLKSRC_CLKDIV2 2
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#define MCI_CLKSRC_CLKDIV3 3
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#define MCI_CLK_SOURCE(slot, clksrc) ((clksrc)<<((slot) * 2)) /*!< Set slot cklock divider source */
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/** \brief Clock Enable register defines
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*/
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#define MCI_CLKEN_LOW_PWR(slot) (1<<((slot) + 16)) /*!< Enable clock idle for slot */
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#define MCI_CLKEN_ENABLE(slot) (1<<(slot)) /*!< Enable slot clock */
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/** \brief time-out register defines
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*/
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#define MCI_TMOUT_DATA(clks) ((clks)<<8) /*!< Data timeout clocks */
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#define MCI_TMOUT_DATA_MSK 0xFFFFFF00
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#define MCI_TMOUT_RESP(clks) ((clks) & 0xFF) /*!< Response timeout clocks */
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#define MCI_TMOUT_RESP_MSK 0xFF
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/** \brief card-type register defines
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*/
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#define MCI_CTYPE_8BIT(slot) (1<<((slot) + 16)) /*!< Enable 4-bit mode */
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#define MCI_CTYPE_4BIT(slot) (1<<(slot)) /*!< Enable 8-bit mode */
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/** \brief Bus mode register defines
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*/
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#define MCI_BMOD_PBL1 (0<<8) /*!< Burst length = 1 */
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#define MCI_BMOD_PBL4 (1<<8) /*!< Burst length = 4 */
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#define MCI_BMOD_PBL8 (2<<8) /*!< Burst length = 8 */
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#define MCI_BMOD_PBL16 (3<<8) /*!< Burst length = 16 */
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#define MCI_BMOD_PBL32 (4<<8) /*!< Burst length = 32 */
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#define MCI_BMOD_PBL64 (5<<8) /*!< Burst length = 64 */
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#define MCI_BMOD_PBL128 (6<<8) /*!< Burst length = 128 */
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#define MCI_BMOD_PBL256 (7<<8) /*!< Burst length = 256 */
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#define MCI_BMOD_DE (1<<7) /*!< Enable internal DMAC */
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#define MCI_BMOD_DSL(len) ((len)<<2) /*!< Descriptor skip length */
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#define MCI_BMOD_FB (1<<1) /*!< Fixed bursts */
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#define MCI_BMOD_SWR (1<<0) /*!< Software reset of internal registers */
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/** \brief Interrupt status & mask register defines
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*/
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#define MCI_INT_SDIO(slot) (1<<(slot)) /*!< Slot specific interrupt enable */
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#define MCI_INT_EBE (1<<15) /*!< End-bit error */
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#define MCI_INT_ACD (1<<14) /*!< Auto command done */
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#define MCI_INT_SBE (1<<13) /*!< Start bit error */
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#define MCI_INT_HLE (1<<12) /*!< Hardware locked error */
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#define MCI_INT_FRUN (1<<11) /*!< FIFO overrun/underrun error */
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#define MCI_INT_HTO (1<<10) /*!< Host data starvation error */
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#define MCI_INT_DTO (1<<9) /*!< Data timeout error */
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#define MCI_INT_RTO (1<<8) /*!< Response timeout error */
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#define MCI_INT_DCRC (1<<7) /*!< Data CRC error */
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#define MCI_INT_RCRC (1<<6) /*!< Response CRC error */
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#define MCI_INT_RXDR (1<<5) /*!< RX data ready */
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#define MCI_INT_TXDR (1<<4) /*!< TX data needed */
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#define MCI_INT_DATA_OVER (1<<3) /*!< Data transfer over */
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#define MCI_INT_CMD_DONE (1<<2) /*!< Command done */
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#define MCI_INT_RESP_ERR (1<<1) /*!< Command response error */
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#define MCI_INT_CD (1<<0) /*!< Card detect */
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#define MCI_INT_ERROR 0xbfc2
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/** \brief Command register defines
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*/
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#define MCI_CMD_START (1UL<<31) /*!< Start command */
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#define MCI_CMD_VOLT_SWITCH (1<<28) /*!< Voltage switch bit */
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#define MCI_CMD_BOOT_MODE (1<<27) /*!< Boot mode */
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#define MCI_CMD_DISABLE_BOOT (1<<26) /*!< Disable boot */
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#define MCI_CMD_EXPECT_BOOT_ACK (1<<25) /*!< Expect boot ack */
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#define MCI_CMD_ENABLE_BOOT (1<<24) /*!< Enable boot */
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#define MCI_CMD_CCS_EXP (1<<23) /*!< CCS expected */
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#define MCI_CMD_CEATA_RD (1<<22) /*!< CE-ATA read in progress */
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#define MCI_CMD_UPD_CLK (1<<21) /*!< Update clock register only */
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#define MCI_CMD_CARDNUM 0x1F0000
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#define MCI_CMD_INIT (1<<15) /*!< Send init sequence */
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#define MCI_CMD_STOP (1<<14) /*!< Stop/abort command */
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#define MCI_CMD_PRV_DAT_WAIT (1<<13) /*!< Wait before send */
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#define MCI_CMD_SEND_STOP (1<<12) /*!< Send auto-stop */
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#define MCI_CMD_STRM_MODE (1<<11) /*!< Stream transfer mode */
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#define MCI_CMD_DAT_WR (1<<10) /*!< Read(0)/Write(1) selection */
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#define MCI_CMD_DAT_EXP (1<<9) /*!< Data expected */
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#define MCI_CMD_RESP_CRC (1<<8) /*!< Check response CRC */
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#define MCI_CMD_RESP_LONG (1<<7) /*!< Response length */
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#define MCI_CMD_RESP_EXP (1<<6) /*!< Response expected */
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#define MCI_CMD_INDX(n) ((n) & 0x1F)
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/** \brief status register definess
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*/
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#define MCI_STS_GET_FCNT(x) (((x)>>17) & 0x1FF)
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/** \brief card type defines
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*/
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#define CARD_TYPE_SD (1 << 0)
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#define CARD_TYPE_4BIT (1 << 1)
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#define CARD_TYPE_8BIT (1 << 2)
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#define CARD_TYPE_HC (OCR_HC_CCS) /*!< high capacity card > 2GB */
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/** \brief Commonly used definitions
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*/
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#define MMC_SECTOR_SIZE 512
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#define MCI_FIFO_SZ 32 /*!< Size of SDIO FIFO (32-bit wide) */
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/** \brief Setup options for the SDIO driver
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*/
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#define US_TIMEOUT 1000000 /*!< give 1 atleast 1 sec for the card to respond */
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#define MS_ACQUIRE_DELAY (10) /*!< inter-command acquire oper condition delay in msec*/
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#define INIT_OP_RETRIES 10 /*!< initial OP_COND retries */
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#define SET_OP_RETRIES 200 /*!< set OP_COND retries */
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#define SDIO_BUS_WIDTH 4 /*!< Max bus width supported */
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#define SD_MMC_ENUM_CLOCK 400000 /*!< Typical enumeration clock rate */
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#define MMC_MAX_CLOCK 20000000 /*!< Max MMC clock rate */
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#define MMC_LOW_BUS_MAX_CLOCK 26000000 /*!< Type 0 MMC card max clock rate */
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#define MMC_HIGH_BUS_MAX_CLOCK 52000000 /*!< Type 1 MMC card max clock rate */
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#define SD_MAX_CLOCK 25000000 /*!< Max SD clock rate */
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#define SYS_REG_SD_CARD_DELAY 0x1B /*!< SD card delay (register) */
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#define SYS_REG_MMC_CARD_DELAY 0x16 /*!< MMC card delay (register) */
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/* The SDIO driver can be used in polled or IRQ based modes. In polling
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mode, the driver functions block until complete. In IRQ mode, the
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functions won't block and the status must be checked elsewhere. */
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#define SDIO_USE_POLLING /* non-polling mode does not work yet */
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/* If the following define is enabled, 'double buffer' type DMA descriptors
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will be used instead of chained descriptors. */
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/* Note: Avoid using double buffer mode - is isn't working yet. */
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//#define USE_DMADESC_DBUFF
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/***********************************************************************
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* MCI device structure and it defines
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**********************************************************************/
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typedef struct _mci_card_struct MCI_CARD_INFO_T;
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typedef uint32_t (*MCI_CMD_WAIT_FUNC_T)(MCI_CARD_INFO_T* , uint32_t);
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typedef void (*MCI_IRQ_CB_FUNC_T)(MCI_CARD_INFO_T* , uint32_t);
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struct _mci_card_struct
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{
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uint32_t response[4]; /*!< Most recent response */
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uint32_t cid[4]; /*!< CID of acquired card */
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uint32_t csd[4]; /*!< CSD of acquired card */
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uint32_t ext_csd[MMC_SECTOR_SIZE/4];
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uint32_t card_type;
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uint32_t rca; /*!< Relative address assigned to card */
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uint32_t speed;
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uint32_t block_len;
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uint32_t device_size;
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uint32_t blocknr;
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MCI_CMD_WAIT_FUNC_T wait_func;
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MCI_IRQ_CB_FUNC_T irq_callback;
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};
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/** \brief MCI driver API functions
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*/
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/* Initialize the SDIO controller */
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void sdio_init(MCI_CMD_WAIT_FUNC_T waitfunc,
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MCI_IRQ_CB_FUNC_T irqfunc);
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/* Detect if an SD card is inserted */
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int sdio_card_detect(void);
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/* Detect if write protect is enabled */
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int sdio_card_wp_on(void);
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/* Enable or disable slot power */
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void sdio_power_onoff(int enable);
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void sdio_power_on(void);
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void sdio_power_off(void);
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/* Function to enumerate the SD/MMC/SDHC/MMC+ cards */
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int sdio_acquire(void);
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/* Close the SDIO controller */
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void sdio_deinit(void);
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/* SDIO read function - reads data from a card */
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int sdio_read_blocks(void *buffer,
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int start_block,
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int end_block);
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/* SDIO write function - writes data to a card. After calling this
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function, do not use read or write until the card state has
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left the program state. */
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int sdio_write_blocks(void *buffer,
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int start_block,
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int end_block);
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/* Get card's current state (idle, transfer, program, etc.) */
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int sdio_get_state(void);
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int sdio_get_device_size(void);
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extern uint32_t sdio_clk_rate;
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#ifdef __cplusplus
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}
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#endif
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#endif /* end __SDIO_H */
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/*****************************************************************************
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** End Of File
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******************************************************************************/
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