563 lines
16 KiB
C
563 lines
16 KiB
C
/*
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* The MIT License (MIT)
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*
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* Copyright (c) 2019 Peter Lawrence
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*
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* This file is part of the TinyUSB stack.
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*/
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/*
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Theory of operation:
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The NUC121/NUC125/NUC126 USBD peripheral has eight "EP"s, but each is simplex,
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so two collectively (peripheral nomenclature of "EP0" and "EP1") are needed to
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implement USB EP0. PERIPH_EP0 and PERIPH_EP1 are used by this driver for
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EP0_IN and EP0_OUT respectively. This leaves up to six for user usage.
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*/
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#include "tusb_option.h"
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#if CFG_TUD_ENABLED && ( (CFG_TUSB_MCU == OPT_MCU_NUC121) || (CFG_TUSB_MCU == OPT_MCU_NUC126) )
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#include "device/dcd.h"
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#include "NuMicro.h"
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// Since TinyUSB doesn't use SOF for now, and this interrupt too often (1ms interval)
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// We disable SOF for now until needed later on
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#ifndef USE_SOF
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# define USE_SOF 0
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#endif
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/* allocation of USBD RAM for Setup, EP0_IN, and and EP_OUT */
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#define PERIPH_SETUP_BUF_BASE 0
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#define PERIPH_SETUP_BUF_LEN 8
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#define PERIPH_EP0_BUF_BASE (PERIPH_SETUP_BUF_BASE + PERIPH_SETUP_BUF_LEN)
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#define PERIPH_EP0_BUF_LEN CFG_TUD_ENDPOINT0_SIZE
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#define PERIPH_EP1_BUF_BASE (PERIPH_EP0_BUF_BASE + PERIPH_EP0_BUF_LEN)
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#define PERIPH_EP1_BUF_LEN CFG_TUD_ENDPOINT0_SIZE
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#define PERIPH_EP2_BUF_BASE (PERIPH_EP1_BUF_BASE + PERIPH_EP1_BUF_LEN)
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/* rather important info unfortunately not provided by device include files: how much there is */
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#define USBD_BUF_SIZE ((CFG_TUSB_MCU == OPT_MCU_NUC121) ? 768 : 512)
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enum ep_enum
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{
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PERIPH_EP0 = 0,
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PERIPH_EP1 = 1,
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PERIPH_EP2 = 2,
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PERIPH_EP3 = 3,
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PERIPH_EP4 = 4,
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PERIPH_EP5 = 5,
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PERIPH_EP6 = 6,
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PERIPH_EP7 = 7,
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PERIPH_MAX_EP,
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};
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/* reset by dcd_init(), this is used by dcd_edpt_open() to assign USBD peripheral buffer addresses */
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static uint32_t bufseg_addr;
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/* used by dcd_edpt_xfer() and the ISR to reset the data sync (DATA0/DATA1) in an EP0_IN transfer */
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static bool active_ep0_xfer;
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/* RAM table needed to track ongoing transfers performed by dcd_edpt_xfer(), dcd_in_xfer(), and the ISR */
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static struct xfer_ctl_t
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{
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uint8_t *data_ptr; /* data_ptr tracks where to next copy data to (for OUT) or from (for IN) */
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// tu_fifo_t * ff; // TODO support dcd_edpt_xfer_fifo API
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union {
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uint16_t in_remaining_bytes; /* for IN endpoints, we track how many bytes are left to transfer */
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uint16_t out_bytes_so_far; /* but for OUT endpoints, we track how many bytes we've transferred so far */
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};
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uint16_t max_packet_size; /* needed since device driver only finds out this at runtime */
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uint16_t total_bytes; /* quantity needed to pass as argument to dcd_event_xfer_complete() (for IN endpoints) */
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} xfer_table[PERIPH_MAX_EP];
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/*
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local helper functions
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*/
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static void usb_attach(void)
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{
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USBD->SE0 &= ~USBD_SE0_SE0_Msk;
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}
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static void usb_detach(void)
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{
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USBD->SE0 |= USBD_SE0_SE0_Msk;
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}
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static inline void usb_memcpy(uint8_t *dest, uint8_t *src, uint16_t size)
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{
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while(size--) *dest++ = *src++;
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}
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static void usb_control_send_zlp(void)
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{
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USBD->EP[PERIPH_EP0].CFG |= USBD_CFG_DSQSYNC_Msk;
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USBD->EP[PERIPH_EP0].MXPLD = 0;
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}
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/* reconstruct ep_addr from particular USB Configuration Register */
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static uint8_t decode_ep_addr(USBD_EP_T *ep)
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{
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uint8_t ep_addr = ep->CFG & USBD_CFG_EPNUM_Msk;
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if ( USBD_CFG_EPMODE_IN == (ep->CFG & USBD_CFG_STATE_Msk) )
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ep_addr |= TUSB_DIR_IN_MASK;
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return ep_addr;
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}
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/* map 8-bit ep_addr into peripheral endpoint index (PERIPH_EP0...) */
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static USBD_EP_T *ep_entry(uint8_t ep_addr, bool add)
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{
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USBD_EP_T *ep;
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enum ep_enum ep_index;
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for (ep_index = PERIPH_EP0, ep = USBD->EP; ep_index < PERIPH_MAX_EP; ep_index++, ep++)
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{
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if (add)
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{
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/* take first peripheral endpoint that is unused */
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if (0 == (ep->CFG & USBD_CFG_STATE_Msk)) return ep;
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}
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else
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{
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/* find a peripheral endpoint that matches ep_addr */
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uint8_t candidate_ep_addr = decode_ep_addr(ep);
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if (candidate_ep_addr == ep_addr) return ep;
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}
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}
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return NULL;
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}
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/* perform an IN endpoint transfer; this is called by dcd_edpt_xfer() and the ISR */
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static void dcd_in_xfer(struct xfer_ctl_t *xfer, USBD_EP_T *ep)
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{
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uint16_t bytes_now = tu_min16(xfer->in_remaining_bytes, xfer->max_packet_size);
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#if 0 // TODO support dcd_edpt_xfer_fifo API
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if (xfer->ff)
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{
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tu_fifo_read_n(xfer->ff, (void *) (USBD_BUF_BASE + ep->BUFSEG), bytes_now);
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}
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else
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#endif
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{
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// USB SRAM seems to only support byte access and memcpy could possibly do it by words
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usb_memcpy((uint8_t *)(USBD_BUF_BASE + ep->BUFSEG), xfer->data_ptr, bytes_now);
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}
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ep->MXPLD = bytes_now;
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}
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/* called by dcd_init() as well as by the ISR during a USB bus reset */
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static void bus_reset(void)
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{
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USBD->STBUFSEG = PERIPH_SETUP_BUF_BASE;
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for (enum ep_enum ep_index = PERIPH_EP0; ep_index < PERIPH_MAX_EP; ep_index++)
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{
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USBD->EP[ep_index].CFG = 0;
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USBD->EP[ep_index].CFGP = 0;
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}
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/* allocate the default EP0 endpoints */
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USBD->EP[PERIPH_EP0].CFG = USBD_CFG_CSTALL_Msk | USBD_CFG_EPMODE_IN;
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USBD->EP[PERIPH_EP0].BUFSEG = PERIPH_EP0_BUF_BASE;
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xfer_table[PERIPH_EP0].max_packet_size = PERIPH_EP0_BUF_LEN;
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USBD->EP[PERIPH_EP1].CFG = USBD_CFG_CSTALL_Msk | USBD_CFG_EPMODE_OUT;
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USBD->EP[PERIPH_EP1].BUFSEG = PERIPH_EP1_BUF_BASE;
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xfer_table[PERIPH_EP1].max_packet_size = PERIPH_EP1_BUF_LEN;
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/* USB RAM beyond what we've allocated above is available to the user */
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bufseg_addr = PERIPH_EP2_BUF_BASE;
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/* Reset USB device address */
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USBD->FADDR = 0;
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/* reset EP0_IN flag */
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active_ep0_xfer = false;
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}
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/* centralized location for USBD interrupt enable bit mask */
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enum {
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ENABLED_IRQS = USBD_INTSTS_VBDETIF_Msk | USBD_INTSTS_BUSIF_Msk | USBD_INTSTS_SETUP_Msk |
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USBD_INTSTS_USBIF_Msk | (USE_SOF ? USBD_INTSTS_SOFIF_Msk : 0)
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};
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/*
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NUC121/NUC125/NUC126 TinyUSB API driver implementation
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*/
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void dcd_init(uint8_t rhport)
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{
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(void) rhport;
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#ifdef SUPPORT_LPM
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USBD->ATTR = 0x7D0 | USBD_LPMACK;
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#else
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USBD->ATTR = 0x7D0;
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#endif
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usb_detach();
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bus_reset();
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usb_attach();
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USBD->INTSTS = ENABLED_IRQS;
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USBD->INTEN = ENABLED_IRQS;
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}
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void dcd_int_enable(uint8_t rhport)
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{
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(void) rhport;
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NVIC_EnableIRQ(USBD_IRQn);
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}
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void dcd_int_disable(uint8_t rhport)
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{
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(void) rhport;
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NVIC_DisableIRQ(USBD_IRQn);
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}
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void dcd_set_address(uint8_t rhport, uint8_t dev_addr)
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{
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(void) rhport;
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(void) dev_addr;
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usb_control_send_zlp(); /* SET_ADDRESS is the one exception where TinyUSB doesn't use dcd_edpt_xfer() to generate a ZLP */
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// DCD can only set address after status for this request is complete.
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// do it at dcd_edpt0_status_complete()
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}
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static void remote_wakeup_delay(void)
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{
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// try to delay for 1 ms
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uint32_t count = SystemCoreClock / 1000;
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while(count--) __NOP();
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}
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void dcd_remote_wakeup(uint8_t rhport)
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{
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(void) rhport;
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// Enable PHY before sending Resume('K') state
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USBD->ATTR |= USBD_ATTR_PHYEN_Msk;
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USBD->ATTR |= USBD_ATTR_RWAKEUP_Msk;
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// Per specs: remote wakeup signal bit must be clear within 1-15ms
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remote_wakeup_delay();
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USBD->ATTR &=~USBD_ATTR_RWAKEUP_Msk;
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}
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bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc)
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{
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(void) rhport;
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USBD_EP_T *ep = ep_entry(p_endpoint_desc->bEndpointAddress, true);
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TU_ASSERT(ep);
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/* mine the data for the information we need */
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int const dir = tu_edpt_dir(p_endpoint_desc->bEndpointAddress);
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int const size = tu_edpt_packet_size(p_endpoint_desc);
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tusb_xfer_type_t const type = (tusb_xfer_type_t) p_endpoint_desc->bmAttributes.xfer;
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struct xfer_ctl_t *xfer = &xfer_table[ep - USBD->EP];
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/* allocate buffer from USB RAM */
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ep->BUFSEG = bufseg_addr;
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bufseg_addr += size;
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TU_ASSERT(bufseg_addr <= USBD_BUF_SIZE);
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/* construct USB Configuration Register value and then write it */
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uint32_t cfg = tu_edpt_number(p_endpoint_desc->bEndpointAddress);
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cfg |= (TUSB_DIR_IN == dir) ? USBD_CFG_EPMODE_IN : USBD_CFG_EPMODE_OUT;
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if (TUSB_XFER_ISOCHRONOUS == type)
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cfg |= USBD_CFG_TYPE_ISO;
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ep->CFG = cfg;
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/* make a note of the endpoint size */
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xfer->max_packet_size = size;
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return true;
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}
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void dcd_edpt_close_all (uint8_t rhport)
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{
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(void) rhport;
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// TODO implement dcd_edpt_close_all()
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}
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bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t *buffer, uint16_t total_bytes)
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{
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(void) rhport;
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/* mine the data for the information we need */
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tusb_dir_t dir = tu_edpt_dir(ep_addr);
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USBD_EP_T *ep = ep_entry(ep_addr, false);
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struct xfer_ctl_t *xfer = &xfer_table[ep - USBD->EP];
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/* store away the information we'll needing now and later */
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xfer->data_ptr = buffer;
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// xfer->ff = NULL; // TODO support dcd_edpt_xfer_fifo API
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xfer->in_remaining_bytes = total_bytes;
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xfer->total_bytes = total_bytes;
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/* for the first of one or more EP0_IN packets in a message, the first must be DATA1 */
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if ( (0x80 == ep_addr) && !active_ep0_xfer ) ep->CFG |= USBD_CFG_DSQSYNC_Msk;
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if (TUSB_DIR_IN == dir)
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{
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dcd_in_xfer(xfer, ep);
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}
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else
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{
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xfer->out_bytes_so_far = 0;
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ep->MXPLD = xfer->max_packet_size;
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}
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return true;
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}
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#if 0 // TODO support dcd_edpt_xfer_fifo API
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bool dcd_edpt_xfer_fifo (uint8_t rhport, uint8_t ep_addr, tu_fifo_t * ff, uint16_t total_bytes)
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{
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(void) rhport;
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/* mine the data for the information we need */
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tusb_dir_t dir = tu_edpt_dir(ep_addr);
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USBD_EP_T *ep = ep_entry(ep_addr, false);
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struct xfer_ctl_t *xfer = &xfer_table[ep - USBD->EP];
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/* store away the information we'll needing now and later */
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xfer->data_ptr = NULL; // Indicates a FIFO shall be used
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xfer->ff = ff;
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xfer->in_remaining_bytes = total_bytes;
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xfer->total_bytes = total_bytes;
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if (TUSB_DIR_IN == dir)
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{
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dcd_in_xfer(xfer, ep);
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}
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else
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{
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xfer->out_bytes_so_far = 0;
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ep->MXPLD = xfer->max_packet_size;
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}
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return true;
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}
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#endif
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void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr)
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{
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(void) rhport;
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USBD_EP_T *ep = ep_entry(ep_addr, false);
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ep->CFGP |= USBD_CFGP_SSTALL_Msk;
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}
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void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr)
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{
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(void) rhport;
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USBD_EP_T *ep = ep_entry(ep_addr, false);
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ep->CFG = (ep->CFG & ~USBD_CFG_DSQSYNC_Msk) | USBD_CFG_CSTALL_Msk;
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}
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void dcd_int_handler(uint8_t rhport)
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{
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(void) rhport;
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// Mask non-enabled irqs, ex. SOF
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uint32_t status = USBD->INTSTS & (ENABLED_IRQS | 0xffffff00);
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#ifdef SUPPORT_LPM
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uint32_t state = USBD->ATTR & 0x300f;
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#else
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uint32_t state = USBD->ATTR & 0xf;
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#endif
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if(status & USBD_INTSTS_VBDETIF_Msk)
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{
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if(USBD->VBUSDET & USBD_VBUSDET_VBUSDET_Msk)
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{
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/* USB connect */
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USBD->ATTR |= USBD_ATTR_USBEN_Msk | USBD_ATTR_PHYEN_Msk;
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}
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else
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{
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/* USB disconnect */
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USBD->ATTR &= ~USBD_ATTR_USBEN_Msk;
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}
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}
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if(status & USBD_INTSTS_BUSIF_Msk)
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{
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if(state & USBD_ATTR_USBRST_Msk)
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{
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/* USB bus reset */
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USBD->ATTR |= USBD_ATTR_USBEN_Msk | USBD_ATTR_PHYEN_Msk;
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bus_reset();
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dcd_event_bus_reset(0, TUSB_SPEED_FULL, true);
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}
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if(state & USBD_ATTR_SUSPEND_Msk)
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{
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/* Enable USB but disable PHY */
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USBD->ATTR &= ~USBD_ATTR_PHYEN_Msk;
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dcd_event_bus_signal(0, DCD_EVENT_SUSPEND, true);
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}
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if(state & USBD_ATTR_RESUME_Msk)
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{
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/* Enable USB and enable PHY */
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USBD->ATTR |= USBD_ATTR_USBEN_Msk | USBD_ATTR_PHYEN_Msk;
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dcd_event_bus_signal(0, DCD_EVENT_RESUME, true);
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}
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}
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if(status & USBD_INTSTS_SETUP_Msk)
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{
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/* clear the data ready flag of control endpoints */
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USBD->EP[PERIPH_EP0].CFGP |= USBD_CFGP_CLRRDY_Msk;
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USBD->EP[PERIPH_EP1].CFGP |= USBD_CFGP_CLRRDY_Msk;
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/* get SETUP packet from USB buffer */
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dcd_event_setup_received(0, (uint8_t *)USBD_BUF_BASE, true);
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}
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if(status & USBD_INTSTS_USBIF_Msk)
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{
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if (status & USBD_INTSTS_EPEVT0_Msk) /* PERIPH_EP0 (EP0_IN) event: this is treated separately from the rest */
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{
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uint16_t const available_bytes = USBD->EP[PERIPH_EP0].MXPLD;
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active_ep0_xfer = (available_bytes == xfer_table[PERIPH_EP0].max_packet_size);
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dcd_event_xfer_complete(0, 0x80, available_bytes, XFER_RESULT_SUCCESS, true);
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}
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/* service PERIPH_EP1 through PERIPH_EP7 */
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enum ep_enum ep_index;
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uint32_t mask;
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struct xfer_ctl_t *xfer;
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USBD_EP_T *ep;
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for (ep_index = PERIPH_EP1, mask = USBD_INTSTS_EPEVT1_Msk, xfer = &xfer_table[PERIPH_EP1], ep = &USBD->EP[PERIPH_EP1]; ep_index <= PERIPH_EP7; ep_index++, mask <<= 1, xfer++, ep++)
|
|
{
|
|
if(status & mask)
|
|
{
|
|
USBD->INTSTS = mask;
|
|
|
|
uint16_t const available_bytes = ep->MXPLD;
|
|
uint8_t const ep_addr = decode_ep_addr(ep);
|
|
bool const out_ep = !(ep_addr & TUSB_DIR_IN_MASK);
|
|
|
|
if (out_ep)
|
|
{
|
|
/* copy the data from the PC to the previously provided buffer */
|
|
#if 0 // TODO support dcd_edpt_xfer_fifo API
|
|
if (xfer->ff)
|
|
{
|
|
tu_fifo_write_n(xfer->ff, (const void *) (USBD_BUF_BASE + ep->BUFSEG), available_bytes);
|
|
}
|
|
else
|
|
#endif
|
|
{
|
|
// USB SRAM seems to only support byte access and memcpy could possibly do it by words
|
|
usb_memcpy(xfer->data_ptr, (uint8_t *)(USBD_BUF_BASE + ep->BUFSEG), available_bytes);
|
|
xfer->data_ptr += available_bytes;
|
|
}
|
|
|
|
xfer->out_bytes_so_far += available_bytes;
|
|
|
|
/* when the transfer is finished, alert TinyUSB; otherwise, accept more data */
|
|
if ( (xfer->total_bytes == xfer->out_bytes_so_far) || (available_bytes < xfer->max_packet_size) )
|
|
dcd_event_xfer_complete(0, ep_addr, xfer->out_bytes_so_far, XFER_RESULT_SUCCESS, true);
|
|
else
|
|
ep->MXPLD = xfer->max_packet_size;
|
|
}
|
|
else
|
|
{
|
|
/* update the bookkeeping to reflect the data that has now been sent to the PC */
|
|
xfer->in_remaining_bytes -= available_bytes;
|
|
xfer->data_ptr += available_bytes;
|
|
|
|
/* if more data to send, send it; otherwise, alert TinyUSB that we've finished */
|
|
if (xfer->in_remaining_bytes)
|
|
dcd_in_xfer(xfer, ep);
|
|
else
|
|
dcd_event_xfer_complete(0, ep_addr, xfer->total_bytes, XFER_RESULT_SUCCESS, true);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
if(status & USBD_INTSTS_SOFIF_Msk)
|
|
{
|
|
/* Start-Of-Frame event */
|
|
dcd_event_bus_signal(0, DCD_EVENT_SOF, true);
|
|
}
|
|
|
|
/* acknowledge all interrupts */
|
|
USBD->INTSTS = status & ENABLED_IRQS;
|
|
}
|
|
|
|
// Invoked when a control transfer's status stage is complete.
|
|
// May help DCD to prepare for next control transfer, this API is optional.
|
|
void dcd_edpt0_status_complete(uint8_t rhport, tusb_control_request_t const * request)
|
|
{
|
|
(void) rhport;
|
|
|
|
if (request->bmRequestType_bit.recipient == TUSB_REQ_RCPT_DEVICE &&
|
|
request->bmRequestType_bit.type == TUSB_REQ_TYPE_STANDARD &&
|
|
request->bRequest == TUSB_REQ_SET_ADDRESS )
|
|
{
|
|
uint8_t const dev_addr = (uint8_t) request->wValue;
|
|
|
|
// Setting new address after the whole request is complete
|
|
USBD->FADDR = dev_addr;
|
|
}
|
|
}
|
|
|
|
void dcd_disconnect(uint8_t rhport)
|
|
{
|
|
(void) rhport;
|
|
usb_detach();
|
|
}
|
|
|
|
void dcd_connect(uint8_t rhport)
|
|
{
|
|
(void) rhport;
|
|
usb_attach();
|
|
}
|
|
|
|
void dcd_sof_enable(uint8_t rhport, bool en)
|
|
{
|
|
(void) rhport;
|
|
(void) en;
|
|
|
|
// TODO implement later
|
|
}
|
|
|
|
#endif
|