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<div class="title">ehci_qhd_t Struct Reference<div class="ingroups"><a class="el" href="group___e_h_c_i.html">EHCI</a></div></div> </div>
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<p>Queue Head (section 3.6)
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<a href="structehci__qhd__t.html#details">More...</a></p>
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<p><code>#include <<a class="el" href="ehci_8h_source.html">ehci.h</a>></code></p>
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<table class="memberdecls">
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<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="pub-attribs"></a>
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Data Fields</h2></td></tr>
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<tr class="memitem:a8f18d97ad3c8b23a16c6b07c3ce58113"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a8f18d97ad3c8b23a16c6b07c3ce58113"></a>
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<a class="el" href="unionehci__link__t.html">ehci_link_t</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structehci__qhd__t.html#a8f18d97ad3c8b23a16c6b07c3ce58113">next</a></td></tr>
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<tr class="memdesc:a8f18d97ad3c8b23a16c6b07c3ce58113"><td class="mdescLeft"> </td><td class="mdescRight">Word 0: Queue Head Horizontal Link Pointer. <br/></td></tr>
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<tr class="separator:a8f18d97ad3c8b23a16c6b07c3ce58113"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a5e961d126e4339cdfa5a69e8ad877a46"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structehci__qhd__t.html#a5e961d126e4339cdfa5a69e8ad877a46">device_address</a>: 7</td></tr>
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<tr class="memdesc:a5e961d126e4339cdfa5a69e8ad877a46"><td class="mdescLeft"> </td><td class="mdescRight">Word 1 : Endpoint Characteristics. <a href="#a5e961d126e4339cdfa5a69e8ad877a46">More...</a><br/></td></tr>
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<tr class="separator:a5e961d126e4339cdfa5a69e8ad877a46"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:afd4670b18165eca38c5aab7e1e365c36"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="afd4670b18165eca38c5aab7e1e365c36"></a>
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uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structehci__qhd__t.html#afd4670b18165eca38c5aab7e1e365c36">non_hs_period_inactive_next_xact</a>: 1</td></tr>
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<tr class="memdesc:afd4670b18165eca38c5aab7e1e365c36"><td class="mdescLeft"> </td><td class="mdescRight">This bit is used by system software to request that the host controller set the Active bit to zero. See Section 4.12.2.5 for full operational details. <br/></td></tr>
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<tr class="memitem:a8ece0acb43021a17c4368c5580b537f4"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a8ece0acb43021a17c4368c5580b537f4"></a>
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uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structehci__qhd__t.html#a8ece0acb43021a17c4368c5580b537f4">endpoint_number</a>: 4</td></tr>
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<tr class="memdesc:a8ece0acb43021a17c4368c5580b537f4"><td class="mdescLeft"> </td><td class="mdescRight">This 4-bit field selects the particular endpoint number on the device serving as the data source or sink. <br/></td></tr>
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<tr class="separator:a8ece0acb43021a17c4368c5580b537f4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a4fa561d2dc9d0fa4c4e3a1a5cd52e0f5"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a4fa561d2dc9d0fa4c4e3a1a5cd52e0f5"></a>
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uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structehci__qhd__t.html#a4fa561d2dc9d0fa4c4e3a1a5cd52e0f5">endpoint_speed</a>: 2</td></tr>
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<tr class="memdesc:a4fa561d2dc9d0fa4c4e3a1a5cd52e0f5"><td class="mdescLeft"> </td><td class="mdescRight">This is the speed of the associated endpoint 00b=Full 01b=Low 10b=High 11b=Reserved. <br/></td></tr>
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<tr class="memitem:a480c98472730d78702010ab74152003b"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a480c98472730d78702010ab74152003b"></a>
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uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structehci__qhd__t.html#a480c98472730d78702010ab74152003b">data_toggle_control</a>: 1</td></tr>
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<tr class="memdesc:a480c98472730d78702010ab74152003b"><td class="mdescLeft"> </td><td class="mdescRight">This bit specifies where the host controller should get the initial data toggle on an overlay transition. 0b=Ignore DT bit of qTD, 1b=Use DT bit of qTD. <br/></td></tr>
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<tr class="memitem:a21fefa6cf4a25779826f13c7c91d00ab"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a21fefa6cf4a25779826f13c7c91d00ab"></a>
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uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structehci__qhd__t.html#a21fefa6cf4a25779826f13c7c91d00ab">head_list_flag</a>: 1</td></tr>
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<tr class="memdesc:a21fefa6cf4a25779826f13c7c91d00ab"><td class="mdescLeft"> </td><td class="mdescRight">This bit is set by System Software to mark a queue head as being the head of the reclamation list. See Section 4.8 for operational model. <br/></td></tr>
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<tr class="memitem:ad55818a81c7231005bf4853be413fa51"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ad55818a81c7231005bf4853be413fa51"></a>
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uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structehci__qhd__t.html#ad55818a81c7231005bf4853be413fa51">max_package_size</a>: 11</td></tr>
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<tr class="memdesc:ad55818a81c7231005bf4853be413fa51"><td class="mdescLeft"> </td><td class="mdescRight">This directly corresponds to the maximum packet size of the associated endpoint (wMaxPacketSize) <br/></td></tr>
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<tr class="memitem:a3c1209ca551e4338a312c65a138f6c1c"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a3c1209ca551e4338a312c65a138f6c1c"></a>
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uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structehci__qhd__t.html#a3c1209ca551e4338a312c65a138f6c1c">non_hs_control_endpoint</a>: 1</td></tr>
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<tr class="memdesc:a3c1209ca551e4338a312c65a138f6c1c"><td class="mdescLeft"> </td><td class="mdescRight">If the QH.EPSfield indicates the endpoint is not a high-speed device, and the endpoint is an control endpoint, then software must set this bit to a one. Otherwise it should always set this bit to a zero. <br/></td></tr>
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<tr class="memitem:aee0c90ac76fc369c57de5ed8e1c44d22"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="aee0c90ac76fc369c57de5ed8e1c44d22"></a>
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uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structehci__qhd__t.html#aee0c90ac76fc369c57de5ed8e1c44d22">nak_count_reload</a>: 4</td></tr>
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<tr class="memdesc:aee0c90ac76fc369c57de5ed8e1c44d22"><td class="mdescLeft"> </td><td class="mdescRight">This field contains a value, which is used by the host controller to reload the Nak Counter field. <br/></td></tr>
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uint32_t </td><td class="memItemRight" valign="bottom"><b>__pad0__</b>: 0</td></tr>
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<tr class="separator:a3e57c2ef1c3ffb36722f000cc1156824"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a2a2a839a2af77a8364cf30a2fb6623eb"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structehci__qhd__t.html#a2a2a839a2af77a8364cf30a2fb6623eb">interrupt_smask</a>: 8</td></tr>
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<tr class="memdesc:a2a2a839a2af77a8364cf30a2fb6623eb"><td class="mdescLeft"> </td><td class="mdescRight">Word 2 : Endpoint Capabilities. <a href="#a2a2a839a2af77a8364cf30a2fb6623eb">More...</a><br/></td></tr>
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<tr class="memitem:a50195a9b2e4e35a821c66bc7f4957336"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a50195a9b2e4e35a821c66bc7f4957336"></a>
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uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structehci__qhd__t.html#a50195a9b2e4e35a821c66bc7f4957336">non_hs_interrupt_cmask</a>: 8</td></tr>
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<tr class="memdesc:a50195a9b2e4e35a821c66bc7f4957336"><td class="mdescLeft"> </td><td class="mdescRight">This field is ignored by the host controller unless the EPSfield indicates this device is a low- or full-speed device and this queue head is in the periodic list. This field (along with the Activeand SplitX-statefields) is used to determine during which micro-frames the host controller should execute a complete-split transaction. <br/></td></tr>
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<tr class="memitem:a3e65707a3c47fda14d6c69f2e49a1c2f"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a3e65707a3c47fda14d6c69f2e49a1c2f"></a>
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uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structehci__qhd__t.html#a3e65707a3c47fda14d6c69f2e49a1c2f">hub_address</a>: 7</td></tr>
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<tr class="memdesc:a3e65707a3c47fda14d6c69f2e49a1c2f"><td class="mdescLeft"> </td><td class="mdescRight">This field is ignored by the host controller unless the EPSfield indicates a full- or low-speed device. The value is the USB device address of the USB 2.0 Hub below which the full- or low-speed device associated with this endpoint is attached. This field is used in the split-transaction protocol. See Section 4.12. <br/></td></tr>
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<tr class="memitem:a0c40895e72c535540d39eab88b4eb88e"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a0c40895e72c535540d39eab88b4eb88e"></a>
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uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structehci__qhd__t.html#a0c40895e72c535540d39eab88b4eb88e">hub_port</a>: 7</td></tr>
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<tr class="memdesc:a0c40895e72c535540d39eab88b4eb88e"><td class="mdescLeft"> </td><td class="mdescRight">This field is ignored by the host controller unless the EPSfield indicates a full- or low-speed device. The value is the port number identifier on the USB 2.0 Hub (for hub at device address Hub Addrbelow), below which the full- or low-speed device associated with this endpoint is attached. This information is used in the split-transaction protocol. See Section 4.12. <br/></td></tr>
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uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structehci__qhd__t.html#aa7883b4c0e8f4770d654c03e18cfe00f">mult</a>: 2</td></tr>
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<tr class="memdesc:aa7883b4c0e8f4770d654c03e18cfe00f"><td class="mdescLeft"> </td><td class="mdescRight">This field is a multiplier used to key the host controller as the number of successive packets the host controller may submit to the endpoint in the current execution. 00b=Reserved 01b,10b,11b= 1 (2, 3) Transaction for this endpoint/micro frame. <br/></td></tr>
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uint32_t </td><td class="memItemRight" valign="bottom"><b>__pad1__</b>: 0</td></tr>
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volatile uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structehci__qhd__t.html#acd25df2a0b360a90b8f4337f42965155">qtd_addr</a></td></tr>
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<tr class="memdesc:acd25df2a0b360a90b8f4337f42965155"><td class="mdescLeft"> </td><td class="mdescRight">Word 3: Current qTD Pointer. <br/></td></tr>
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volatile <a class="el" href="structehci__qtd__t.html">ehci_qtd_t</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structehci__qhd__t.html#a521a53b806cafcb364cb0c161bcac87e">qtd_overlay</a></td></tr>
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<tr class="memdesc:a521a53b806cafcb364cb0c161bcac87e"><td class="mdescLeft"> </td><td class="mdescRight">Word 4-11: Transfer Overlay. <br/></td></tr>
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<tr class="memitem:a4b1141237b480e4c38afe96a59ca4cad"><td class="memItemLeft" align="right" valign="top">uint8_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structehci__qhd__t.html#a4b1141237b480e4c38afe96a59ca4cad">used</a></td></tr>
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<tr class="memdesc:a4b1141237b480e4c38afe96a59ca4cad"><td class="mdescLeft"> </td><td class="mdescRight">thus there are 16 bytes padding free that we can make use of. <a href="#a4b1141237b480e4c38afe96a59ca4cad">More...</a><br/></td></tr>
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uint8_t </td><td class="memItemRight" valign="bottom"><b>is_removing</b></td></tr>
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uint8_t </td><td class="memItemRight" valign="bottom"><b>pid_non_control</b></td></tr>
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uint8_t </td><td class="memItemRight" valign="bottom"><b>class_code</b></td></tr>
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uint16_t </td><td class="memItemRight" valign="bottom"><b>total_xferred_bytes</b></td></tr>
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uint8_t </td><td class="memItemRight" valign="bottom"><b>interval_ms</b></td></tr>
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uint8_t </td><td class="memItemRight" valign="bottom"><b>reserved</b></td></tr>
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<a class="el" href="structehci__qtd__t.html">ehci_qtd_t</a> *volatile </td><td class="memItemRight" valign="bottom"><b>p_qtd_list_head</b></td></tr>
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<a class="el" href="structehci__qtd__t.html">ehci_qtd_t</a> *volatile </td><td class="memItemRight" valign="bottom"><b>p_qtd_list_tail</b></td></tr>
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</table>
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<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2>
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<div class="textblock"><p>Queue Head (section 3.6) </p>
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<p>Definition at line <a class="el" href="ehci_8h_source.html#l00156">156</a> of file <a class="el" href="ehci_8h_source.html">ehci.h</a>.</p>
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</div><h2 class="groupheader">Field Documentation</h2>
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<td class="memname">uint32_t device_address</td>
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<p>Word 1 : Endpoint Characteristics. </p>
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<p>This field selects the specific device serving as the data source or sink </p>
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<p>Definition at line <a class="el" href="ehci_8h_source.html#l00161">161</a> of file <a class="el" href="ehci_8h_source.html">ehci.h</a>.</p>
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<td class="memname">uint32_t interrupt_smask</td>
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</div><div class="memdoc">
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<p>Word 2 : Endpoint Capabilities. </p>
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<p>This field is used for all endpoint speeds. Software should set this field to a zero when the queue head is on the asynchronous schedule. A non-zero value in this field indicates an interrupt endpoint </p>
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<p>Definition at line <a class="el" href="ehci_8h_source.html#l00174">174</a> of file <a class="el" href="ehci_8h_source.html">ehci.h</a>.</p>
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<td class="memname">uint8_t used</td>
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</div><div class="memdoc">
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<p>thus there are 16 bytes padding free that we can make use of. </p>
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<p>Due to the fact QHD is 32 bytes aligned but occupies only 48 bytes </p>
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<p>Definition at line <a class="el" href="ehci_8h_source.html#l00192">192</a> of file <a class="el" href="ehci_8h_source.html">ehci.h</a>.</p>
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</div>
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<hr/>The documentation for this struct was generated from the following file:<ul>
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<li>tinyusb/host/ehci/<a class="el" href="ehci_8h_source.html">ehci.h</a></li>
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<li class="navelem"><a class="el" href="structehci__qhd__t.html">ehci_qhd_t</a></li>
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<li class="footer">Generated on Thu Apr 17 2014 13:05:30 for tinyusb by
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<a href="http://www.doxygen.org/index.html">
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<img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.8.6 </li>
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