137 lines
5.1 KiB
C
137 lines
5.1 KiB
C
/*
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* The MIT License (MIT)
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*
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* Copyright (c) 2021, Ha Thach (tinyusb.org)
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*
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* This file is part of the TinyUSB stack.
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*/
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#ifndef COMMON_TRANSDIMENSION_H_
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#define COMMON_TRANSDIMENSION_H_
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#ifdef __cplusplus
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extern "C" {
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#endif
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// USBCMD
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enum {
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USBCMD_RUN_STOP = TU_BIT(0),
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USBCMD_RESET = TU_BIT(1),
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USBCMD_SETUP_TRIPWIRE = TU_BIT(13),
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USBCMD_ADD_QTD_TRIPWIRE = TU_BIT(14) ///< This bit is used as a semaphore to ensure the to proper addition of a new dTD to an active (primed) endpoint’s linked list. This bit is set and cleared by software during the process of adding a new dTD
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// Interrupt Threshold bit 23:16
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};
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// PORTSC1
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#define PORTSC1_PORT_SPEED_POS 26
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enum {
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PORTSC1_CURRENT_CONNECT_STATUS = TU_BIT(0),
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PORTSC1_FORCE_PORT_RESUME = TU_BIT(6),
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PORTSC1_SUSPEND = TU_BIT(7),
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PORTSC1_FORCE_FULL_SPEED = TU_BIT(24),
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PORTSC1_PORT_SPEED = TU_BIT(26) | TU_BIT(27)
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};
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// OTGSC
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enum {
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OTGSC_VBUS_DISCHARGE = TU_BIT(0),
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OTGSC_VBUS_CHARGE = TU_BIT(1),
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// OTGSC_HWASSIST_AUTORESET = TU_BIT(2),
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OTGSC_OTG_TERMINATION = TU_BIT(3), ///< Must set to 1 when OTG go to device mode
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OTGSC_DATA_PULSING = TU_BIT(4),
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OTGSC_ID_PULLUP = TU_BIT(5),
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// OTGSC_HWASSIT_DATA_PULSE = TU_BIT(6),
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// OTGSC_HWASSIT_BDIS_ACONN = TU_BIT(7),
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OTGSC_ID = TU_BIT(8), ///< 0 = A device, 1 = B Device
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OTGSC_A_VBUS_VALID = TU_BIT(9),
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OTGSC_A_SESSION_VALID = TU_BIT(10),
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OTGSC_B_SESSION_VALID = TU_BIT(11),
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OTGSC_B_SESSION_END = TU_BIT(12),
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OTGSC_1MS_TOGGLE = TU_BIT(13),
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OTGSC_DATA_BUS_PULSING_STATUS = TU_BIT(14),
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};
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// USBMode
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enum {
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USBMODE_CM_DEVICE = 2,
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USBMODE_CM_HOST = 3,
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USBMODE_SLOM = TU_BIT(3),
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USBMODE_SDIS = TU_BIT(4),
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USBMODE_VBUS_POWER_SELECT = TU_BIT(5), // Need to be enabled for LPC18XX/43XX in host mode
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};
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// Device Registers
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typedef struct
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{
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//------------- ID + HW Parameter Registers-------------//
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__I uint32_t TU_RESERVED[64]; ///< For iMX RT10xx, but not used by LPC18XX/LPC43XX
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//------------- Capability Registers-------------//
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__I uint8_t CAPLENGTH; ///< Capability Registers Length
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__I uint8_t TU_RESERVED[1];
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__I uint16_t HCIVERSION; ///< Host Controller Interface Version
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__I uint32_t HCSPARAMS; ///< Host Controller Structural Parameters
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__I uint32_t HCCPARAMS; ///< Host Controller Capability Parameters
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__I uint32_t TU_RESERVED[5];
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__I uint16_t DCIVERSION; ///< Device Controller Interface Version
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__I uint8_t TU_RESERVED[2];
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__I uint32_t DCCPARAMS; ///< Device Controller Capability Parameters
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__I uint32_t TU_RESERVED[6];
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//------------- Operational Registers -------------//
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__IO uint32_t USBCMD; ///< USB Command Register
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__IO uint32_t USBSTS; ///< USB Status Register
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__IO uint32_t USBINTR; ///< Interrupt Enable Register
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__IO uint32_t FRINDEX; ///< USB Frame Index
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__I uint32_t TU_RESERVED;
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__IO uint32_t DEVICEADDR; ///< Device Address
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__IO uint32_t ENDPTLISTADDR; ///< Endpoint List Address
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__I uint32_t TU_RESERVED;
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__IO uint32_t BURSTSIZE; ///< Programmable Burst Size
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__IO uint32_t TXFILLTUNING; ///< TX FIFO Fill Tuning
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uint32_t TU_RESERVED[4];
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__IO uint32_t ENDPTNAK; ///< Endpoint NAK
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__IO uint32_t ENDPTNAKEN; ///< Endpoint NAK Enable
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__I uint32_t TU_RESERVED;
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__IO uint32_t PORTSC1; ///< Port Status & Control
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__I uint32_t TU_RESERVED[7];
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__IO uint32_t OTGSC; ///< On-The-Go Status & control
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__IO uint32_t USBMODE; ///< USB Device Mode
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__IO uint32_t ENDPTSETUPSTAT; ///< Endpoint Setup Status
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__IO uint32_t ENDPTPRIME; ///< Endpoint Prime
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__IO uint32_t ENDPTFLUSH; ///< Endpoint Flush
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__I uint32_t ENDPTSTAT; ///< Endpoint Status
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__IO uint32_t ENDPTCOMPLETE; ///< Endpoint Complete
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__IO uint32_t ENDPTCTRL[8]; ///< Endpoint Control 0 - 7
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} dcd_registers_t, hcd_registers_t;
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#ifdef __cplusplus
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}
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#endif
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#endif /* COMMON_TRANSDIMENSION_H_ */
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