Ha Thach
fdeac8508b
Merge pull request #1381 from hathach/add-sof-isr
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Add SOF IRQ Handler
2022-05-31 22:25:14 +07:00
Jerzy Kasenberg
e49cad84e2
dcd_pic32: Fix memory overwrite in incoming data
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When transfer was finished rx_fifo_read() read all that
was to read RXPKTRDY was cleared allowing next packet to
be received.
Then xfer_complete was called.
Interrupt for OUT endpoint was left enable, that would not
be a problem if data was handled fast and new transfer was
scheduled.
For MSC when host sends a lot of data this interrupt that was
enabled could cause epn_handle_rx_int() to be called after
transfer was completed and next was not scheduled yet.
Without TU_ASSERT that was added to detect this, incoming
data was written past buffer provided by user code resulting
in random memory corruption.
This just blocks RX interrupt when transfer is finished,
and also only unmasked rx interrupts are handled.
2022-05-01 14:26:24 +02:00
Jerzy Kasenberg
c145777e0e
dcd_pic32: Add asserts transfer sanity check
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TU_ASSERTS added to detect transfer inconsistency.
2022-05-01 14:14:42 +02:00
hathach
606f932d92
added dcd_sof_enable() stubs for all other ports
2022-03-07 23:05:05 +07:00
hathach
d10326cb4e
rename TUSB_OPT_DEVICE_ENABLED to CFG_TUD_ENABLED
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TUSB_OPT_DEVICE_ENABLED still usable for backward compatible
2022-02-25 18:35:21 +07:00
Jerzy Kasenberg
168c7095e8
pic32mz: Fix remote_wakeup without OS
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Remote wakeup requires 10ms of delay when RESUME bit
is toggled.
It was covered for OS build.
For non-OS build simple delay based on board_millis() is
used to wait required amount of time.
Without this remote wakup may not work.
2022-01-17 17:59:51 +01:00
Jerzy Kasenberg
340309561d
Add driver for PIC32MZ MCUs
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Device-only driver for PIC32MZ MCUs.
2022-01-07 14:12:42 +01:00
Jerzy Kasenberg
2f69649bb6
Add register file for Microchip PIC32MZ
2021-12-31 22:53:27 +01:00
hathach
109b7a6661
more wMaxPacketSize
2021-10-24 14:39:02 +07:00
hathach
5af989384b
remove ep descriptor wMaxPacketSize bitfield due to endian issue
2021-10-24 13:11:21 +07:00
hathach
76345ea3a1
clear stall and reset data toggle when open edpt
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required to pass one of msc test.
2021-08-31 16:41:45 +07:00
hathach
71e77e47fa
add dcd_edpt_close_all() for clear existing configured state
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correctly responded to TD 9.13 Set Configuration Test
2021-08-26 17:07:03 +07:00
MasterPhi
a698dda67e
Minor fix.
2021-08-05 09:56:24 +02:00
MasterPhi
383290a634
Move register define to separate header.
2021-07-30 21:15:58 +02:00
MasterPhi
c4cd36980d
Add cache clean/invalidate.
2021-07-30 12:07:23 +02:00
MasterPhi
8c6cd5396c
Fix non-DMA IN irq.
2021-07-21 10:50:07 +02:00
MasterPhi
5492d9148c
Re-enable SETUP irq on EP0 stall.
2021-07-21 10:29:47 +02:00
MasterPhi
9c26c0c01e
Remove redundant TX irq.
2021-07-21 09:42:26 +02:00
MasterPhi
eec927ea95
Fix EP0 issue (again)
2021-07-21 00:28:51 +02:00
MasterPhi
fa9a327a71
Workaround of EP0 issue, clean up.
2021-07-20 13:24:39 +02:00
MasterPhi
895c913aa9
Merge branch 'dcd_same70' of https://github.com/HiFiPhile/tinyusb into dcd_same70
2021-07-19 22:04:34 +02:00
MasterPhi
75f61328ea
Remove clock init.
2021-07-19 22:03:47 +02:00
hathach
05f59fb8ed
clean up warning
2021-07-19 12:08:01 +07:00
MasterPhi
8cae17bfc8
Fixing NAKed OUT xfer
2021-07-19 01:07:33 +02:00
MasterPhi
bae0d3b7bb
Fix build error.
2021-07-17 14:42:23 +02:00
MasterPhi
7e3e41952f
Fix ISO support.
2021-07-17 13:48:21 +02:00
HiFiPhile
b194aa240b
Merge branch 'master' into dcd_same70
2021-07-17 12:10:35 +02:00
MasterPhi
30fff56aa4
Revert "Use byte copy.", add barrier after buffer write.
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Signed-off-by: MasterPhi <admin@hifiphile.com>
2021-06-16 00:18:38 +02:00
MasterPhi
67a6560ec9
Default use dual bank for FS, use dcd irq switch.
2021-06-15 21:52:14 +02:00
MasterPhi
6cc702e9ec
Prevent buffer overflow.
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Signed-off-by: MasterPhi <admin@hifiphile.com>
2021-06-15 21:16:51 +02:00
MasterPhi
54dc694be4
Use byte copy.
2021-06-15 19:11:53 +02:00
MasterPhi
ca8e8041ef
Fix resume, always init FS clock.
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Signed-off-by: MasterPhi <admin@hifiphile.com>
2021-06-15 17:53:09 +02:00
sabas1080
7bed7d70f0
add support SAML21
2021-06-15 00:01:28 -05:00
MasterPhi
85fc423569
Rename SAM7X to SAMX7X
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Signed-off-by: MasterPhi <admin@hifiphile.com>
2021-06-12 12:36:59 +02:00
MasterPhi
f039607afc
Fix indent.
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Signed-off-by: MasterPhi <admin@hifiphile.com>
2021-06-12 11:19:08 +02:00
Rafael Silva
776a770947
dcd: sam7x: rename family dcd to include the whole family
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Signed-off-by: Rafael Silva <perigoso@riseup.net>
2021-06-12 00:09:24 +01:00
Rafael Silva
2196991df3
dcd: same70: trim trailling spaces
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Signed-off-by: Rafael Silva <perigoso@riseup.net>
2021-06-11 21:03:36 +01:00
Rafael Silva
bcd3e31bd6
dcd: same70: fix unused variable warning
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Signed-off-by: Rafael Silva <perigoso@riseup.net>
2021-06-11 20:59:48 +01:00
Rafael Silva
9a03ab9dfa
dcd: same70: change cmsis deprecated macros
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Signed-off-by: Rafael Silva <perigoso@riseup.net>
2021-06-11 20:52:22 +01:00
MasterPhi
c291deccfa
Add fifo & DMA linked list mode support.
2021-06-11 12:17:11 +02:00
HiFiPhile
24de9d39af
Format.
2021-06-11 12:17:11 +02:00
HiFiPhile
1dafcd1132
- Add Full Speed switch
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- Add DMA support
- Add Dual bank support
Signed-off-by: HiFiPhile <admin@hifiphile.com>
2021-06-11 12:17:11 +02:00
HiFiPhile
4f4a33b378
Seems like fixed ep0 issues, code format.
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Signed-off-by: HiFiPhile <admin@hifiphile.com>
2021-06-11 12:17:11 +02:00
HiFiPhile
f8aa4b3ff3
Add sketchy SAME70 DCD driver.
2021-06-11 12:17:10 +02:00
hathach
b36b211c26
clean up tusb_fifo.h include
2021-05-27 17:58:42 +07:00
hathach
13de8f5d98
minor clean up
2021-05-10 19:15:46 +07:00
hathach
b687a4fc20
Merge branch 'master' into edpt_ISO_xfer
2021-04-15 12:12:52 +07:00
Joey Castillo
7c8b4991f1
Add support for SAM L22 family
2021-04-09 17:33:14 -04:00
hathach
bebe2f0bbf
revert dcd_edpt_xfer_fifo() implementation for nuc505
2021-04-04 22:50:26 +07:00
hathach
586a46c7d3
revert dcd_edpt_xfer_fifo() implementation for samg
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samg fifo is accessed byte by byte (although the register is 32 bit).
2021-04-04 21:33:19 +07:00