Commit Graph

49 Commits

Author SHA1 Message Date
hathach 606f932d92 added dcd_sof_enable() stubs for all other ports 2022-03-07 23:05:05 +07:00
hathach f72da8ee7d fix build with esp32s2, also use dwc2 for esp example 2022-03-04 14:45:26 +07:00
hathach d10326cb4e rename TUSB_OPT_DEVICE_ENABLED to CFG_TUD_ENABLED
TUSB_OPT_DEVICE_ENABLED still usable for backward compatible
2022-02-25 18:35:21 +07:00
suda-morris 7d0d6f85f2 update dcd_esp32sx with correct include list 2021-10-25 21:53:14 +08:00
hathach 5af989384b remove ep descriptor wMaxPacketSize bitfield due to endian issue 2021-10-24 13:11:21 +07:00
hathach cdc63459eb esp32sx implement dcd_remote_wakeup(), fully compliance to chapter9 test suite 2021-09-13 16:49:38 +07:00
hathach e64bfb9ff5 implement dcd_edpt_close_all(), pass chapter9 test suite (without remote wakeup) 2021-09-13 16:16:37 +07:00
hathach 71e77e47fa
add dcd_edpt_close_all() for clear existing configured state
correctly responded to TD 9.13 Set Configuration Test
2021-08-26 17:07:03 +07:00
hathach b36b211c26
clean up tusb_fifo.h include 2021-05-27 17:58:42 +07:00
hathach 13de8f5d98 minor clean up 2021-05-10 19:15:46 +07:00
Alex Lisitsyn 2f0cb8b5f1 tinyusb: add support of esp32s3 target
add support of new esp32s3 target and the board
update the roles.mk wrapper to allow dfu flashing of espressif chip
update examples to allow compilation for esp32s3_addax_1 board
once the code is tested the PR to original tinyusb repo will be submitted
2021-04-16 13:38:00 +02:00
hathach 3acf0c2d73 revert dcd_edpt_xfer_fifo() implementation for esp32s2 2021-04-06 01:00:00 +07:00
Reinhard Panhuber a60bd0c8ac Fix bug in writing to constant src/dst address.
Copying has to be conduct in full words (at least for STM32). Renamed
copy function to tu_fifo_write_n_const_addr_full_words()
2021-03-23 19:33:04 +01:00
Reinhard Panhuber a1b07ae14c Change copy modes for new read/write functions in tusb_fifo.c 2021-03-02 21:52:42 +01:00
Reinhard Panhuber 7b8a08d2e1 Rename dcd_edpt_iso_xfer() to dcd_edpt_xfer_fifo() 2021-03-02 20:00:39 +01:00
Reinhard Panhuber 893f997dcb Change FIFO use indication to ff == NULL to avoid future errors.
This way people don't need to pay attention for the buffer pointer
2021-02-14 09:25:34 +01:00
Reinhard Panhuber 59d6ed9ea4 Implement dcd_edpt_iso_xfer() for dcd_esp32s2.c 2021-02-13 12:13:10 +01:00
hathach 6e6e6265e4 use dcd_event_bus_reset() with speed to replace bus_signal 2021-01-08 22:34:36 +07:00
hathach 8b34f2fca8 fix ci 2020-11-27 16:07:13 +07:00
hathach 94527951a0 add bus suspend & resume support for esp32s2 2020-11-27 15:54:55 +07:00
hathach acde49ccc9
enable pull-up in dcd_init() instead of usbd 2020-08-01 20:14:58 +07:00
hathach 5af08e2ffc
fix strict prototype 2020-07-29 16:59:07 +07:00
Ha Thach 8dda0a0dd1
Merge pull request #454 from me-no-dev/esp32-s2-fifos
ESP32-S2: Handle the fact that available EP IN FIFOs are less than the number of available EP INs
2020-07-28 15:16:15 +07:00
me-no-dev a1a390a788 Update dcd_esp32s2.c 2020-07-28 10:54:23 +03:00
me-no-dev d493724a7b ESP32-S2: Detect EP IN Xfer Timeout
In some rare ocasions (bad cable, noise, etc.) data transfer might timeout and hang the endpoint, unless the interrupt flag is cleared.
This pull request targets to solve that case.
2020-07-02 13:05:17 +03:00
me-no-dev 6178f8de2f ESP32-S2: Handle the fact that available EP IN FIFOs are less than the number of available EP INs
ESP32-S2 has only 5 available endpoint-in FIFOs (including EP0) but 7 available EP IN numbers. This change decouples the fifo number from the endpoint number, providing FIFO numbers until they reach the limit, at which point it will return false and assert an error that too many endpoints were allocated.
2020-07-01 13:38:59 +03:00
hathach 00fcf829a1 sync synopsis fix for esp32s2 2020-04-26 22:41:04 +07:00
hathach c3fc5f1595 session end interrupt doesn't trigger on esp32 saola board
it is possibly due to the board design without vbus sense. Revisit
later.
2020-04-18 23:42:51 +07:00
hathach 6f9c256ad0
complete remove dcd_set_config(), fix unit test 2020-04-17 13:52:34 +07:00
hathach 50be9d7c3a
mass rename tud/dcd_irq_handler to tud/dcd_init_handler 2020-04-17 12:27:53 +07:00
hathach 63655ac9d7
cleanup for esp32 2020-04-16 20:43:26 +07:00
hathach ae1314f1c7 fix incorrect setup packet
also increase usbd stack in example when debug is enabled
2020-04-11 12:55:45 +07:00
hathach a37a56acd3 remove CONFIG_IDF_TARGET_ESP32S2BETA per review 2020-04-10 23:38:36 +07:00
hathach 8953bc9255 added comment note for beta chip walkaround 2020-04-10 20:25:53 +07:00
hathach c545cfc0bc Correct dedicated FIFO SRAM size to 1024
add note for up to 5 active IN endpoints (including EP0 IN)
2020-04-10 15:42:50 +07:00
hathach 978eec73b3 remove 100us delay at the end of dcd_init() 2020-04-10 15:39:59 +07:00
hathach 30945ab9f3 revert name to dcd_int_handler due to function prototype warning 2020-04-10 15:27:23 +07:00
hathach c0695b4b55 clear USB_RXFLVI_M before read_rx_fifo()
more format clean up
2020-04-10 15:13:12 +07:00
hathach 933e3cdfc7 change indent from 4 -> 2 spaces 2020-04-10 15:01:12 +07:00
hathach cec747776d rename dcd_init_handler to dcd_irq_handler to consistent with other ports 2020-04-10 14:47:02 +07:00
hathach d122d7de88 remove commented code 2020-04-10 14:45:55 +07:00
hathach a40d1e800d try to fix racing condition with setup 2020-04-10 14:04:18 +07:00
hathach 880595433c use macro for easy enable/disable SOF 2020-04-08 15:41:16 +07:00
hathach 7b7a78ab2e disable SOF interrupt since it is not used for now 2020-04-08 15:33:07 +07:00
hathach 06e87b47a2 revert name to dcd_init_handler()
since the function signature is different
2020-04-06 21:28:02 +07:00
hathach 22a9b05834 rename dcd_int_handler to dcd_irq_handler for consistency with other port 2020-04-06 19:49:25 +07:00
hathach 050de0ec33 fix issue and typo with In token when Fifo empty
fix transmit packet endpoint's fifo
2020-04-06 16:32:55 +07:00
hathach 1e7c3cf95e update dcd esp32s2 fifo allocation to match current dcd synopsys 2020-04-03 17:09:38 +07:00
hathach a3e50242b9 add dcd_esp32s2
skip esp32s2_saola for make build since idf use cmake
2020-04-01 17:07:28 +07:00