Merge branch 'master' into update-host
This commit is contained in:
hathach
commit
f308990ab5
|
|
@ -22,5 +22,8 @@ Steps to reproduce the behavior:
|
|||
2. Click on '....'
|
||||
3. See error
|
||||
|
||||
**Log & screenshots**
|
||||
If applicable, add screenshots and TinyUSB's log to help explain your problem. To enable logging, add `LOG=2` to your make command if building with stock examples or set `CFG_TUSB_DEBUG=2` in your tusb_config.h. More information can be found at [example's readme](/examples/readme.md)
|
||||
**Screenshots**
|
||||
If applicable, add screenshots, bus capture to help explain your problem.
|
||||
|
||||
**Log**
|
||||
Please provide the stack's log (uart/rtt/swo) where the issue occurred, best with comments to explain the actual events. To enable logging, add `LOG=2` to to the make command if building with stock examples or set `CFG_TUSB_DEBUG=2` in your tusb_config.h. More information can be found at [example's readme](/examples/readme.md)
|
||||
|
|
|
|||
|
|
@ -90,6 +90,7 @@ This code base already had supported for a handful of following boards (sorted a
|
|||
- STM32 F411ce Black Pill
|
||||
- [STM32 F411ve Discovery](https://www.st.com/en/evaluation-tools/32f411ediscovery.html)
|
||||
- [STM32 F412zg Discovery](https://www.st.com/en/evaluation-tools/32f412gdiscovery.html)
|
||||
- [STM32 F746zg Nucleo](https://www.st.com/en/evaluation-tools/nucleo-f746zg.html)
|
||||
- [STM32 F767zi Nucleo](https://www.st.com/en/evaluation-tools/nucleo-f767zi.html)
|
||||
- [STM32 H743zi Nucleo](https://www.st.com/en/evaluation-tools/nucleo-h743zi.html)
|
||||
|
||||
|
|
|
|||
|
|
@ -19,8 +19,9 @@
|
|||
arm_target_device_name="nRF52840_xxAA"
|
||||
arm_target_interface_type="SWD"
|
||||
build_treat_warnings_as_errors="Yes"
|
||||
c_preprocessor_definitions="NRF52840_XXAA;__nRF_FAMILY;ARM_MATH_CM4;FLASH_PLACEMENT=1;CFG_TUSB_MCU=OPT_MCU_NRF5X"
|
||||
c_user_include_directories="../../src;$(rootDir)/hw/mcu/nordic/cmsis/Include;$(rootDir)/hw;$(rootDir)/src;$(nrfxDir)/..;$(nrfxDir);$(nrfxDir)/mdk;$(nrfxDir)/hal;$(nrfxDir)/drivers/include;$(nrfxDir)/drivers/src"
|
||||
c_additional_options="-Wno-error=undef;-Wno-error=unused-parameter;-Wno-error=cast-align;-Wno-error=cast-function-type"
|
||||
c_preprocessor_definitions="NRF52840_XXAA;__nRF_FAMILY;ARM_MATH_CM4;FLASH_PLACEMENT=1;CFG_TUSB_MCU=OPT_MCU_NRF5X;CFG_TUSB_DEBUG=1"
|
||||
c_user_include_directories="../../src;$(rootDir)/lib/CMSIS_4/CMSIS/Include;$(rootDir)/hw;$(rootDir)/src;$(nrfxDir)/..;$(nrfxDir);$(nrfxDir)/mdk;$(nrfxDir)/hal;$(nrfxDir)/drivers/include;$(nrfxDir)/drivers/src"
|
||||
debug_register_definition_file="nrf52840_Registers.xml"
|
||||
debug_target_connection="J-Link"
|
||||
gcc_enable_all_warnings="Yes"
|
||||
|
|
@ -42,11 +43,12 @@
|
|||
recurse="Yes" />
|
||||
<folder Name="hw">
|
||||
<folder Name="bsp">
|
||||
<folder Name="pca10056">
|
||||
<file file_name="../../../../../hw/bsp/pca10056/pca10056.c" />
|
||||
</folder>
|
||||
<file file_name="../../../../../hw/bsp/ansi_escape.h" />
|
||||
<file file_name="../../../../../hw/bsp/board.h" />
|
||||
<file file_name="../../../../../hw/bsp/board.c" />
|
||||
<folder Name="feather_nrf52840_express">
|
||||
<file file_name="../../../../../hw/bsp/feather_nrf52840_express/feather_nrf52840_express.c" />
|
||||
</folder>
|
||||
</folder>
|
||||
<folder Name="mcu">
|
||||
<folder Name="nordic">
|
||||
|
|
@ -103,16 +105,10 @@
|
|||
<file file_name="thumb_crt0.s" />
|
||||
<file file_name="nRF52840_xxAA_s140v6_MemoryMap.xml" />
|
||||
</folder>
|
||||
<folder
|
||||
Name="segger_rtt"
|
||||
exclude=""
|
||||
filter="*.c;*.h"
|
||||
path="../../../../../lib/segger_rtt"
|
||||
recurse="No" />
|
||||
<configuration
|
||||
Name="pca10056"
|
||||
build_treat_warnings_as_errors="No"
|
||||
c_preprocessor_definitions="BOARD_PCA10056"
|
||||
c_preprocessor_definitions=""
|
||||
linker_memory_map_file="nRF52840_xxAA_MemoryMap.xml" />
|
||||
<configuration
|
||||
Name="pca10056 s140v6"
|
||||
|
|
@ -121,7 +117,16 @@
|
|||
c_user_include_directories="$(nrfxDir)/../nrf5x/s140_nrf52_6.1.1_API/include;$(nrfxDir)/../nrf5x/s140_nrf52_6.1.1_API/include/nrf52"
|
||||
debug_start_from_entry_point_symbol="No"
|
||||
linker_memory_map_file="nRF52840_xxAA_s140v6_MemoryMap.xml" />
|
||||
<folder Name="SEGGER_RTT">
|
||||
<folder Name="RTT">
|
||||
<file file_name="../../../../../lib/SEGGER_RTT/RTT/SEGGER_RTT.c" />
|
||||
<file file_name="../../../../../lib/SEGGER_RTT/RTT/SEGGER_RTT.h" />
|
||||
<file file_name="../../../../../lib/SEGGER_RTT/RTT/SEGGER_RTT_Conf.h" />
|
||||
<file file_name="../../../../../lib/SEGGER_RTT/RTT/SEGGER_RTT_printf.c" />
|
||||
</folder>
|
||||
</folder>
|
||||
</project>
|
||||
<configuration Name="pca10056" />
|
||||
<configuration Name="pca10056 s140v6" />
|
||||
<configuration Name="Feather nRF52840" />
|
||||
</solution>
|
||||
|
|
|
|||
|
|
@ -6,6 +6,9 @@ CFLAGS += \
|
|||
-DTCP_WND=2*TCP_MSS \
|
||||
-DHTTPD_USE_CUSTOM_FSDATA=0
|
||||
|
||||
# TODO rndis_reports.c and net_device cause cast algin warnings
|
||||
CFLAGS += -Wno-error=cast-align
|
||||
|
||||
INC += \
|
||||
src \
|
||||
$(TOP)/hw \
|
||||
|
|
|
|||
|
|
@ -63,11 +63,9 @@ CFLAGS += \
|
|||
-Wwrite-strings \
|
||||
-Wsign-compare \
|
||||
-Wmissing-format-attribute \
|
||||
-Wunreachable-code
|
||||
|
||||
# This causes lots of warning with nrf5x build due to nrfx code
|
||||
# CFLAGS += -Wcast-align
|
||||
|
||||
-Wunreachable-code \
|
||||
-Wcast-align
|
||||
|
||||
# Debugging/Optimization
|
||||
ifeq ($(DEBUG), 1)
|
||||
CFLAGS += -Og -ggdb
|
||||
|
|
|
|||
|
|
@ -9,8 +9,8 @@ CFLAGS += \
|
|||
-DNRF52840_XXAA \
|
||||
-DCONFIG_GPIO_AS_PINRESET
|
||||
|
||||
# nrfx issue undef _ARMCC_VERSION usage https://github.com/NordicSemiconductor/nrfx/issues/49
|
||||
CFLAGS += -Wno-error=undef -Wno-error=unused-parameter
|
||||
# suppress warning caused by vendor mcu driver
|
||||
CFLAGS += -Wno-error=undef -Wno-error=unused-parameter -Wno-error=cast-align
|
||||
|
||||
# due to tusb_hal_nrf_power_event
|
||||
GCCVERSION = $(firstword $(subst ., ,$(shell arm-none-eabi-gcc -dumpversion)))
|
||||
|
|
|
|||
|
|
@ -9,8 +9,8 @@ CFLAGS += \
|
|||
-DNRF52840_XXAA \
|
||||
-DCONFIG_GPIO_AS_PINRESET
|
||||
|
||||
# nrfx issue undef _ARMCC_VERSION usage https://github.com/NordicSemiconductor/nrfx/issues/49
|
||||
CFLAGS += -Wno-error=undef -Wno-error=unused-parameter
|
||||
# suppress warning caused by vendor mcu driver
|
||||
CFLAGS += -Wno-error=undef -Wno-error=unused-parameter -Wno-error=cast-align
|
||||
|
||||
# due to tusb_hal_nrf_power_event
|
||||
GCCVERSION = $(firstword $(subst ., ,$(shell arm-none-eabi-gcc -dumpversion)))
|
||||
|
|
|
|||
|
|
@ -9,8 +9,8 @@ CFLAGS += \
|
|||
-DNRF52840_XXAA \
|
||||
-DCONFIG_GPIO_AS_PINRESET
|
||||
|
||||
# nrfx issue undef _ARMCC_VERSION usage https://github.com/NordicSemiconductor/nrfx/issues/49
|
||||
CFLAGS += -Wno-error=undef -Wno-error=unused-parameter
|
||||
# suppress warning caused by vendor mcu driver
|
||||
CFLAGS += -Wno-error=undef -Wno-error=unused-parameter -Wno-error=cast-align
|
||||
|
||||
# due to tusb_hal_nrf_power_event
|
||||
GCCVERSION = $(firstword $(subst ., ,$(shell arm-none-eabi-gcc -dumpversion)))
|
||||
|
|
|
|||
|
|
@ -9,8 +9,8 @@ CFLAGS += \
|
|||
-DNRF52840_XXAA \
|
||||
-DCONFIG_GPIO_AS_PINRESET
|
||||
|
||||
# nrfx issue undef _ARMCC_VERSION usage https://github.com/NordicSemiconductor/nrfx/issues/49
|
||||
CFLAGS += -Wno-error=undef -Wno-error=unused-parameter
|
||||
# suppress warning caused by vendor mcu driver
|
||||
CFLAGS += -Wno-error=undef -Wno-error=unused-parameter -Wno-error=cast-align
|
||||
|
||||
# due to tusb_hal_nrf_power_event
|
||||
GCCVERSION = $(firstword $(subst ., ,$(shell arm-none-eabi-gcc -dumpversion)))
|
||||
|
|
|
|||
|
|
@ -9,8 +9,8 @@ CFLAGS += \
|
|||
-DNRF52840_XXAA \
|
||||
-DCONFIG_GPIO_AS_PINRESET
|
||||
|
||||
# nrfx issue undef _ARMCC_VERSION usage https://github.com/NordicSemiconductor/nrfx/issues/49
|
||||
CFLAGS += -Wno-error=undef -Wno-error=unused-parameter
|
||||
# suppress warning caused by vendor mcu driver
|
||||
CFLAGS += -Wno-error=undef -Wno-error=unused-parameter -Wno-error=cast-align
|
||||
|
||||
# due to tusb_hal_nrf_power_event
|
||||
GCCVERSION = $(firstword $(subst ., ,$(shell arm-none-eabi-gcc -dumpversion)))
|
||||
|
|
|
|||
|
|
@ -9,6 +9,9 @@ CFLAGS += \
|
|||
-DSTM32F405xx \
|
||||
-DCFG_TUSB_MCU=OPT_MCU_STM32F4
|
||||
|
||||
# suppress warning caused by vendor mcu driver
|
||||
CFLAGS += -Wno-error=cast-align
|
||||
|
||||
ST_HAL_DRIVER = hw/mcu/st/st_driver/STM32F4xx_HAL_Driver
|
||||
ST_CMSIS = hw/mcu/st/st_driver/CMSIS/Device/ST/STM32F4xx
|
||||
|
||||
|
|
|
|||
|
|
@ -8,8 +8,8 @@ CFLAGS += \
|
|||
-DNRF52840_XXAA \
|
||||
-DCFG_TUSB_MCU=OPT_MCU_NRF5X
|
||||
|
||||
# nrfx issue undef _ARMCC_VERSION usage https://github.com/NordicSemiconductor/nrfx/issues/49
|
||||
CFLAGS += -Wno-error=undef -Wno-error=unused-parameter
|
||||
# suppress warning caused by vendor mcu driver
|
||||
CFLAGS += -Wno-error=undef -Wno-error=unused-parameter -Wno-error=cast-align
|
||||
|
||||
# due to tusb_hal_nrf_power_event
|
||||
GCCVERSION = $(firstword $(subst ., ,$(shell arm-none-eabi-gcc -dumpversion)))
|
||||
|
|
|
|||
|
|
@ -19,13 +19,11 @@ SRC_C += \
|
|||
hw/mcu/nuvoton/nuc505/StdDriver/src/i2s.c \
|
||||
hw/mcu/nuvoton/nuc505/StdDriver/src/pwm.c \
|
||||
hw/mcu/nuvoton/nuc505/StdDriver/src/rtc.c \
|
||||
hw/mcu/nuvoton/nuc505/StdDriver/src/sd.c \
|
||||
hw/mcu/nuvoton/nuc505/StdDriver/src/spi.c \
|
||||
hw/mcu/nuvoton/nuc505/StdDriver/src/spim.c \
|
||||
hw/mcu/nuvoton/nuc505/StdDriver/src/sys.c \
|
||||
hw/mcu/nuvoton/nuc505/StdDriver/src/timer.c \
|
||||
hw/mcu/nuvoton/nuc505/StdDriver/src/uart.c \
|
||||
hw/mcu/nuvoton/nuc505/StdDriver/src/usbd.c \
|
||||
hw/mcu/nuvoton/nuc505/StdDriver/src/wdt.c \
|
||||
hw/mcu/nuvoton/nuc505/StdDriver/src/wwdt.c
|
||||
|
||||
|
|
|
|||
|
|
@ -9,8 +9,8 @@ CFLAGS += \
|
|||
-DCONFIG_GPIO_AS_PINRESET \
|
||||
-DCFG_TUSB_MCU=OPT_MCU_NRF5X
|
||||
|
||||
# nrfx issue undef _ARMCC_VERSION usage https://github.com/NordicSemiconductor/nrfx/issues/49
|
||||
CFLAGS += -Wno-error=undef -Wno-error=unused-parameter
|
||||
# suppress warning caused by vendor mcu driver
|
||||
CFLAGS += -Wno-error=undef -Wno-error=unused-parameter -Wno-error=cast-align
|
||||
|
||||
# due to tusb_hal_nrf_power_event
|
||||
GCCVERSION = $(firstword $(subst ., ,$(shell arm-none-eabi-gcc -dumpversion)))
|
||||
|
|
|
|||
|
|
@ -9,8 +9,8 @@ CFLAGS += \
|
|||
-DCONFIG_GPIO_AS_PINRESET \
|
||||
-DCFG_TUSB_MCU=OPT_MCU_NRF5X
|
||||
|
||||
# nrfx issue undef _ARMCC_VERSION usage https://github.com/NordicSemiconductor/nrfx/issues/49
|
||||
CFLAGS += -Wno-error=undef -Wno-error=unused-parameter
|
||||
# suppress warning caused by vendor mcu driver
|
||||
CFLAGS += -Wno-error=undef -Wno-error=unused-parameter -Wno-error=cast-align
|
||||
|
||||
# due to tusb_hal_nrf_power_event
|
||||
GCCVERSION = $(firstword $(subst ., ,$(shell arm-none-eabi-gcc -dumpversion)))
|
||||
|
|
|
|||
|
|
@ -9,8 +9,8 @@ CFLAGS += \
|
|||
-DCONFIG_GPIO_AS_PINRESET \
|
||||
-DCFG_TUSB_MCU=OPT_MCU_NRF5X
|
||||
|
||||
# nrfx issue undef _ARMCC_VERSION usage https://github.com/NordicSemiconductor/nrfx/issues/49
|
||||
CFLAGS += -Wno-error=undef -Wno-error=unused-parameter
|
||||
# suppress warning caused by vendor mcu driver
|
||||
CFLAGS += -Wno-error=undef -Wno-error=unused-parameter -Wno-error=cast-align
|
||||
|
||||
# due to tusb_hal_nrf_power_event
|
||||
GCCVERSION = $(firstword $(subst ., ,$(shell arm-none-eabi-gcc -dumpversion)))
|
||||
|
|
|
|||
|
|
@ -8,8 +8,8 @@ CFLAGS += \
|
|||
-DNRF52840_XXAA \
|
||||
-DCFG_TUSB_MCU=OPT_MCU_NRF5X
|
||||
|
||||
# nrfx issue undef _ARMCC_VERSION usage https://github.com/NordicSemiconductor/nrfx/issues/49
|
||||
CFLAGS += -Wno-error=undef -Wno-error=unused-parameter
|
||||
# suppress warning caused by vendor mcu driver
|
||||
CFLAGS += -Wno-error=undef -Wno-error=unused-parameter -Wno-error=cast-align
|
||||
|
||||
# due to tusb_hal_nrf_power_event
|
||||
GCCVERSION = $(firstword $(subst ., ,$(shell arm-none-eabi-gcc -dumpversion)))
|
||||
|
|
|
|||
|
|
@ -9,8 +9,8 @@ CFLAGS += \
|
|||
-DCFG_EXAMPLE_MSC_READONLY \
|
||||
-DCFG_TUSB_MCU=OPT_MCU_STM32F0
|
||||
|
||||
# mcu driver cause following warnings
|
||||
CFLAGS += -Wno-error=unused-parameter
|
||||
# suppress warning caused by vendor mcu driver
|
||||
CFLAGS += -Wno-error=unused-parameter -Wno-error=cast-align
|
||||
|
||||
ST_HAL_DRIVER = hw/mcu/st/st_driver/STM32F0xx_HAL_Driver
|
||||
ST_CMSIS = hw/mcu/st/st_driver/CMSIS/Device/ST/STM32F0xx
|
||||
|
|
|
|||
|
|
@ -9,8 +9,8 @@ CFLAGS += \
|
|||
-DCFG_EXAMPLE_MSC_READONLY \
|
||||
-DCFG_TUSB_MCU=OPT_MCU_STM32F0
|
||||
|
||||
# mcu driver cause following warnings
|
||||
CFLAGS += -Wno-error=unused-parameter
|
||||
# suppress warning caused by vendor mcu driver
|
||||
CFLAGS += -Wno-error=unused-parameter -Wno-error=cast-align
|
||||
|
||||
ST_HAL_DRIVER = hw/mcu/st/st_driver/STM32F0xx_HAL_Driver
|
||||
ST_CMSIS = hw/mcu/st/st_driver/CMSIS/Device/ST/STM32F0xx
|
||||
|
|
|
|||
|
|
@ -9,6 +9,9 @@ CFLAGS += \
|
|||
-DSTM32F407xx \
|
||||
-DCFG_TUSB_MCU=OPT_MCU_STM32F4
|
||||
|
||||
# suppress warning caused by vendor mcu driver
|
||||
CFLAGS += -Wno-error=cast-align
|
||||
|
||||
ST_HAL_DRIVER = hw/mcu/st/st_driver/STM32F4xx_HAL_Driver
|
||||
ST_CMSIS = hw/mcu/st/st_driver/CMSIS/Device/ST/STM32F4xx
|
||||
|
||||
|
|
|
|||
|
|
@ -9,6 +9,9 @@ CFLAGS += \
|
|||
-DSTM32F411xE \
|
||||
-DCFG_TUSB_MCU=OPT_MCU_STM32F4
|
||||
|
||||
# suppress warning caused by vendor mcu driver
|
||||
CFLAGS += -Wno-error=cast-align
|
||||
|
||||
ST_HAL_DRIVER = hw/mcu/st/st_driver/STM32F4xx_HAL_Driver
|
||||
ST_CMSIS = hw/mcu/st/st_driver/CMSIS/Device/ST/STM32F4xx
|
||||
|
||||
|
|
|
|||
|
|
@ -9,8 +9,8 @@ CFLAGS += \
|
|||
-DSTM32F412Zx \
|
||||
-DCFG_TUSB_MCU=OPT_MCU_STM32F4
|
||||
|
||||
# mcu driver cause following warnings
|
||||
CFLAGS += -Wno-error=maybe-uninitialized
|
||||
# suppress warning caused by vendor mcu driver
|
||||
CFLAGS += -Wno-error=cast-align
|
||||
|
||||
ST_HAL_DRIVER = hw/mcu/st/st_driver/STM32F4xx_HAL_Driver
|
||||
ST_CMSIS = hw/mcu/st/st_driver/CMSIS/Device/ST/STM32F4xx
|
||||
|
|
|
|||
|
|
@ -0,0 +1,167 @@
|
|||
/*
|
||||
*****************************************************************************
|
||||
**
|
||||
|
||||
** File : LinkerScript.ld
|
||||
**
|
||||
** Abstract : Linker script for STM32F746ZGTx Device with
|
||||
** 1024KByte FLASH, 320KByte RAM
|
||||
**
|
||||
** Set heap size, stack size and stack location according
|
||||
** to application requirements.
|
||||
**
|
||||
** Set memory bank area and size if external memory is used.
|
||||
**
|
||||
** Target : STMicroelectronics STM32
|
||||
**
|
||||
**
|
||||
** Distribution: The file is distributed as is, without any warranty
|
||||
** of any kind.
|
||||
**
|
||||
** (c)Copyright Ac6.
|
||||
** You may use this file as-is or modify it according to the needs of your
|
||||
** project. Distribution of this file (unmodified or modified) is not
|
||||
** permitted. Ac6 permit registered System Workbench for MCU users the
|
||||
** rights to distribute the assembled, compiled & linked contents of this
|
||||
** file as part of an application binary file, provided that it is built
|
||||
** using the System Workbench for MCU toolchain.
|
||||
**
|
||||
*****************************************************************************
|
||||
*/
|
||||
|
||||
/* Entry Point */
|
||||
ENTRY(Reset_Handler)
|
||||
|
||||
/* Highest address of the user mode stack */
|
||||
_estack = 0x20050000; /* end of RAM */
|
||||
/* Generate a link error if heap and stack don't fit into RAM */
|
||||
_Min_Heap_Size = 0x200; /* required amount of heap */
|
||||
_Min_Stack_Size = 0x460; /* required amount of stack */
|
||||
|
||||
/* Specify the memory areas */
|
||||
MEMORY
|
||||
{
|
||||
RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 320K
|
||||
FLASH (rx) : ORIGIN = 0x8000000, LENGTH = 1024K
|
||||
}
|
||||
|
||||
/* Define output sections */
|
||||
SECTIONS
|
||||
{
|
||||
/* The startup code goes first into FLASH */
|
||||
.isr_vector :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
KEEP(*(.isr_vector)) /* Startup code */
|
||||
. = ALIGN(4);
|
||||
} >FLASH
|
||||
|
||||
/* The program code and other data goes into FLASH */
|
||||
.text :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
*(.text) /* .text sections (code) */
|
||||
*(.text*) /* .text* sections (code) */
|
||||
*(.glue_7) /* glue arm to thumb code */
|
||||
*(.glue_7t) /* glue thumb to arm code */
|
||||
*(.eh_frame)
|
||||
|
||||
KEEP (*(.init))
|
||||
KEEP (*(.fini))
|
||||
|
||||
. = ALIGN(4);
|
||||
_etext = .; /* define a global symbols at end of code */
|
||||
} >FLASH
|
||||
|
||||
/* Constant data goes into FLASH */
|
||||
.rodata :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
*(.rodata) /* .rodata sections (constants, strings, etc.) */
|
||||
*(.rodata*) /* .rodata* sections (constants, strings, etc.) */
|
||||
. = ALIGN(4);
|
||||
} >FLASH
|
||||
|
||||
.ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
|
||||
.ARM : {
|
||||
__exidx_start = .;
|
||||
*(.ARM.exidx*)
|
||||
__exidx_end = .;
|
||||
} >FLASH
|
||||
|
||||
.preinit_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__preinit_array_start = .);
|
||||
KEEP (*(.preinit_array*))
|
||||
PROVIDE_HIDDEN (__preinit_array_end = .);
|
||||
} >FLASH
|
||||
.init_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__init_array_start = .);
|
||||
KEEP (*(SORT(.init_array.*)))
|
||||
KEEP (*(.init_array*))
|
||||
PROVIDE_HIDDEN (__init_array_end = .);
|
||||
} >FLASH
|
||||
.fini_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__fini_array_start = .);
|
||||
KEEP (*(SORT(.fini_array.*)))
|
||||
KEEP (*(.fini_array*))
|
||||
PROVIDE_HIDDEN (__fini_array_end = .);
|
||||
} >FLASH
|
||||
|
||||
/* used by the startup to initialize data */
|
||||
_sidata = LOADADDR(.data);
|
||||
|
||||
/* Initialized data sections goes into RAM, load LMA copy after code */
|
||||
.data :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_sdata = .; /* create a global symbol at data start */
|
||||
*(.data) /* .data sections */
|
||||
*(.data*) /* .data* sections */
|
||||
|
||||
. = ALIGN(4);
|
||||
_edata = .; /* define a global symbol at data end */
|
||||
} >RAM AT> FLASH
|
||||
|
||||
|
||||
/* Uninitialized data section */
|
||||
. = ALIGN(4);
|
||||
.bss :
|
||||
{
|
||||
/* This is used by the startup in order to initialize the .bss secion */
|
||||
_sbss = .; /* define a global symbol at bss start */
|
||||
__bss_start__ = _sbss;
|
||||
*(.bss)
|
||||
*(.bss*)
|
||||
*(COMMON)
|
||||
|
||||
. = ALIGN(4);
|
||||
_ebss = .; /* define a global symbol at bss end */
|
||||
__bss_end__ = _ebss;
|
||||
} >RAM
|
||||
|
||||
/* User_heap_stack section, used to check that there is enough RAM left */
|
||||
._user_heap_stack :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
PROVIDE ( end = . );
|
||||
PROVIDE ( _end = . );
|
||||
. = . + _Min_Heap_Size;
|
||||
. = . + _Min_Stack_Size;
|
||||
. = ALIGN(8);
|
||||
} >RAM
|
||||
|
||||
|
||||
|
||||
/* Remove information from the standard libraries */
|
||||
/DISCARD/ :
|
||||
{
|
||||
libc.a ( * )
|
||||
libm.a ( * )
|
||||
libgcc.a ( * )
|
||||
}
|
||||
|
||||
.ARM.attributes 0 : { *(.ARM.attributes) }
|
||||
}
|
||||
|
|
@ -0,0 +1,48 @@
|
|||
CFLAGS += \
|
||||
-flto \
|
||||
-mthumb \
|
||||
-mabi=aapcs \
|
||||
-mcpu=cortex-m7 \
|
||||
-mfloat-abi=hard \
|
||||
-mfpu=fpv5-d16 \
|
||||
-nostdlib -nostartfiles \
|
||||
-DSTM32F746xx \
|
||||
-DCFG_TUSB_MCU=OPT_MCU_STM32F7
|
||||
|
||||
# suppress warning caused by vendor mcu driver
|
||||
CFLAGS += -Wno-error=cast-align -Wno-error=shadow
|
||||
|
||||
ST_HAL_DRIVER = hw/mcu/st/st_driver/STM32F7xx_HAL_Driver
|
||||
ST_CMSIS = hw/mcu/st/st_driver/CMSIS/Device/ST/STM32F7xx
|
||||
|
||||
# All source paths should be relative to the top level.
|
||||
LD_FILE = hw/bsp/$(BOARD)/STM32F746ZGTx_FLASH.ld
|
||||
|
||||
SRC_C += \
|
||||
$(ST_CMSIS)/Source/Templates/system_stm32f7xx.c \
|
||||
$(ST_HAL_DRIVER)/Src/stm32f7xx_hal.c \
|
||||
$(ST_HAL_DRIVER)/Src/stm32f7xx_hal_cortex.c \
|
||||
$(ST_HAL_DRIVER)/Src/stm32f7xx_hal_rcc.c \
|
||||
$(ST_HAL_DRIVER)/Src/stm32f7xx_hal_rcc_ex.c \
|
||||
$(ST_HAL_DRIVER)/Src/stm32f7xx_hal_gpio.c \
|
||||
$(ST_HAL_DRIVER)/Src/stm32f7xx_hal_uart.c \
|
||||
$(ST_HAL_DRIVER)/Src/stm32f7xx_hal_pwr_ex.c
|
||||
|
||||
SRC_S += \
|
||||
$(ST_CMSIS)/Source/Templates/gcc/startup_stm32f746xx.s
|
||||
|
||||
INC += \
|
||||
$(TOP)/hw/mcu/st/st_driver/CMSIS/Include \
|
||||
$(TOP)/$(ST_CMSIS)/Include \
|
||||
$(TOP)/$(ST_HAL_DRIVER)/Inc \
|
||||
$(TOP)/hw/bsp/$(BOARD)
|
||||
|
||||
# For TinyUSB port source
|
||||
VENDOR = st
|
||||
CHIP_FAMILY = synopsys
|
||||
|
||||
# For freeRTOS port source
|
||||
FREERTOS_PORT = ARM_CM7/r0p1
|
||||
|
||||
# flash target using on-board stlink
|
||||
flash: flash-stlink
|
||||
|
|
@ -0,0 +1,255 @@
|
|||
/*
|
||||
* The MIT License (MIT)
|
||||
*
|
||||
* Copyright (c) 2019 William D. Jones (thor0505@comcast.net),
|
||||
* Ha Thach (tinyusb.org)
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
* of this software and associated documentation files (the "Software"), to deal
|
||||
* in the Software without restriction, including without limitation the rights
|
||||
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
* copies of the Software, and to permit persons to whom the Software is
|
||||
* furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
||||
* THE SOFTWARE.
|
||||
*
|
||||
* This file is part of the TinyUSB stack.
|
||||
*/
|
||||
|
||||
#include "../board.h"
|
||||
|
||||
#include "stm32f7xx_hal.h"
|
||||
|
||||
//--------------------------------------------------------------------+
|
||||
// Forward USB interrupt events to TinyUSB IRQ Handler
|
||||
//--------------------------------------------------------------------+
|
||||
void OTG_FS_IRQHandler(void)
|
||||
{
|
||||
tud_int_handler(0);
|
||||
}
|
||||
|
||||
//--------------------------------------------------------------------+
|
||||
// MACRO TYPEDEF CONSTANT ENUM
|
||||
//--------------------------------------------------------------------+
|
||||
|
||||
#define LED_PORT GPIOB
|
||||
#define LED_PIN GPIO_PIN_14
|
||||
#define LED_STATE_ON 1
|
||||
|
||||
#define BUTTON_PORT GPIOC
|
||||
#define BUTTON_PIN GPIO_PIN_13
|
||||
#define BUTTON_STATE_ACTIVE 1
|
||||
|
||||
#define UARTx USART3
|
||||
#define UART_GPIO_PORT GPIOD
|
||||
#define UART_GPIO_AF GPIO_AF7_USART3
|
||||
#define UART_TX_PIN GPIO_PIN_8
|
||||
#define UART_RX_PIN GPIO_PIN_9
|
||||
|
||||
UART_HandleTypeDef UartHandle;
|
||||
|
||||
// enable all LED, Button, Uart, USB clock
|
||||
static void all_rcc_clk_enable(void)
|
||||
{
|
||||
__HAL_RCC_GPIOA_CLK_ENABLE(); // USB D+, D-
|
||||
__HAL_RCC_GPIOB_CLK_ENABLE(); // LED
|
||||
__HAL_RCC_GPIOC_CLK_ENABLE(); // Button
|
||||
__HAL_RCC_GPIOD_CLK_ENABLE(); // Uart tx, rx
|
||||
__HAL_RCC_USART3_CLK_ENABLE(); // Uart module
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief System Clock Configuration
|
||||
* The system Clock is configured as follow :
|
||||
* System Clock source = PLL (HSE)
|
||||
* SYSCLK(Hz) = 216000000
|
||||
* HCLK(Hz) = 216000000
|
||||
* AHB Prescaler = 1
|
||||
* APB1 Prescaler = 4
|
||||
* APB2 Prescaler = 2
|
||||
* HSE Frequency(Hz) = 8000000
|
||||
* PLL_M = HSE_VALUE/1000000
|
||||
* PLL_N = 432
|
||||
* PLL_P = 2
|
||||
* PLL_Q = 9
|
||||
* VDD(V) = 3.3
|
||||
* Main regulator output voltage = Scale1 mode
|
||||
* Flash Latency(WS) = 7
|
||||
* The USB clock configuration from PLLSAI:
|
||||
* PLLSAIP = 8
|
||||
* PLLSAIN = 384
|
||||
* PLLSAIQ = 7
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void SystemClock_Config(void)
|
||||
{
|
||||
RCC_ClkInitTypeDef RCC_ClkInitStruct;
|
||||
RCC_OscInitTypeDef RCC_OscInitStruct;
|
||||
|
||||
/* Enable Power Control clock */
|
||||
__HAL_RCC_PWR_CLK_ENABLE();
|
||||
|
||||
/* The voltage scaling allows optimizing the power consumption when the device is
|
||||
clocked below the maximum system frequency, to update the voltage scaling value
|
||||
regarding system frequency refer to product datasheet. */
|
||||
__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
|
||||
|
||||
/* Enable HSE Oscillator and activate PLL with HSE as source */
|
||||
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
|
||||
RCC_OscInitStruct.HSEState = RCC_HSE_ON;
|
||||
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
|
||||
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
|
||||
RCC_OscInitStruct.PLL.PLLM = HSE_VALUE/1000000;
|
||||
RCC_OscInitStruct.PLL.PLLN = 432;
|
||||
RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
|
||||
RCC_OscInitStruct.PLL.PLLQ = 9;
|
||||
HAL_RCC_OscConfig(&RCC_OscInitStruct);
|
||||
|
||||
/* Activate the OverDrive to reach the 216 MHz Frequency */
|
||||
HAL_PWREx_EnableOverDrive();
|
||||
|
||||
/* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
|
||||
RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
|
||||
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
|
||||
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
|
||||
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4;
|
||||
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2;
|
||||
|
||||
HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_7);
|
||||
}
|
||||
|
||||
void board_init(void)
|
||||
{
|
||||
|
||||
|
||||
SystemClock_Config();
|
||||
all_rcc_clk_enable();
|
||||
|
||||
#if CFG_TUSB_OS == OPT_OS_NONE
|
||||
// 1ms tick timer
|
||||
SysTick_Config(SystemCoreClock / 1000);
|
||||
#endif
|
||||
|
||||
GPIO_InitTypeDef GPIO_InitStruct;
|
||||
|
||||
// LED
|
||||
GPIO_InitStruct.Pin = LED_PIN;
|
||||
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
|
||||
GPIO_InitStruct.Pull = GPIO_PULLUP;
|
||||
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
|
||||
HAL_GPIO_Init(LED_PORT, &GPIO_InitStruct);
|
||||
|
||||
// Button
|
||||
GPIO_InitStruct.Pin = BUTTON_PIN;
|
||||
GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
|
||||
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
||||
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
|
||||
HAL_GPIO_Init(BUTTON_PORT, &GPIO_InitStruct);
|
||||
|
||||
// Uart
|
||||
GPIO_InitStruct.Pin = UART_TX_PIN | UART_RX_PIN;
|
||||
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
||||
GPIO_InitStruct.Pull = GPIO_PULLUP;
|
||||
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
|
||||
GPIO_InitStruct.Alternate = UART_GPIO_AF;
|
||||
HAL_GPIO_Init(UART_GPIO_PORT, &GPIO_InitStruct);
|
||||
|
||||
UartHandle.Instance = UARTx;
|
||||
UartHandle.Init.BaudRate = CFG_BOARD_UART_BAUDRATE;
|
||||
UartHandle.Init.WordLength = UART_WORDLENGTH_8B;
|
||||
UartHandle.Init.StopBits = UART_STOPBITS_1;
|
||||
UartHandle.Init.Parity = UART_PARITY_NONE;
|
||||
UartHandle.Init.HwFlowCtl = UART_HWCONTROL_NONE;
|
||||
UartHandle.Init.Mode = UART_MODE_TX_RX;
|
||||
UartHandle.Init.OverSampling = UART_OVERSAMPLING_16;
|
||||
HAL_UART_Init(&UartHandle);
|
||||
|
||||
/* Configure USB FS GPIOs */
|
||||
/* Configure DM DP Pins */
|
||||
GPIO_InitStruct.Pin = (GPIO_PIN_11 | GPIO_PIN_12);
|
||||
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
||||
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
||||
GPIO_InitStruct.Speed = GPIO_SPEED_HIGH;
|
||||
GPIO_InitStruct.Alternate = GPIO_AF10_OTG_FS;
|
||||
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
|
||||
|
||||
/* Configure VBUS Pin */
|
||||
GPIO_InitStruct.Pin = GPIO_PIN_9;
|
||||
GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
|
||||
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
||||
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
|
||||
|
||||
/* Configure ID pin */
|
||||
GPIO_InitStruct.Pin = GPIO_PIN_10;
|
||||
GPIO_InitStruct.Mode = GPIO_MODE_AF_OD;
|
||||
GPIO_InitStruct.Pull = GPIO_PULLUP;
|
||||
GPIO_InitStruct.Alternate = GPIO_AF10_OTG_FS;
|
||||
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
|
||||
|
||||
/* Enable USB FS Clocks */
|
||||
__HAL_RCC_USB_OTG_FS_CLK_ENABLE();
|
||||
|
||||
// Enable VBUS sense (B device) via pin PA9
|
||||
USB_OTG_FS->GCCFG |= USB_OTG_GCCFG_VBDEN;
|
||||
}
|
||||
|
||||
//--------------------------------------------------------------------+
|
||||
// Board porting API
|
||||
//--------------------------------------------------------------------+
|
||||
|
||||
void board_led_write(bool state)
|
||||
{
|
||||
HAL_GPIO_WritePin(LED_PORT, LED_PIN, state);
|
||||
}
|
||||
|
||||
uint32_t board_button_read(void)
|
||||
{
|
||||
return HAL_GPIO_ReadPin(BUTTON_PORT, BUTTON_PIN);
|
||||
}
|
||||
|
||||
int board_uart_read(uint8_t* buf, int len)
|
||||
{
|
||||
(void) buf; (void) len;
|
||||
return 0;
|
||||
}
|
||||
|
||||
int board_uart_write(void const * buf, int len)
|
||||
{
|
||||
HAL_UART_Transmit(&UartHandle, (uint8_t*) buf, len, 0xffff);
|
||||
return len;
|
||||
}
|
||||
|
||||
#if CFG_TUSB_OS == OPT_OS_NONE
|
||||
volatile uint32_t system_ticks = 0;
|
||||
void SysTick_Handler (void)
|
||||
{
|
||||
system_ticks++;
|
||||
}
|
||||
|
||||
uint32_t board_millis(void)
|
||||
{
|
||||
return system_ticks;
|
||||
}
|
||||
#endif
|
||||
|
||||
void HardFault_Handler (void)
|
||||
{
|
||||
asm("bkpt");
|
||||
}
|
||||
|
||||
// Required by __libc_init_array in startup code if we are compiling using
|
||||
// -nostdlib/-nostartfiles.
|
||||
void _init(void)
|
||||
{
|
||||
|
||||
}
|
||||
|
|
@ -0,0 +1,472 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f7xx_hal_conf.h
|
||||
* @author MCD Application Team
|
||||
* @brief HAL configuration file.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2016 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F7xx_HAL_CONF_H
|
||||
#define __STM32F7xx_HAL_CONF_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/* ########################## Module Selection ############################## */
|
||||
/**
|
||||
* @brief This is the list of modules to be used in the HAL driver
|
||||
*/
|
||||
#define HAL_MODULE_ENABLED
|
||||
/* #define HAL_ADC_MODULE_ENABLED */
|
||||
/* #define HAL_CAN_MODULE_ENABLED */
|
||||
/* #define HAL_CAN_LEGACY_MODULE_ENABLED */
|
||||
/* #define HAL_CEC_MODULE_ENABLED */
|
||||
/* #define HAL_CRC_MODULE_ENABLED */
|
||||
/* #define HAL_CRYP_MODULE_ENABLED */
|
||||
/* #define HAL_DAC_MODULE_ENABLED */
|
||||
/* #define HAL_DCMI_MODULE_ENABLED */
|
||||
#define HAL_DMA_MODULE_ENABLED
|
||||
/* #define HAL_DMA2D_MODULE_ENABLED */
|
||||
/* #define HAL_ETH_MODULE_ENABLED */
|
||||
#define HAL_FLASH_MODULE_ENABLED
|
||||
/* #define HAL_NAND_MODULE_ENABLED */
|
||||
/* #define HAL_NOR_MODULE_ENABLED */
|
||||
/* #define HAL_SRAM_MODULE_ENABLED */
|
||||
/* #define HAL_SDRAM_MODULE_ENABLED */
|
||||
/* #define HAL_HASH_MODULE_ENABLED */
|
||||
#define HAL_GPIO_MODULE_ENABLED
|
||||
/* #define HAL_I2C_MODULE_ENABLED */
|
||||
/* #define HAL_I2S_MODULE_ENABLED */
|
||||
/* #define HAL_IWDG_MODULE_ENABLED */
|
||||
/* #define HAL_LPTIM_MODULE_ENABLED */
|
||||
/* #define HAL_LTDC_MODULE_ENABLED */
|
||||
#define HAL_PWR_MODULE_ENABLED
|
||||
/* #define HAL_QSPI_MODULE_ENABLED */
|
||||
#define HAL_RCC_MODULE_ENABLED
|
||||
/* #define HAL_RNG_MODULE_ENABLED */
|
||||
/* #define HAL_RTC_MODULE_ENABLED */
|
||||
/* #define HAL_SAI_MODULE_ENABLED */
|
||||
/* #define HAL_SD_MODULE_ENABLED */
|
||||
/* #define HAL_SPDIFRX_MODULE_ENABLED */
|
||||
/* #define HAL_SPI_MODULE_ENABLED */
|
||||
/* #define HAL_TIM_MODULE_ENABLED */
|
||||
#define HAL_UART_MODULE_ENABLED
|
||||
/* #define HAL_USART_MODULE_ENABLED */
|
||||
/* #define HAL_IRDA_MODULE_ENABLED */
|
||||
/* #define HAL_SMARTCARD_MODULE_ENABLED */
|
||||
/* #define HAL_WWDG_MODULE_ENABLED */
|
||||
#define HAL_CORTEX_MODULE_ENABLED
|
||||
/* #define HAL_PCD_MODULE_ENABLED */
|
||||
/* #define HAL_HCD_MODULE_ENABLED */
|
||||
/* #define HAL_DFSDM_MODULE_ENABLED */
|
||||
/* #define HAL_DSI_MODULE_ENABLED */
|
||||
/* #define HAL_JPEG_MODULE_ENABLED */
|
||||
/* #define HAL_MDIOS_MODULE_ENABLED */
|
||||
|
||||
|
||||
/* ########################## HSE/HSI Values adaptation ##################### */
|
||||
/**
|
||||
* @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
|
||||
* This value is used by the RCC HAL module to compute the system frequency
|
||||
* (when HSE is used as system clock source, directly or through the PLL).
|
||||
*/
|
||||
#if !defined (HSE_VALUE)
|
||||
#define HSE_VALUE ((uint32_t)8000000U) /*!< Value of the External oscillator in Hz */
|
||||
#endif /* HSE_VALUE */
|
||||
|
||||
#if !defined (HSE_STARTUP_TIMEOUT)
|
||||
#define HSE_STARTUP_TIMEOUT ((uint32_t)100U) /*!< Time out for HSE start up, in ms */
|
||||
#endif /* HSE_STARTUP_TIMEOUT */
|
||||
|
||||
/**
|
||||
* @brief Internal High Speed oscillator (HSI) value.
|
||||
* This value is used by the RCC HAL module to compute the system frequency
|
||||
* (when HSI is used as system clock source, directly or through the PLL).
|
||||
*/
|
||||
#if !defined (HSI_VALUE)
|
||||
#define HSI_VALUE ((uint32_t)16000000U) /*!< Value of the Internal oscillator in Hz*/
|
||||
#endif /* HSI_VALUE */
|
||||
|
||||
/**
|
||||
* @brief Internal Low Speed oscillator (LSI) value.
|
||||
*/
|
||||
#if !defined (LSI_VALUE)
|
||||
#define LSI_VALUE ((uint32_t)32000U) /*!< LSI Typical Value in Hz*/
|
||||
#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz
|
||||
The real value may vary depending on the variations
|
||||
in voltage and temperature. */
|
||||
/**
|
||||
* @brief External Low Speed oscillator (LSE) value.
|
||||
*/
|
||||
#if !defined (LSE_VALUE)
|
||||
#define LSE_VALUE ((uint32_t)32768U) /*!< Value of the External Low Speed oscillator in Hz */
|
||||
#endif /* LSE_VALUE */
|
||||
|
||||
#if !defined (LSE_STARTUP_TIMEOUT)
|
||||
#define LSE_STARTUP_TIMEOUT ((uint32_t)5000U) /*!< Time out for LSE start up, in ms */
|
||||
#endif /* LSE_STARTUP_TIMEOUT */
|
||||
|
||||
/**
|
||||
* @brief External clock source for I2S peripheral
|
||||
* This value is used by the I2S HAL module to compute the I2S clock source
|
||||
* frequency, this source is inserted directly through I2S_CKIN pad.
|
||||
*/
|
||||
#if !defined (EXTERNAL_CLOCK_VALUE)
|
||||
#define EXTERNAL_CLOCK_VALUE ((uint32_t)12288000U) /*!< Value of the Internal oscillator in Hz*/
|
||||
#endif /* EXTERNAL_CLOCK_VALUE */
|
||||
|
||||
/* Tip: To avoid modifying this file each time you need to use different HSE,
|
||||
=== you can define the HSE value in your toolchain compiler preprocessor. */
|
||||
|
||||
/* ########################### System Configuration ######################### */
|
||||
/**
|
||||
* @brief This is the HAL system configuration section
|
||||
*/
|
||||
#define VDD_VALUE ((uint32_t)3300U) /*!< Value of VDD in mv */
|
||||
#define TICK_INT_PRIORITY ((uint32_t)0x0FU) /*!< tick interrupt priority */
|
||||
#define USE_RTOS 0U
|
||||
#define PREFETCH_ENABLE 1U
|
||||
#define ART_ACCLERATOR_ENABLE 1U /* To enable instruction cache and prefetch */
|
||||
|
||||
#define USE_HAL_ADC_REGISTER_CALLBACKS 0U /* ADC register callback disabled */
|
||||
#define USE_HAL_CAN_REGISTER_CALLBACKS 0U /* CAN register callback disabled */
|
||||
#define USE_HAL_CEC_REGISTER_CALLBACKS 0U /* CEC register callback disabled */
|
||||
#define USE_HAL_CRYP_REGISTER_CALLBACKS 0U /* CRYP register callback disabled */
|
||||
#define USE_HAL_DAC_REGISTER_CALLBACKS 0U /* DAC register callback disabled */
|
||||
#define USE_HAL_DCMI_REGISTER_CALLBACKS 0U /* DCMI register callback disabled */
|
||||
#define USE_HAL_DFSDM_REGISTER_CALLBACKS 0U /* DFSDM register callback disabled */
|
||||
#define USE_HAL_DMA2D_REGISTER_CALLBACKS 0U /* DMA2D register callback disabled */
|
||||
#define USE_HAL_DSI_REGISTER_CALLBACKS 0U /* DSI register callback disabled */
|
||||
#define USE_HAL_ETH_REGISTER_CALLBACKS 0U /* ETH register callback disabled */
|
||||
#define USE_HAL_HASH_REGISTER_CALLBACKS 0U /* HASH register callback disabled */
|
||||
#define USE_HAL_HCD_REGISTER_CALLBACKS 0U /* HCD register callback disabled */
|
||||
#define USE_HAL_I2C_REGISTER_CALLBACKS 0U /* I2C register callback disabled */
|
||||
#define USE_HAL_I2S_REGISTER_CALLBACKS 0U /* I2S register callback disabled */
|
||||
#define USE_HAL_IRDA_REGISTER_CALLBACKS 0U /* IRDA register callback disabled */
|
||||
#define USE_HAL_JPEG_REGISTER_CALLBACKS 0U /* JPEG register callback disabled */
|
||||
#define USE_HAL_LPTIM_REGISTER_CALLBACKS 0U /* LPTIM register callback disabled */
|
||||
#define USE_HAL_LTDC_REGISTER_CALLBACKS 0U /* LTDC register callback disabled */
|
||||
#define USE_HAL_MDIOS_REGISTER_CALLBACKS 0U /* MDIOS register callback disabled */
|
||||
#define USE_HAL_MMC_REGISTER_CALLBACKS 0U /* MMC register callback disabled */
|
||||
#define USE_HAL_NAND_REGISTER_CALLBACKS 0U /* NAND register callback disabled */
|
||||
#define USE_HAL_NOR_REGISTER_CALLBACKS 0U /* NOR register callback disabled */
|
||||
#define USE_HAL_PCD_REGISTER_CALLBACKS 0U /* PCD register callback disabled */
|
||||
#define USE_HAL_QSPI_REGISTER_CALLBACKS 0U /* QSPI register callback disabled */
|
||||
#define USE_HAL_RNG_REGISTER_CALLBACKS 0U /* RNG register callback disabled */
|
||||
#define USE_HAL_RTC_REGISTER_CALLBACKS 0U /* RTC register callback disabled */
|
||||
#define USE_HAL_SAI_REGISTER_CALLBACKS 0U /* SAI register callback disabled */
|
||||
#define USE_HAL_SD_REGISTER_CALLBACKS 0U /* SD register callback disabled */
|
||||
#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0U /* SMARTCARD register callback disabled */
|
||||
#define USE_HAL_SDRAM_REGISTER_CALLBACKS 0U /* SDRAM register callback disabled */
|
||||
#define USE_HAL_SRAM_REGISTER_CALLBACKS 0U /* SRAM register callback disabled */
|
||||
#define USE_HAL_SPDIFRX_REGISTER_CALLBACKS 0U /* SPDIFRX register callback disabled */
|
||||
#define USE_HAL_SMBUS_REGISTER_CALLBACKS 0U /* SMBUS register callback disabled */
|
||||
#define USE_HAL_SPI_REGISTER_CALLBACKS 0U /* SPI register callback disabled */
|
||||
#define USE_HAL_TIM_REGISTER_CALLBACKS 0U /* TIM register callback disabled */
|
||||
#define USE_HAL_UART_REGISTER_CALLBACKS 0U /* UART register callback disabled */
|
||||
#define USE_HAL_USART_REGISTER_CALLBACKS 0U /* USART register callback disabled */
|
||||
#define USE_HAL_WWDG_REGISTER_CALLBACKS 0U /* WWDG register callback disabled */
|
||||
|
||||
/* ########################## Assert Selection ############################## */
|
||||
/**
|
||||
* @brief Uncomment the line below to expanse the "assert_param" macro in the
|
||||
* HAL drivers code
|
||||
*/
|
||||
/* #define USE_FULL_ASSERT 1 */
|
||||
|
||||
/* ################## Ethernet peripheral configuration for NUCLEO 144 board ##################### */
|
||||
|
||||
/* Section 1 : Ethernet peripheral configuration */
|
||||
|
||||
/* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */
|
||||
#define MAC_ADDR0 2U
|
||||
#define MAC_ADDR1 0U
|
||||
#define MAC_ADDR2 0U
|
||||
#define MAC_ADDR3 0U
|
||||
#define MAC_ADDR4 0U
|
||||
#define MAC_ADDR5 0U
|
||||
|
||||
/* Definition of the Ethernet driver buffers size and count */
|
||||
#define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for receive */
|
||||
#define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for transmit */
|
||||
#define ETH_RXBUFNB ((uint32_t)5) /* 5 Rx buffers of size ETH_RX_BUF_SIZE */
|
||||
#define ETH_TXBUFNB ((uint32_t)5) /* 5 Tx buffers of size ETH_TX_BUF_SIZE */
|
||||
|
||||
/* Section 2: PHY configuration section */
|
||||
/* LAN8742A PHY Address*/
|
||||
#define LAN8742A_PHY_ADDRESS 0x00
|
||||
/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/
|
||||
#define PHY_RESET_DELAY ((uint32_t)0x00000FFF)
|
||||
/* PHY Configuration delay */
|
||||
#define PHY_CONFIG_DELAY ((uint32_t)0x00000FFF)
|
||||
|
||||
#define PHY_READ_TO ((uint32_t)0x0000FFFF)
|
||||
#define PHY_WRITE_TO ((uint32_t)0x0000FFFF)
|
||||
|
||||
/* Section 3: Common PHY Registers */
|
||||
|
||||
#define PHY_BCR ((uint16_t)0x00) /*!< Transceiver Basic Control Register */
|
||||
#define PHY_BSR ((uint16_t)0x01) /*!< Transceiver Basic Status Register */
|
||||
|
||||
#define PHY_RESET ((uint16_t)0x8000) /*!< PHY Reset */
|
||||
#define PHY_LOOPBACK ((uint16_t)0x4000) /*!< Select loop-back mode */
|
||||
#define PHY_FULLDUPLEX_100M ((uint16_t)0x2100) /*!< Set the full-duplex mode at 100 Mb/s */
|
||||
#define PHY_HALFDUPLEX_100M ((uint16_t)0x2000) /*!< Set the half-duplex mode at 100 Mb/s */
|
||||
#define PHY_FULLDUPLEX_10M ((uint16_t)0x0100) /*!< Set the full-duplex mode at 10 Mb/s */
|
||||
#define PHY_HALFDUPLEX_10M ((uint16_t)0x0000) /*!< Set the half-duplex mode at 10 Mb/s */
|
||||
#define PHY_AUTONEGOTIATION ((uint16_t)0x1000) /*!< Enable auto-negotiation function */
|
||||
#define PHY_RESTART_AUTONEGOTIATION ((uint16_t)0x0200) /*!< Restart auto-negotiation function */
|
||||
#define PHY_POWERDOWN ((uint16_t)0x0800) /*!< Select the power down mode */
|
||||
#define PHY_ISOLATE ((uint16_t)0x0400) /*!< Isolate PHY from MII */
|
||||
|
||||
#define PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020) /*!< Auto-Negotiation process completed */
|
||||
#define PHY_LINKED_STATUS ((uint16_t)0x0004) /*!< Valid link established */
|
||||
#define PHY_JABBER_DETECTION ((uint16_t)0x0002) /*!< Jabber condition detected */
|
||||
|
||||
/* Section 4: Extended PHY Registers */
|
||||
|
||||
#define PHY_SR ((uint16_t)0x1F) /*!< PHY special control/ status register Offset */
|
||||
|
||||
#define PHY_SPEED_STATUS ((uint16_t)0x0004) /*!< PHY Speed mask */
|
||||
#define PHY_DUPLEX_STATUS ((uint16_t)0x0010) /*!< PHY Duplex mask */
|
||||
|
||||
|
||||
#define PHY_ISFR ((uint16_t)0x1D) /*!< PHY Interrupt Source Flag register Offset */
|
||||
#define PHY_ISFR_INT4 ((uint16_t)0x0010) /*!< PHY Link down inturrupt */
|
||||
|
||||
/* ################## SPI peripheral configuration ########################## */
|
||||
|
||||
/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver
|
||||
* Activated: CRC code is present inside driver
|
||||
* Deactivated: CRC code cleaned from driver
|
||||
*/
|
||||
|
||||
#define USE_SPI_CRC 1U
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
/**
|
||||
* @brief Include module's header file
|
||||
*/
|
||||
|
||||
#ifdef HAL_RCC_MODULE_ENABLED
|
||||
#include "stm32f7xx_hal_rcc.h"
|
||||
#endif /* HAL_RCC_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_GPIO_MODULE_ENABLED
|
||||
#include "stm32f7xx_hal_gpio.h"
|
||||
#endif /* HAL_GPIO_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_DMA_MODULE_ENABLED
|
||||
#include "stm32f7xx_hal_dma.h"
|
||||
#endif /* HAL_DMA_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_CORTEX_MODULE_ENABLED
|
||||
#include "stm32f7xx_hal_cortex.h"
|
||||
#endif /* HAL_CORTEX_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_ADC_MODULE_ENABLED
|
||||
#include "stm32f7xx_hal_adc.h"
|
||||
#endif /* HAL_ADC_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_CAN_MODULE_ENABLED
|
||||
#include "stm32f7xx_hal_can.h"
|
||||
#endif /* HAL_CAN_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_CAN_LEGACY_MODULE_ENABLED
|
||||
#include "stm32f7xx_hal_can_legacy.h"
|
||||
#endif /* HAL_CAN_LEGACY_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_CEC_MODULE_ENABLED
|
||||
#include "stm32f7xx_hal_cec.h"
|
||||
#endif /* HAL_CEC_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_CRC_MODULE_ENABLED
|
||||
#include "stm32f7xx_hal_crc.h"
|
||||
#endif /* HAL_CRC_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_CRYP_MODULE_ENABLED
|
||||
#include "stm32f7xx_hal_cryp.h"
|
||||
#endif /* HAL_CRYP_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_DMA2D_MODULE_ENABLED
|
||||
#include "stm32f7xx_hal_dma2d.h"
|
||||
#endif /* HAL_DMA2D_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_DAC_MODULE_ENABLED
|
||||
#include "stm32f7xx_hal_dac.h"
|
||||
#endif /* HAL_DAC_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_DCMI_MODULE_ENABLED
|
||||
#include "stm32f7xx_hal_dcmi.h"
|
||||
#endif /* HAL_DCMI_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_ETH_MODULE_ENABLED
|
||||
#include "stm32f7xx_hal_eth.h"
|
||||
#endif /* HAL_ETH_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_FLASH_MODULE_ENABLED
|
||||
#include "stm32f7xx_hal_flash.h"
|
||||
#endif /* HAL_FLASH_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_SRAM_MODULE_ENABLED
|
||||
#include "stm32f7xx_hal_sram.h"
|
||||
#endif /* HAL_SRAM_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_NOR_MODULE_ENABLED
|
||||
#include "stm32f7xx_hal_nor.h"
|
||||
#endif /* HAL_NOR_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_NAND_MODULE_ENABLED
|
||||
#include "stm32f7xx_hal_nand.h"
|
||||
#endif /* HAL_NAND_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_SDRAM_MODULE_ENABLED
|
||||
#include "stm32f7xx_hal_sdram.h"
|
||||
#endif /* HAL_SDRAM_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_HASH_MODULE_ENABLED
|
||||
#include "stm32f7xx_hal_hash.h"
|
||||
#endif /* HAL_HASH_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_I2C_MODULE_ENABLED
|
||||
#include "stm32f7xx_hal_i2c.h"
|
||||
#endif /* HAL_I2C_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_I2S_MODULE_ENABLED
|
||||
#include "stm32f7xx_hal_i2s.h"
|
||||
#endif /* HAL_I2S_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_IWDG_MODULE_ENABLED
|
||||
#include "stm32f7xx_hal_iwdg.h"
|
||||
#endif /* HAL_IWDG_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_LPTIM_MODULE_ENABLED
|
||||
#include "stm32f7xx_hal_lptim.h"
|
||||
#endif /* HAL_LPTIM_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_LTDC_MODULE_ENABLED
|
||||
#include "stm32f7xx_hal_ltdc.h"
|
||||
#endif /* HAL_LTDC_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_PWR_MODULE_ENABLED
|
||||
#include "stm32f7xx_hal_pwr.h"
|
||||
#endif /* HAL_PWR_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_QSPI_MODULE_ENABLED
|
||||
#include "stm32f7xx_hal_qspi.h"
|
||||
#endif /* HAL_QSPI_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_RNG_MODULE_ENABLED
|
||||
#include "stm32f7xx_hal_rng.h"
|
||||
#endif /* HAL_RNG_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_RTC_MODULE_ENABLED
|
||||
#include "stm32f7xx_hal_rtc.h"
|
||||
#endif /* HAL_RTC_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_SAI_MODULE_ENABLED
|
||||
#include "stm32f7xx_hal_sai.h"
|
||||
#endif /* HAL_SAI_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_SD_MODULE_ENABLED
|
||||
#include "stm32f7xx_hal_sd.h"
|
||||
#endif /* HAL_SD_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_SPDIFRX_MODULE_ENABLED
|
||||
#include "stm32f7xx_hal_spdifrx.h"
|
||||
#endif /* HAL_SPDIFRX_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_SPI_MODULE_ENABLED
|
||||
#include "stm32f7xx_hal_spi.h"
|
||||
#endif /* HAL_SPI_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_TIM_MODULE_ENABLED
|
||||
#include "stm32f7xx_hal_tim.h"
|
||||
#endif /* HAL_TIM_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_UART_MODULE_ENABLED
|
||||
#include "stm32f7xx_hal_uart.h"
|
||||
#endif /* HAL_UART_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_USART_MODULE_ENABLED
|
||||
#include "stm32f7xx_hal_usart.h"
|
||||
#endif /* HAL_USART_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_IRDA_MODULE_ENABLED
|
||||
#include "stm32f7xx_hal_irda.h"
|
||||
#endif /* HAL_IRDA_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_SMARTCARD_MODULE_ENABLED
|
||||
#include "stm32f7xx_hal_smartcard.h"
|
||||
#endif /* HAL_SMARTCARD_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_WWDG_MODULE_ENABLED
|
||||
#include "stm32f7xx_hal_wwdg.h"
|
||||
#endif /* HAL_WWDG_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_PCD_MODULE_ENABLED
|
||||
#include "stm32f7xx_hal_pcd.h"
|
||||
#endif /* HAL_PCD_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_HCD_MODULE_ENABLED
|
||||
#include "stm32f7xx_hal_hcd.h"
|
||||
#endif /* HAL_HCD_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_DFSDM_MODULE_ENABLED
|
||||
#include "stm32f7xx_hal_dfsdm.h"
|
||||
#endif /* HAL_DFSDM_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_DSI_MODULE_ENABLED
|
||||
#include "stm32f7xx_hal_dsi.h"
|
||||
#endif /* HAL_DSI_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_JPEG_MODULE_ENABLED
|
||||
#include "stm32f7xx_hal_jpeg.h"
|
||||
#endif /* HAL_JPEG_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_MDIOS_MODULE_ENABLED
|
||||
#include "stm32f7xx_hal_mdios.h"
|
||||
#endif /* HAL_MDIOS_MODULE_ENABLED */
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
#ifdef USE_FULL_ASSERT
|
||||
/**
|
||||
* @brief The assert_param macro is used for function's parameters check.
|
||||
* @param expr: If expr is false, it calls assert_failed function
|
||||
* which reports the name of the source file and the source
|
||||
* line number of the call that failed.
|
||||
* If expr is true, it returns no value.
|
||||
* @retval None
|
||||
*/
|
||||
#define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
|
||||
/* Exported functions ------------------------------------------------------- */
|
||||
void assert_failed(uint8_t* file, uint32_t line);
|
||||
#else
|
||||
#define assert_param(expr) ((void)0U)
|
||||
#endif /* USE_FULL_ASSERT */
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F7xx_HAL_CONF_H */
|
||||
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -9,8 +9,8 @@ CFLAGS += \
|
|||
-DSTM32F767xx \
|
||||
-DCFG_TUSB_MCU=OPT_MCU_STM32F7
|
||||
|
||||
# mcu driver cause following warnings
|
||||
CFLAGS += -Wno-error=shadow
|
||||
# suppress warning caused by vendor mcu driver
|
||||
CFLAGS += -Wno-error=cast-align -Wno-error=shadow
|
||||
|
||||
ST_HAL_DRIVER = hw/mcu/st/st_driver/STM32F7xx_HAL_Driver
|
||||
ST_CMSIS = hw/mcu/st/st_driver/CMSIS/Device/ST/STM32F7xx
|
||||
|
|
|
|||
|
|
@ -10,7 +10,6 @@ CFLAGS += \
|
|||
-DCFG_TUSB_MCU=OPT_MCU_STM32H7
|
||||
|
||||
# mcu driver cause following warnings
|
||||
CFLAGS += -Wno-error=maybe-uninitialized
|
||||
|
||||
ST_HAL_DRIVER = hw/mcu/st/st_driver/STM32H7xx_HAL_Driver
|
||||
ST_CMSIS = hw/mcu/st/st_driver/CMSIS/Device/ST/STM32H7xx
|
||||
|
|
|
|||
|
|
@ -86,14 +86,19 @@ static void SystemClock_Config(void)
|
|||
RCC_OscInitTypeDef RCC_OscInitStruct;
|
||||
RCC_PeriphCLKInitTypeDef PeriphClkInitStruct;
|
||||
|
||||
/* Enable the LSE Oscilator */
|
||||
/* Enable the LSE Oscillator */
|
||||
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE;
|
||||
RCC_OscInitStruct.LSEState = RCC_LSE_ON;
|
||||
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
|
||||
HAL_RCC_OscConfig(&RCC_OscInitStruct);
|
||||
|
||||
/* Enable the CSS interrupt in case LSE signal is corrupted or not present */
|
||||
HAL_RCCEx_DisableLSECSS();
|
||||
|
||||
/* Set tick interrupt priority, default HAL value is intentionally invalid
|
||||
and that prevents PLL initialization in HAL_RCC_OscConfig() */
|
||||
HAL_InitTick((1UL << __NVIC_PRIO_BITS) - 1UL);
|
||||
|
||||
/* Enable MSI Oscillator and activate PLL with MSI as source */
|
||||
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI;
|
||||
RCC_OscInitStruct.MSIState = RCC_MSI_ON;
|
||||
|
|
|
|||
5
pkg.yml
5
pkg.yml
|
|
@ -5,5 +5,10 @@ pkg.homepage: "https://github.com/hathach/tinyusb"
|
|||
pkg.keywords:
|
||||
- usb
|
||||
|
||||
pkg.type: sdk
|
||||
|
||||
pkg.deps:
|
||||
- "@apache-mynewt-core/kernel/os"
|
||||
|
||||
pkg.include_dirs:
|
||||
- src
|
||||
|
|
|
|||
|
|
@ -106,7 +106,7 @@ static inline uint16_t tu_max16 (uint16_t x, uint16_t y) { return (x > y) ? x :
|
|||
static inline uint32_t tu_max32 (uint32_t x, uint32_t y) { return (x > y) ? x : y; }
|
||||
|
||||
// Align
|
||||
static inline uint32_t tu_align_n(uint32_t value, uint32_t alignment)
|
||||
static inline uint32_t tu_align(uint32_t value, uint32_t alignment)
|
||||
{
|
||||
return value & ((uint32_t) ~(alignment-1));
|
||||
}
|
||||
|
|
@ -215,8 +215,11 @@ static inline bool tu_bit_test (uint32_t value, uint8_t pos) { return (value
|
|||
|
||||
void tu_print_mem(void const *buf, uint16_t count, uint8_t indent);
|
||||
|
||||
#ifndef tu_printf
|
||||
#define tu_printf printf
|
||||
#ifdef CFG_TUSB_DEBUG_PRINTF
|
||||
extern int CFG_TUSB_DEBUG_PRINTF(const char *format, ...);
|
||||
#define tu_printf CFG_TUSB_DEBUG_PRINTF
|
||||
#else
|
||||
#define tu_printf printf
|
||||
#endif
|
||||
|
||||
static inline
|
||||
|
|
|
|||
|
|
@ -99,7 +99,26 @@
|
|||
#define TU_BSWAP16(u16) (__builtin_bswap16(u16))
|
||||
#define TU_BSWAP32(u32) (__builtin_bswap32(u32))
|
||||
|
||||
#else
|
||||
#elif defined(__ICCARM__)
|
||||
#define TU_ATTR_ALIGNED(Bytes) __attribute__ ((aligned(Bytes)))
|
||||
#define TU_ATTR_SECTION(sec_name) __attribute__ ((section(#sec_name)))
|
||||
#define TU_ATTR_PACKED __attribute__ ((packed))
|
||||
#define TU_ATTR_PREPACKED
|
||||
#define TU_ATTR_WEAK __attribute__ ((weak))
|
||||
#define TU_ATTR_DEPRECATED(mess) __attribute__ ((deprecated(mess))) // warn if function with this attribute is used
|
||||
#define TU_ATTR_UNUSED __attribute__ ((unused)) // Function/Variable is meant to be possibly unused
|
||||
#define TU_ATTR_USED __attribute__ ((used)) // Function/Variable is meant to be used
|
||||
|
||||
// Endian conversion use well-known host to network (big endian) naming
|
||||
#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__
|
||||
#define TU_BYTE_ORDER TU_LITTLE_ENDIAN
|
||||
#else
|
||||
#define TU_BYTE_ORDER TU_BIG_ENDIAN
|
||||
#endif
|
||||
|
||||
#define TU_BSWAP16(u16) (__iar_builtin_REV16(u16))
|
||||
#define TU_BSWAP32(u32) (__iar_builtin_REV(u32))
|
||||
#else
|
||||
#error "Compiler attribute porting is required"
|
||||
#endif
|
||||
|
||||
|
|
|
|||
|
|
@ -71,41 +71,46 @@ bool tu_fifo_config(tu_fifo_t *f, void* buffer, uint16_t depth, uint16_t item_si
|
|||
return true;
|
||||
}
|
||||
|
||||
static inline uint16_t _ff_mod(uint16_t idx, uint16_t depth)
|
||||
{
|
||||
return (idx < depth) ? idx : (idx-depth);
|
||||
}
|
||||
|
||||
// retrieve data from fifo
|
||||
static void _tu_ff_pull(tu_fifo_t* f, void * buffer)
|
||||
static inline void _ff_pull(tu_fifo_t* f, void * buffer, uint16_t n)
|
||||
{
|
||||
memcpy(buffer,
|
||||
f->buffer + (f->rd_idx * f->item_size),
|
||||
f->item_size);
|
||||
f->item_size*n);
|
||||
|
||||
f->rd_idx = (f->rd_idx + 1) % f->depth;
|
||||
f->count--;
|
||||
f->rd_idx = _ff_mod(f->rd_idx + n, f->depth);
|
||||
f->count -= n;
|
||||
}
|
||||
|
||||
// send data to fifo
|
||||
static void _tu_ff_push(tu_fifo_t* f, void const * data)
|
||||
static inline void _ff_push(tu_fifo_t* f, void const * data, uint16_t n)
|
||||
{
|
||||
memcpy( f->buffer + (f->wr_idx * f->item_size),
|
||||
data,
|
||||
f->item_size);
|
||||
memcpy(f->buffer + (f->wr_idx * f->item_size),
|
||||
data,
|
||||
f->item_size*n);
|
||||
|
||||
f->wr_idx = (f->wr_idx + 1) % f->depth;
|
||||
f->wr_idx = _ff_mod(f->wr_idx + n, f->depth);
|
||||
|
||||
if (tu_fifo_full(f))
|
||||
{
|
||||
f->rd_idx = f->wr_idx; // keep the full state (rd == wr && len = size)
|
||||
f->rd_idx = f->wr_idx; // keep the full state (rd == wr && count = depth)
|
||||
}
|
||||
else
|
||||
{
|
||||
f->count++;
|
||||
f->count += n;
|
||||
}
|
||||
}
|
||||
|
||||
/******************************************************************************/
|
||||
/*!
|
||||
@brief Read one byte out of the RX buffer.
|
||||
@brief Read one element out of the RX buffer.
|
||||
|
||||
This function will return the byte located at the array index of the
|
||||
This function will return the element located at the array index of the
|
||||
read pointer, and then increment the read pointer index. If the read
|
||||
pointer exceeds the maximum buffer size, it will roll over to zero.
|
||||
|
||||
|
|
@ -123,7 +128,7 @@ bool tu_fifo_read(tu_fifo_t* f, void * buffer)
|
|||
|
||||
tu_fifo_lock(f);
|
||||
|
||||
_tu_ff_pull(f, buffer);
|
||||
_ff_pull(f, buffer, 1);
|
||||
|
||||
tu_fifo_unlock(f);
|
||||
|
||||
|
|
@ -132,8 +137,8 @@ bool tu_fifo_read(tu_fifo_t* f, void * buffer)
|
|||
|
||||
/******************************************************************************/
|
||||
/*!
|
||||
@brief This function will read n elements into the array index specified by
|
||||
the write pointer and increment the write index. If the write index
|
||||
@brief This function will read n elements from the array index specified by
|
||||
the read pointer and increment the read index. If the read index
|
||||
exceeds the max buffer size, then it will roll over to zero.
|
||||
|
||||
@param[in] f
|
||||
|
|
@ -148,32 +153,37 @@ bool tu_fifo_read(tu_fifo_t* f, void * buffer)
|
|||
/******************************************************************************/
|
||||
uint16_t tu_fifo_read_n (tu_fifo_t* f, void * buffer, uint16_t count)
|
||||
{
|
||||
if( tu_fifo_empty(f) ) return 0;
|
||||
if(tu_fifo_empty(f)) return 0;
|
||||
|
||||
tu_fifo_lock(f);
|
||||
|
||||
/* Limit up to fifo's count */
|
||||
if ( count > f->count ) count = f->count;
|
||||
// Limit up to fifo's count
|
||||
if(count > f->count) count = f->count;
|
||||
|
||||
uint8_t* buf8 = (uint8_t*) buffer;
|
||||
uint16_t len = 0;
|
||||
|
||||
while (len < count)
|
||||
if(count + f->rd_idx <= f->depth)
|
||||
{
|
||||
_tu_ff_pull(f, buf8);
|
||||
_ff_pull(f, buffer, count);
|
||||
}
|
||||
else
|
||||
{
|
||||
uint16_t const part1 = f->depth - f->rd_idx;
|
||||
|
||||
len++;
|
||||
buf8 += f->item_size;
|
||||
// Part 1: from rd_idx to end
|
||||
_ff_pull(f, buffer, part1);
|
||||
buffer = ((uint8_t*) buffer) + part1*f->item_size;
|
||||
|
||||
// Part 2: start to remaining
|
||||
_ff_pull(f, buffer, count-part1);
|
||||
}
|
||||
|
||||
tu_fifo_unlock(f);
|
||||
|
||||
return len;
|
||||
return count;
|
||||
}
|
||||
|
||||
/******************************************************************************/
|
||||
/*!
|
||||
@brief Reads one item without removing it from the FIFO
|
||||
@brief Read one item without removing it from the FIFO
|
||||
|
||||
@param[in] f
|
||||
Pointer to the FIFO buffer to manipulate
|
||||
|
|
@ -189,12 +199,16 @@ bool tu_fifo_peek_at(tu_fifo_t* f, uint16_t pos, void * p_buffer)
|
|||
{
|
||||
if ( pos >= f->count ) return false;
|
||||
|
||||
tu_fifo_lock(f);
|
||||
|
||||
// rd_idx is pos=0
|
||||
uint16_t index = (f->rd_idx + pos) % f->depth;
|
||||
uint16_t index = _ff_mod(f->rd_idx + pos, f->depth);
|
||||
memcpy(p_buffer,
|
||||
f->buffer + (index * f->item_size),
|
||||
f->item_size);
|
||||
|
||||
tu_fifo_unlock(f);
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
|
|
@ -221,7 +235,7 @@ bool tu_fifo_write (tu_fifo_t* f, const void * data)
|
|||
|
||||
tu_fifo_lock(f);
|
||||
|
||||
_tu_ff_push(f, data);
|
||||
_ff_push(f, data, 1);
|
||||
|
||||
tu_fifo_unlock(f);
|
||||
|
||||
|
|
@ -249,23 +263,42 @@ uint16_t tu_fifo_write_n (tu_fifo_t* f, const void * data, uint16_t count)
|
|||
|
||||
tu_fifo_lock(f);
|
||||
|
||||
// Not overwritable limit up to full
|
||||
if (!f->overwritable) count = tu_min16(count, tu_fifo_remaining(f));
|
||||
|
||||
uint8_t const* buf8 = (uint8_t const*) data;
|
||||
uint16_t len = 0;
|
||||
|
||||
while (len < count)
|
||||
if (!f->overwritable)
|
||||
{
|
||||
_tu_ff_push(f, buf8);
|
||||
|
||||
len++;
|
||||
buf8 += f->item_size;
|
||||
// Not overwritable limit up to full
|
||||
count = tu_min16(count, tu_fifo_remaining(f));
|
||||
}
|
||||
else if (count > f->depth)
|
||||
{
|
||||
// Only copy last part
|
||||
buf8 = buf8 + (count - f->depth) * f->item_size;
|
||||
count = f->depth;
|
||||
f->wr_idx = 0;
|
||||
f->rd_idx = 0;
|
||||
f->count = 0;
|
||||
}
|
||||
|
||||
if (count + f->wr_idx <= f->depth )
|
||||
{
|
||||
_ff_push(f, buf8, count);
|
||||
}
|
||||
else
|
||||
{
|
||||
uint16_t const part1 = f->depth - f->wr_idx;
|
||||
|
||||
// Part 1: from wr_idx to end
|
||||
_ff_push(f, buf8, part1);
|
||||
buf8 += part1*f->item_size;
|
||||
|
||||
// Part 2: start to remaining
|
||||
_ff_push(f, buf8, count-part1);
|
||||
}
|
||||
|
||||
tu_fifo_unlock(f);
|
||||
|
||||
return len;
|
||||
return count;
|
||||
}
|
||||
|
||||
/******************************************************************************/
|
||||
|
|
|
|||
|
|
@ -339,6 +339,14 @@ static void usbd_reset(uint8_t rhport)
|
|||
}
|
||||
}
|
||||
|
||||
bool tud_task_event_ready(void)
|
||||
{
|
||||
// Skip if stack is not initialized
|
||||
if ( !tusb_inited() ) return false;
|
||||
|
||||
return !osal_queue_empty(_usbd_q);
|
||||
}
|
||||
|
||||
/* USB Device Driver task
|
||||
* This top level thread manages all device controller event and delegates events to class-specific drivers.
|
||||
* This should be called periodically within the mainloop or rtos thread.
|
||||
|
|
|
|||
|
|
@ -47,6 +47,9 @@ bool tud_init (void);
|
|||
// Task function should be called in main/rtos loop
|
||||
void tud_task (void);
|
||||
|
||||
// Check if there is pending events need proccessing by tud_task()
|
||||
bool tud_task_event_ready(void);
|
||||
|
||||
// Interrupt handler, name alias to DCD
|
||||
#define tud_int_handler dcd_int_handler
|
||||
|
||||
|
|
|
|||
|
|
@ -32,6 +32,10 @@
|
|||
#include "device/usbd_pvt.h"
|
||||
#include "dcd.h"
|
||||
|
||||
#if CFG_TUSB_DEBUG >= 2
|
||||
extern void usbd_driver_print_control_complete_name(bool (*control_complete) (uint8_t, tusb_control_request_t const *));
|
||||
#endif
|
||||
|
||||
enum
|
||||
{
|
||||
EDPT_CTRL_OUT = 0x00,
|
||||
|
|
@ -192,7 +196,6 @@ bool usbd_control_xfer_cb (uint8_t rhport, uint8_t ep_addr, xfer_result_t result
|
|||
if ( _ctrl_xfer.complete_cb )
|
||||
{
|
||||
#if CFG_TUSB_DEBUG >= 2
|
||||
extern void usbd_driver_print_control_complete_name(bool (*control_complete) (uint8_t, tusb_control_request_t const *));
|
||||
usbd_driver_print_control_complete_name(_ctrl_xfer.complete_cb);
|
||||
#endif
|
||||
|
||||
|
|
|
|||
|
|
@ -78,8 +78,9 @@ static inline bool osal_mutex_unlock(osal_mutex_t mutex_hdl);
|
|||
|
||||
//------------- Queue -------------//
|
||||
static inline osal_queue_t osal_queue_create(osal_queue_def_t* qdef);
|
||||
static inline bool osal_queue_receive(osal_queue_t const qhdl, void* data);
|
||||
static inline bool osal_queue_send(osal_queue_t const qhdl, void const * data, bool in_isr);
|
||||
static inline bool osal_queue_receive(osal_queue_t qhdl, void* data);
|
||||
static inline bool osal_queue_send(osal_queue_t qhdl, void const * data, bool in_isr);
|
||||
static inline bool osal_queue_empty(osal_queue_t qhdl);
|
||||
|
||||
#if 0 // TODO remove subtask related macros later
|
||||
// Sub Task
|
||||
|
|
|
|||
|
|
@ -118,14 +118,19 @@ static inline osal_queue_t osal_queue_create(osal_queue_def_t* qdef)
|
|||
return xQueueCreateStatic(qdef->depth, qdef->item_sz, (uint8_t*) qdef->buf, &qdef->sq);
|
||||
}
|
||||
|
||||
static inline bool osal_queue_receive(osal_queue_t const queue_hdl, void* data)
|
||||
static inline bool osal_queue_receive(osal_queue_t qhdl, void* data)
|
||||
{
|
||||
return xQueueReceive(queue_hdl, data, portMAX_DELAY);
|
||||
return xQueueReceive(qhdl, data, portMAX_DELAY);
|
||||
}
|
||||
|
||||
static inline bool osal_queue_send(osal_queue_t const queue_hdl, void const * data, bool in_isr)
|
||||
static inline bool osal_queue_send(osal_queue_t qhdl, void const * data, bool in_isr)
|
||||
{
|
||||
return in_isr ? xQueueSendToBackFromISR(queue_hdl, data, NULL) : xQueueSendToBack(queue_hdl, data, OSAL_TIMEOUT_WAIT_FOREVER);
|
||||
return in_isr ? xQueueSendToBackFromISR(qhdl, data, NULL) : xQueueSendToBack(qhdl, data, OSAL_TIMEOUT_WAIT_FOREVER);
|
||||
}
|
||||
|
||||
static inline bool osal_queue_empty(osal_queue_t qhdl)
|
||||
{
|
||||
return uxQueueMessagesWaiting(qhdl) == 0;
|
||||
}
|
||||
|
||||
#ifdef __cplusplus
|
||||
|
|
|
|||
|
|
@ -125,7 +125,7 @@ static inline osal_queue_t osal_queue_create(osal_queue_def_t* qdef)
|
|||
return (osal_queue_t) qdef;
|
||||
}
|
||||
|
||||
static inline bool osal_queue_receive(osal_queue_t const qhdl, void* data)
|
||||
static inline bool osal_queue_receive(osal_queue_t qhdl, void* data)
|
||||
{
|
||||
struct os_event* ev;
|
||||
ev = os_eventq_get(&qhdl->evq);
|
||||
|
|
@ -137,7 +137,7 @@ static inline bool osal_queue_receive(osal_queue_t const qhdl, void* data)
|
|||
return true;
|
||||
}
|
||||
|
||||
static inline bool osal_queue_send(osal_queue_t const qhdl, void const * data, bool in_isr)
|
||||
static inline bool osal_queue_send(osal_queue_t qhdl, void const * data, bool in_isr)
|
||||
{
|
||||
(void) in_isr;
|
||||
|
||||
|
|
@ -161,6 +161,12 @@ static inline bool osal_queue_send(osal_queue_t const qhdl, void const * data, b
|
|||
return true;
|
||||
}
|
||||
|
||||
static inline bool osal_queue_empty(osal_queue_t qhdl)
|
||||
{
|
||||
return STAILQ_EMPTY(&qhdl->evq.evq_list);
|
||||
}
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -142,7 +142,7 @@ typedef osal_queue_def_t* osal_queue_t;
|
|||
}\
|
||||
}
|
||||
|
||||
// lock queue by disable usb isr
|
||||
// lock queue by disable USB interrupt
|
||||
static inline void _osal_q_lock(osal_queue_t qhdl)
|
||||
{
|
||||
(void) qhdl;
|
||||
|
|
@ -176,8 +176,7 @@ static inline osal_queue_t osal_queue_create(osal_queue_def_t* qdef)
|
|||
return (osal_queue_t) qdef;
|
||||
}
|
||||
|
||||
// non blocking
|
||||
static inline bool osal_queue_receive(osal_queue_t const qhdl, void* data)
|
||||
static inline bool osal_queue_receive(osal_queue_t qhdl, void* data)
|
||||
{
|
||||
_osal_q_lock(qhdl);
|
||||
bool success = tu_fifo_read(&qhdl->ff, data);
|
||||
|
|
@ -186,7 +185,7 @@ static inline bool osal_queue_receive(osal_queue_t const qhdl, void* data)
|
|||
return success;
|
||||
}
|
||||
|
||||
static inline bool osal_queue_send(osal_queue_t const qhdl, void const * data, bool in_isr)
|
||||
static inline bool osal_queue_send(osal_queue_t qhdl, void const * data, bool in_isr)
|
||||
{
|
||||
if (!in_isr) {
|
||||
_osal_q_lock(qhdl);
|
||||
|
|
@ -203,6 +202,13 @@ static inline bool osal_queue_send(osal_queue_t const qhdl, void const * data, b
|
|||
return success;
|
||||
}
|
||||
|
||||
static inline bool osal_queue_empty(osal_queue_t qhdl)
|
||||
{
|
||||
// Skip queue lock/unlock since this function is primarily called
|
||||
// with interrupt disabled before going into low power mode
|
||||
return tu_fifo_empty(&qhdl->ff);
|
||||
}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -32,13 +32,6 @@
|
|||
#include "nrf_clock.h"
|
||||
#include "nrf_power.h"
|
||||
#include "nrfx_usbd_errata.h"
|
||||
|
||||
#ifdef SOFTDEVICE_PRESENT
|
||||
// For enable/disable hfclk with SoftDevice
|
||||
#include "nrf_sdm.h"
|
||||
#include "nrf_soc.h"
|
||||
#endif
|
||||
|
||||
#include "device/dcd.h"
|
||||
|
||||
// TODO remove later
|
||||
|
|
@ -58,6 +51,11 @@ enum
|
|||
USBD_INTENCLR_ENDISOIN_Msk | USBD_INTEN_ENDISOOUT_Msk
|
||||
};
|
||||
|
||||
enum
|
||||
{
|
||||
EP_COUNT = 8
|
||||
};
|
||||
|
||||
// Transfer descriptor
|
||||
typedef struct
|
||||
{
|
||||
|
|
@ -76,36 +74,73 @@ typedef struct
|
|||
static struct
|
||||
{
|
||||
// All 8 endpoints including control IN & OUT (offset 1)
|
||||
xfer_td_t xfer[8][2];
|
||||
xfer_td_t xfer[EP_COUNT][2];
|
||||
|
||||
// Only one DMA can run at a time
|
||||
volatile bool dma_running;
|
||||
// Number of pending DMA that is started but not handled yet by dcd_int_handler().
|
||||
// Since nRF can only carry one DMA can run at a time, this value is normally be either 0 or 1.
|
||||
// However, in critical section with interrupt disabled, the DMA can be finished and added up
|
||||
// until handled by dcd_init_handler() when exiting critical section.
|
||||
volatile uint8_t dma_pending;
|
||||
}_dcd;
|
||||
|
||||
/*------------------------------------------------------------------*/
|
||||
/* Control / Bulk / Interrupt (CBI) Transfer
|
||||
*------------------------------------------------------------------*/
|
||||
|
||||
// NVIC_GetEnableIRQ is only available in CMSIS v5
|
||||
#ifndef NVIC_GetEnableIRQ
|
||||
static inline uint32_t NVIC_GetEnableIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
if ((int32_t)(IRQn) >= 0)
|
||||
{
|
||||
return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
|
||||
}
|
||||
else
|
||||
{
|
||||
return(0U);
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
// helper to start DMA
|
||||
static void edpt_dma_start(volatile uint32_t* reg_startep)
|
||||
{
|
||||
// Only one dma can be active
|
||||
if ( _dcd.dma_running )
|
||||
if ( _dcd.dma_pending )
|
||||
{
|
||||
if (SCB->ICSR & SCB_ICSR_VECTACTIVE_Msk)
|
||||
{
|
||||
// If called within ISR, use usbd task to defer later
|
||||
// Called within ISR, use usbd task to defer later
|
||||
usbd_defer_func( (osal_task_func_t) edpt_dma_start, (void*) reg_startep, true );
|
||||
return;
|
||||
}
|
||||
else
|
||||
{
|
||||
// Otherwise simply block wait
|
||||
while ( _dcd.dma_running ) { }
|
||||
if ( __get_PRIMASK() || !NVIC_GetEnableIRQ(USBD_IRQn) )
|
||||
{
|
||||
// Called in critical section with interrupt disabled. We have to manually check
|
||||
// for the DMA complete by comparing current pending DMA with number of ENDED Events
|
||||
uint32_t ended = 0;
|
||||
|
||||
while ( _dcd.dma_pending < ((uint8_t) ended) )
|
||||
{
|
||||
ended = NRF_USBD->EVENTS_ENDISOIN + NRF_USBD->EVENTS_ENDISOOUT;
|
||||
|
||||
for (uint8_t i=0; i<EP_COUNT; i++)
|
||||
{
|
||||
ended += NRF_USBD->EVENTS_ENDEPIN[i] + NRF_USBD->EVENTS_ENDEPOUT[i];
|
||||
}
|
||||
}
|
||||
}else
|
||||
{
|
||||
// Called in non-critical thread-mode, should be 99% of the time.
|
||||
// Should be safe to blocking wait until previous DMA transfer complete
|
||||
while ( _dcd.dma_pending ) { }
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
_dcd.dma_running = true;
|
||||
_dcd.dma_pending++;
|
||||
|
||||
(*reg_startep) = 1;
|
||||
__ISB(); __DSB();
|
||||
|
|
@ -114,8 +149,8 @@ static void edpt_dma_start(volatile uint32_t* reg_startep)
|
|||
// DMA is complete
|
||||
static void edpt_dma_end(void)
|
||||
{
|
||||
TU_ASSERT(_dcd.dma_running, );
|
||||
_dcd.dma_running = false;
|
||||
TU_ASSERT(_dcd.dma_pending, );
|
||||
_dcd.dma_pending = 0;
|
||||
}
|
||||
|
||||
// helper getting td
|
||||
|
|
@ -289,9 +324,11 @@ bool dcd_edpt_xfer (uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t
|
|||
|
||||
if ( control_status )
|
||||
{
|
||||
// Status Phase also require Easy DMA has to be free as well !!!!
|
||||
// Status Phase also requires Easy DMA has to be available as well !!!!
|
||||
// However TASKS_EP0STATUS doesn't trigger any DMA transfer and got ENDED event subsequently
|
||||
// Therefore dma_running state will be corrected right away
|
||||
edpt_dma_start(&NRF_USBD->TASKS_EP0STATUS);
|
||||
edpt_dma_end();
|
||||
if (_dcd.dma_pending) _dcd.dma_pending--; // correct the dma_running++ in dma start
|
||||
|
||||
// The nRF doesn't interrupt on status transmit so we queue up a success response.
|
||||
dcd_event_xfer_complete(0, ep_addr, 0, XFER_RESULT_SUCCESS, false);
|
||||
|
|
@ -564,9 +601,26 @@ void dcd_int_handler(uint8_t rhport)
|
|||
// HFCLK helper
|
||||
//--------------------------------------------------------------------+
|
||||
#ifdef SOFTDEVICE_PRESENT
|
||||
// check if SD is present and enabled
|
||||
static bool is_sd_enabled(void)
|
||||
|
||||
// For enable/disable hfclk with SoftDevice
|
||||
#include "nrf_mbr.h"
|
||||
#include "nrf_sdm.h"
|
||||
#include "nrf_soc.h"
|
||||
|
||||
#ifndef SD_MAGIC_NUMBER
|
||||
#define SD_MAGIC_NUMBER 0x51B1E5DB
|
||||
#endif
|
||||
|
||||
static inline bool is_sd_existed(void)
|
||||
{
|
||||
return *((uint32_t*)(SOFTDEVICE_INFO_STRUCT_ADDRESS+4)) == SD_MAGIC_NUMBER;
|
||||
}
|
||||
|
||||
// check if SD is existed and enabled
|
||||
static inline bool is_sd_enabled(void)
|
||||
{
|
||||
if ( !is_sd_existed() ) return false;
|
||||
|
||||
uint8_t sd_en = false;
|
||||
(void) sd_softdevice_is_enabled(&sd_en);
|
||||
return sd_en;
|
||||
|
|
|
|||
|
|
@ -182,7 +182,10 @@ static void dcd_userEP_in_xfer(struct xfer_ctl_t *xfer, USBD_EP_T *ep)
|
|||
/* provided buffers are thankfully 32-bit aligned, allowing most data to be transfered as 32-bit */
|
||||
while (countdown > 3)
|
||||
{
|
||||
ep->EPDAT = *(uint32_t *)xfer->data_ptr;
|
||||
uint32_t u32;
|
||||
memcpy(&u32, xfer->data_ptr, 4);
|
||||
|
||||
ep->EPDAT = u32;
|
||||
xfer->data_ptr += 4; countdown -= 4;
|
||||
}
|
||||
while (countdown--)
|
||||
|
|
|
|||
|
|
@ -273,7 +273,8 @@ typedef struct {
|
|||
dcd_qtd_t qtd[QHD_MAX] TU_ATTR_ALIGNED(32); // for portability, TinyUSB only queue 1 TD for each Qhd
|
||||
}dcd_data_t;
|
||||
|
||||
static dcd_data_t _dcd_data CFG_TUSB_MEM_SECTION TU_ATTR_ALIGNED(2048);
|
||||
CFG_TUSB_MEM_SECTION TU_ATTR_ALIGNED(2048)
|
||||
static dcd_data_t _dcd_data;
|
||||
|
||||
//--------------------------------------------------------------------+
|
||||
// CONTROLLER API
|
||||
|
|
@ -478,7 +479,8 @@ bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t t
|
|||
|
||||
// Force the CPU to flush the buffer. We increase the size by 32 because the call aligns the
|
||||
// address to 32-byte boundaries.
|
||||
CleanInvalidateDCache_by_Addr((uint32_t*) buffer, total_bytes + 31);
|
||||
// void* cast to suppress cast-align warning, buffer must be
|
||||
CleanInvalidateDCache_by_Addr((uint32_t*) tu_align((uint32_t) buffer, 4), total_bytes + 31);
|
||||
|
||||
//------------- Prepare qtd -------------//
|
||||
qtd_init(p_qtd, buffer, total_bytes);
|
||||
|
|
|
|||
|
|
@ -195,7 +195,7 @@ void dcd_init (uint8_t rhport)
|
|||
|
||||
// Programming model begins in the last section of the chapter on the USB
|
||||
// peripheral in each Reference Manual.
|
||||
USB_OTG_FS->GAHBCFG |= USB_OTG_GAHBCFG_TXFELVL | USB_OTG_GAHBCFG_GINT;
|
||||
USB_OTG_FS->GAHBCFG |= USB_OTG_GAHBCFG_GINT;
|
||||
|
||||
// No HNP/SRP (no OTG support), program timeout later, turnaround
|
||||
// programmed for 32+ MHz.
|
||||
|
|
@ -374,7 +374,6 @@ bool dcd_edpt_xfer (uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t
|
|||
((total_bytes & USB_OTG_DIEPTSIZ_XFRSIZ_Msk) << USB_OTG_DIEPTSIZ_XFRSIZ_Pos);
|
||||
|
||||
in_ep[epnum].DIEPCTL |= USB_OTG_DIEPCTL_EPENA | USB_OTG_DIEPCTL_CNAK;
|
||||
|
||||
// Enable fifo empty interrupt only if there are something to put in the fifo.
|
||||
if(total_bytes != 0) {
|
||||
dev->DIEPEMPMSK |= (1 << epnum);
|
||||
|
|
@ -539,45 +538,29 @@ static void receive_packet(xfer_ctl_t * xfer, /* USB_OTG_OUTEndpointTypeDef * ou
|
|||
xfer->short_packet = (xfer_size < xfer->max_size);
|
||||
}
|
||||
|
||||
// Write a data packet to EPIN FIFO
|
||||
static void transmit_packet(xfer_ctl_t * xfer, USB_OTG_INEndpointTypeDef * in_ep, uint8_t fifo_num) {
|
||||
// Write a single data packet to EPIN FIFO
|
||||
static void write_fifo_packet(uint8_t fifo_num, uint8_t * src, uint16_t len){
|
||||
usb_fifo_t tx_fifo = FIFO_BASE(fifo_num);
|
||||
|
||||
uint16_t remaining = (in_ep->DIEPTSIZ & USB_OTG_DIEPTSIZ_XFRSIZ_Msk) >> USB_OTG_DIEPTSIZ_XFRSIZ_Pos;
|
||||
xfer->queued_len = xfer->total_len - remaining;
|
||||
|
||||
uint16_t to_xfer_size = (remaining > xfer->max_size) ? xfer->max_size : remaining;
|
||||
uint8_t to_xfer_rem = to_xfer_size % 4;
|
||||
uint16_t to_xfer_size_aligned = to_xfer_size - to_xfer_rem;
|
||||
|
||||
// Buffer might not be aligned to 32b, so we need to force alignment
|
||||
// by copying to a temp var.
|
||||
uint8_t * base = (xfer->buffer + xfer->queued_len);
|
||||
|
||||
// This for loop always runs at least once- skip if less than 4 bytes
|
||||
// to send off.
|
||||
if(to_xfer_size >= 4) {
|
||||
for(uint16_t i = 0; i < to_xfer_size_aligned; i += 4) {
|
||||
uint32_t tmp = base[i] | (base[i + 1] << 8) | \
|
||||
(base[i + 2] << 16) | (base[i + 3] << 24);
|
||||
(* tx_fifo) = tmp;
|
||||
}
|
||||
// Pushing full available 32 bit words to fifo
|
||||
uint16_t full_words = len >> 2;
|
||||
for(uint16_t i = 0; i < full_words; i++){
|
||||
*tx_fifo = (src[3] << 24) | (src[2] << 16) | (src[1] << 8) | src[0];
|
||||
src += 4;
|
||||
}
|
||||
|
||||
// Do not read beyond end of buffer if not divisible by 4.
|
||||
if(to_xfer_rem != 0) {
|
||||
uint32_t tmp = 0;
|
||||
uint8_t * last_32b_bound = base + to_xfer_size_aligned;
|
||||
|
||||
tmp |= last_32b_bound[0];
|
||||
if(to_xfer_rem > 1) {
|
||||
tmp |= (last_32b_bound[1] << 8);
|
||||
// Write the remaining 1-3 bytes into fifo
|
||||
uint8_t bytes_rem = len & 0x03;
|
||||
if(bytes_rem){
|
||||
uint32_t tmp_word = 0;
|
||||
tmp_word |= src[0];
|
||||
if(bytes_rem > 1){
|
||||
tmp_word |= src[1] << 8;
|
||||
}
|
||||
if(to_xfer_rem > 2) {
|
||||
tmp |= (last_32b_bound[2] << 16);
|
||||
if(bytes_rem > 2){
|
||||
tmp_word |= src[2] << 16;
|
||||
}
|
||||
|
||||
(* tx_fifo) = tmp;
|
||||
*tx_fifo = tmp_word;
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -669,6 +652,7 @@ static void handle_epin_ints(USB_OTG_DeviceTypeDef * dev, USB_OTG_INEndpointType
|
|||
|
||||
if ( dev->DAINT & (1 << (USB_OTG_DAINT_IEPINT_Pos + n)) )
|
||||
{
|
||||
|
||||
// IN XFER complete (entire xfer).
|
||||
if ( in_ep[n].DIEPINT & USB_OTG_DIEPINT_XFRC )
|
||||
{
|
||||
|
|
@ -677,17 +661,36 @@ static void handle_epin_ints(USB_OTG_DeviceTypeDef * dev, USB_OTG_INEndpointType
|
|||
}
|
||||
|
||||
// XFER FIFO empty
|
||||
if ( in_ep[n].DIEPINT & USB_OTG_DIEPINT_TXFE )
|
||||
if ( (in_ep[n].DIEPINT & USB_OTG_DIEPINT_TXFE) && (dev->DIEPEMPMSK & (1 << n)) )
|
||||
{
|
||||
// DIEPINT's TXFE bit is read-only, software cannot clear it.
|
||||
// It will only be cleared by hardware when written bytes is more than
|
||||
// - 64 bytes or
|
||||
// - Half of TX FIFO size (configured by DIEPTXF)
|
||||
|
||||
transmit_packet(xfer, &in_ep[n], n);
|
||||
uint16_t remaining_packets = (in_ep[n].DIEPTSIZ & USB_OTG_DIEPTSIZ_PKTCNT_Msk) >> USB_OTG_DIEPTSIZ_PKTCNT_Pos;
|
||||
|
||||
// Process every single packet (only whole packets can be written to fifo)
|
||||
for(uint16_t i = 0; i < remaining_packets; i++){
|
||||
uint16_t remaining_bytes = (in_ep[n].DIEPTSIZ & USB_OTG_DIEPTSIZ_XFRSIZ_Msk) >> USB_OTG_DIEPTSIZ_XFRSIZ_Pos;
|
||||
// Packet can not be larger than ep max size
|
||||
uint16_t packet_size = tu_min16(remaining_bytes, xfer->max_size);
|
||||
|
||||
// It's only possible to write full packets into FIFO. Therefore DTXFSTS register of current
|
||||
// EP has to be checked if the buffer can take another WHOLE packet
|
||||
if(packet_size > ((in_ep[n].DTXFSTS & USB_OTG_DTXFSTS_INEPTFSAV_Msk) << 2)){
|
||||
break;
|
||||
}
|
||||
|
||||
// TODO: queued_len can be removed later
|
||||
xfer->queued_len = xfer->total_len - remaining_bytes;
|
||||
|
||||
// Push packet to Tx-FIFO
|
||||
write_fifo_packet(n, (xfer->buffer + xfer->queued_len), packet_size);
|
||||
}
|
||||
|
||||
// Turn off TXFE if all bytes are written.
|
||||
if (xfer->queued_len == xfer->total_len)
|
||||
if (((in_ep[n].DIEPTSIZ & USB_OTG_DIEPTSIZ_XFRSIZ_Msk) >> USB_OTG_DIEPTSIZ_XFRSIZ_Pos) == 0)
|
||||
{
|
||||
dev->DIEPEMPMSK &= ~(1 << n);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -54,6 +54,90 @@ void test_normal(void)
|
|||
}
|
||||
}
|
||||
|
||||
void test_item_size(void)
|
||||
{
|
||||
TU_FIFO_DEF(ff4, FIFO_SIZE, uint32_t, false);
|
||||
tu_fifo_clear(&ff4);
|
||||
|
||||
uint32_t data[20];
|
||||
for(uint32_t i=0; i<sizeof(data)/4; i++) data[i] = i;
|
||||
|
||||
tu_fifo_write_n(&ff4, data, 10);
|
||||
|
||||
uint32_t rd[10];
|
||||
uint16_t rd_count;
|
||||
|
||||
// read 0 -> 4
|
||||
rd_count = tu_fifo_read_n(&ff4, rd, 5);
|
||||
TEST_ASSERT_EQUAL( 5, rd_count );
|
||||
TEST_ASSERT_EQUAL_UINT32_ARRAY( data, rd, rd_count ); // 0 -> 4
|
||||
|
||||
tu_fifo_write_n(&ff4, data+10, 5);
|
||||
|
||||
// read 5 -> 14
|
||||
rd_count = tu_fifo_read_n(&ff4, rd, 10);
|
||||
TEST_ASSERT_EQUAL( 10, rd_count );
|
||||
TEST_ASSERT_EQUAL_UINT32_ARRAY( data+5, rd, rd_count ); // 5 -> 14
|
||||
}
|
||||
|
||||
void test_read_n(void)
|
||||
{
|
||||
// prepare data
|
||||
uint8_t data[20];
|
||||
for(int i=0; i<sizeof(data); i++) data[i] = i;
|
||||
|
||||
for(uint8_t i=0; i < FIFO_SIZE; i++) tu_fifo_write(&ff, data+i);
|
||||
|
||||
uint8_t rd[10];
|
||||
uint16_t rd_count;
|
||||
|
||||
// case 1: Read index + count < depth
|
||||
// read 0 -> 4
|
||||
rd_count = tu_fifo_read_n(&ff, rd, 5);
|
||||
TEST_ASSERT_EQUAL( 5, rd_count );
|
||||
TEST_ASSERT_EQUAL_MEMORY( data, rd, rd_count ); // 0 -> 4
|
||||
|
||||
// case 2: Read index + count > depth
|
||||
// write 10, 11, 12
|
||||
tu_fifo_write(&ff, data+10);
|
||||
tu_fifo_write(&ff, data+11);
|
||||
tu_fifo_write(&ff, data+12);
|
||||
|
||||
rd_count = tu_fifo_read_n(&ff, rd, 7);
|
||||
TEST_ASSERT_EQUAL( 7, rd_count );
|
||||
|
||||
TEST_ASSERT_EQUAL_MEMORY( data+5, rd, rd_count ); // 5 -> 11
|
||||
|
||||
// Should only read until empty
|
||||
TEST_ASSERT_EQUAL( 1, tu_fifo_read_n(&ff, rd, 100) );
|
||||
}
|
||||
|
||||
void test_write_n(void)
|
||||
{
|
||||
// prepare data
|
||||
uint8_t data[20];
|
||||
for(int i=0; i<sizeof(data); i++) data[i] = i;
|
||||
|
||||
// case 1: wr + count < depth
|
||||
tu_fifo_write_n(&ff, data, 8); // wr = 8, count = 8
|
||||
|
||||
uint8_t rd[10];
|
||||
uint16_t rd_count;
|
||||
|
||||
rd_count = tu_fifo_read_n(&ff, rd, 5); // wr = 8, count = 3
|
||||
TEST_ASSERT_EQUAL( 5, rd_count );
|
||||
TEST_ASSERT_EQUAL_MEMORY( data, rd, rd_count ); // 0 -> 4
|
||||
|
||||
// case 2: wr + count > depth
|
||||
tu_fifo_write_n(&ff, data+8, 6); // wr = 3, count = 9
|
||||
|
||||
for(rd_count=0; rd_count<7; rd_count++) tu_fifo_read(&ff, rd+rd_count); // wr = 3, count = 2
|
||||
|
||||
TEST_ASSERT_EQUAL_MEMORY( data+5, rd, rd_count); // 5 -> 11
|
||||
|
||||
TEST_ASSERT_EQUAL(2, tu_fifo_count(&ff));
|
||||
}
|
||||
|
||||
void test_peek(void)
|
||||
{
|
||||
uint8_t temp;
|
||||
|
|
|
|||
Loading…
Reference in New Issue