clean up dcd lpc11u
This commit is contained in:
hathach
parent
57f7c18d77
commit
f28a15a886
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@ -40,9 +40,6 @@
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#if TUSB_OPT_DEVICE_ENABLED && (CFG_TUSB_MCU == OPT_MCU_LPC11UXX || CFG_TUSB_MCU == OPT_MCU_LPC13XX)
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// NOTE: despite of being very the same to lpc13uxx controller, lpc11u's controller cannot queue transfer more than
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// endpoint's max packet size and need some soft DMA helper
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#include "chip.h"
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#include "device/dcd.h"
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#include "dcd_lpc11_13_15.h"
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@ -57,6 +54,8 @@
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// only SRAM1 & USB RAM can be used for transfer
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#define SRAM_REGION 0x20000000
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// NOTE: despite of being very the same to lpc13uxx controller, lpc11u's controller cannot queue transfer more than
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// endpoint's max packet size and need some soft DMA helper
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enum {
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DCD_11U_13U_MAX_BYTE_PER_TD = (CFG_TUSB_MCU == OPT_MCU_LPC11UXX ? 64 : 1023)
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};
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@ -95,35 +94,22 @@ typedef struct ATTR_PACKED
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TU_VERIFY_STATIC( sizeof(ep_cmd_sts_t) == 4, "size is not correct" );
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// NOTE data will be transferred as soon as dcd get request by dcd_pipe(_queue)_xfer using double buffering.
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// If there is another dcd_edpt_xfer request, the new request will be saved and executed when the first is done.
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// next_td stored the 2nd request information
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// current_td is used to keep track of number of remaining & xferred bytes of the current request.
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// queued_bytes_in_buff keep track of number of bytes queued to each buffer (in case of short packet)
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typedef struct {
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ep_cmd_sts_t qhd[EP_COUNT][2]; ///< 256 byte aligned, 2 for double buffer
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uint16_t expected_len[EP_COUNT];
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// start at 80, the size should not exceed 48 (for setup_request align at 128)
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struct {
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uint16_t buff_addr_offset;
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uint16_t total_bytes;
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}next_td[EP_COUNT];
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uint32_t current_ioc; ///< interrupt on complete mask for current TD
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uint32_t next_ioc; ///< interrupt on complete mask for next TD
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// must start from 128
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ATTR_ALIGNED(64) uint8_t setup_packet[8];
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typedef struct
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{
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// 256 byte aligned, 2 for double buffer (not used)
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// Each cmd_sts can only transfer up to 1023 bytes each pass
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//
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ep_cmd_sts_t ep[EP_COUNT][2];
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struct {
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uint16_t remaining_bytes; ///< expected bytes of the queued transfer
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uint16_t xferred_total; ///< xferred bytes of the current transfer
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uint16_t xferred_bytes; ///< xferred bytes of the current transfer
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uint16_t queued_bytes_in_buff[2]; ///< expected bytes that are queued for each buffer
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uint16_t nbytes; // Set nbytes, to determine transferred bytes each pass
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}current_td[EP_COUNT];
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ATTR_ALIGNED(64) uint8_t setup_packet[8];
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}dcd_data_t;
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//--------------------------------------------------------------------+
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@ -140,9 +126,10 @@ static inline uint16_t addr_offset(void const * buffer)
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return ( (addr >> 6) & 0xFFFFUL ) ;
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}
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static void queue_xfer_to_buffer(uint8_t ep_id, uint8_t buff_idx, uint16_t buff_addr_offset, uint16_t total_bytes);
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static void pipe_queue_xfer(uint8_t ep_id, uint16_t buff_addr_offset, uint16_t total_bytes);
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static void queue_xfer_in_next_td(uint8_t ep_id);
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static inline uint8_t ep_addr2id(uint8_t endpoint_addr)
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{
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return 2*(endpoint_addr & 0x0F) + ((endpoint_addr & TUSB_DIR_IN_MASK) ? 1 : 0);
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}
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//--------------------------------------------------------------------+
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// CONTROLLER API
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@ -191,7 +178,7 @@ bool dcd_init(uint8_t rhport)
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// Setup PLL clock, and power
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Chip_USB_Init();
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LPC_USB->EPLISTSTART = (uint32_t) _dcd.qhd;
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LPC_USB->EPLISTSTART = (uint32_t) _dcd.ep;
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LPC_USB->DATABUFSTART = SRAM_REGION;
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LPC_USB->INTSTAT = LPC_USB->INTSTAT; // clear all pending interrupt
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@ -205,60 +192,38 @@ bool dcd_init(uint8_t rhport)
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}
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//--------------------------------------------------------------------+
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// PIPE HELPER
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//--------------------------------------------------------------------+
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static inline uint8_t edpt_addr2phy(uint8_t endpoint_addr)
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{
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return 2*(endpoint_addr & 0x0F) + ((endpoint_addr & TUSB_DIR_IN_MASK) ? 1 : 0);
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}
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#if 0
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static inline uint8_t edpt_phy2log(uint8_t physical_endpoint) ATTR_CONST ATTR_ALWAYS_INLINE;
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static inline uint8_t edpt_phy2log(uint8_t physical_endpoint)
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{
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return physical_endpoint/2;
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}
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#endif
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//--------------------------------------------------------------------+
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// BULK/INTERRUPT/ISOCHRONOUS PIPE API
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// DCD Endpoint Port
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//--------------------------------------------------------------------+
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void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr)
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{
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if ( edpt_number(ep_addr) == 0 )
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{
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// TODO cannot able to STALL Control OUT endpoint !!!!! FIXME try some walk-around
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_dcd.qhd[0][0].stall = _dcd.qhd[1][0].stall = 1;
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_dcd.ep[0][0].stall = _dcd.ep[1][0].stall = 1;
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}
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else
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{
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uint8_t const ep_id = edpt_addr2phy(edpt_addr);
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_dcd.qhd[ep_id][0].stall = _dcd.qhd[ep_id][1].stall = 1;
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uint8_t const ep_id = ep_addr2id(ep_addr);
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_dcd.ep[ep_id][0].stall = _dcd.ep[ep_id][1].stall = 1;
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}
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}
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bool dcd_edpt_stalled(uint8_t rhport, uint8_t ep_addr)
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{
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uint8_t const ep_id = edpt_addr2phy(edpt_addr);
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return _dcd.qhd[ep_id][0].stall || _dcd.qhd[ep_id][1].stall;
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uint8_t const ep_id = ep_addr2id(ep_addr);
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return _dcd.ep[ep_id][0].stall || _dcd.ep[ep_id][1].stall;
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}
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void dcd_edpt_clear_stall(uint8_t rhport, uint8_t edpt_addr)
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{
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uint8_t const ep_id = edpt_addr2phy(edpt_addr);
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uint8_t const ep_id = ep_addr2id(edpt_addr);
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// uint8_t active_buffer = BIT_TEST_(LPC_USB->EPINUSE, ep_id) ? 1 : 0;
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_dcd.qhd[ep_id][0].stall = _dcd.qhd[ep_id][1].stall = 0;
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_dcd.ep[ep_id][0].stall = _dcd.ep[ep_id][1].stall = 0;
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// since the next transfer always take place on buffer0 --> clear buffer0 toggle
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_dcd.qhd[ep_id][0].toggle_reset = 1;
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_dcd.qhd[ep_id][0].toggle_mode = 0;
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//------------- clear stall must carry on any previously queued transfer -------------//
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if ( _dcd.next_td[ep_id].total_bytes != 0 )
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{
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queue_xfer_in_next_td(ep_id);
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}
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_dcd.ep[ep_id][0].toggle_reset = 1;
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_dcd.ep[ep_id][0].toggle_mode = 0;
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}
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bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc)
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@ -269,113 +234,49 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc)
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if (p_endpoint_desc->bmAttributes.xfer == TUSB_XFER_ISOCHRONOUS) return false;
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//------------- Prepare Queue Head -------------//
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uint8_t ep_id = edpt_addr2phy(p_endpoint_desc->bEndpointAddress);
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uint8_t ep_id = ep_addr2id(p_endpoint_desc->bEndpointAddress);
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// endpoint must not previously opened, normally this means running out of endpoints
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TU_ASSERT( _dcd.qhd[ep_id][0].disable && _dcd.qhd[ep_id][1].disable );
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// Check if endpoint is available
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TU_ASSERT( _dcd.ep[ep_id][0].disable && _dcd.ep[ep_id][1].disable );
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tu_memclr(_dcd.qhd[ep_id], 2*sizeof(ep_cmd_sts_t));
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_dcd.qhd[ep_id][0].is_iso = _dcd.qhd[ep_id][1].is_iso = (p_endpoint_desc->bmAttributes.xfer == TUSB_XFER_ISOCHRONOUS);
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_dcd.qhd[ep_id][0].disable = _dcd.qhd[ep_id][1].disable = 0;
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tu_memclr(_dcd.ep[ep_id], 2*sizeof(ep_cmd_sts_t));
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_dcd.ep[ep_id][0].is_iso = _dcd.ep[ep_id][1].is_iso = (p_endpoint_desc->bmAttributes.xfer == TUSB_XFER_ISOCHRONOUS);
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LPC_USB->EPBUFCFG |= BIT_(ep_id);
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LPC_USB->INTEN |= BIT_(ep_id);
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// Enable EP interrupt
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LPC_USB->INTEN |= BIT_(ep_id);
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return true;
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}
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bool dcd_edpt_busy(uint8_t rhport, uint8_t ep_addr)
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{
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uint8_t const ep_id = edpt_addr2phy(ep_addr);
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return _dcd.qhd[ep_id][0].active || _dcd.qhd[ep_id][1].active;
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uint8_t const ep_id = ep_addr2id(ep_addr);
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return _dcd.ep[ep_id][0].active || _dcd.ep[ep_id][1].active;
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}
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static void queue_xfer_to_buffer(uint8_t ep_id, uint8_t buff_idx, uint16_t buff_addr_offset, uint16_t total_bytes)
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static void prepare_ep_xfer(uint8_t ep_id, uint16_t buff_addr_offset, uint16_t total_bytes)
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{
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uint16_t const queued_bytes = tu_min16(total_bytes, DCD_11U_13U_MAX_BYTE_PER_TD);
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_dcd.current_td[ep_id].queued_bytes_in_buff[buff_idx] = queued_bytes;
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_dcd.current_td[ep_id].remaining_bytes -= queued_bytes;
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_dcd.current_td[ep_id].nbytes = queued_bytes;
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_dcd.current_td[ep_id].remaining_bytes -= queued_bytes;
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_dcd.expected_len[ep_id] = total_bytes;
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_dcd.ep[ep_id][0].buffer_offset = buff_addr_offset;
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_dcd.ep[ep_id][0].nbytes = queued_bytes;
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_dcd.qhd[ep_id][buff_idx].buffer_offset = buff_addr_offset;
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_dcd.qhd[ep_id][buff_idx].nbytes = queued_bytes;
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_dcd.qhd[ep_id][buff_idx].active = 1;
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}
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static void pipe_queue_xfer(uint8_t ep_id, uint16_t buff_addr_offset, uint16_t total_bytes)
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{
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_dcd.current_td[ep_id].remaining_bytes = total_bytes;
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_dcd.current_td[ep_id].xferred_total = 0;
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_dcd.current_td[ep_id].queued_bytes_in_buff[0] = 0;
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_dcd.current_td[ep_id].queued_bytes_in_buff[1] = 0;
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LPC_USB->EPINUSE = BIT_CLR_(LPC_USB->EPINUSE , ep_id); // force HW to use buffer0
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// need to queue buffer1 first, as activate buffer0 can causes controller does transferring immediately
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// while buffer1 is not ready yet
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if ( total_bytes > DCD_11U_13U_MAX_BYTE_PER_TD)
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{
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queue_xfer_to_buffer(ep_id, 1, buff_addr_offset+1, total_bytes - DCD_11U_13U_MAX_BYTE_PER_TD);
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}
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queue_xfer_to_buffer(ep_id, 0, buff_addr_offset, total_bytes);
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}
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static void queue_xfer_in_next_td(uint8_t ep_id)
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{
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_dcd.current_ioc |= ( _dcd.next_ioc & BIT_(ep_id) ); // copy next IOC to current IOC
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pipe_queue_xfer(ep_id, _dcd.next_td[ep_id].buff_addr_offset, _dcd.next_td[ep_id].total_bytes);
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_dcd.next_td[ep_id].total_bytes = 0; // clear this field as it is used to indicate whehther next TD available
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}
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tusb_error_t dcd_edpt_queue_xfer(uint8_t ep_id , uint8_t * buffer, uint16_t total_bytes)
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{
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_dcd.current_ioc = BIT_CLR_(_dcd.current_ioc, ep_id);
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pipe_queue_xfer(ep_id, addr_offset(buffer), total_bytes);
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return TUSB_ERROR_NONE;
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}
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bool dcd_control_xfer(uint8_t rhport, uint8_t ep_id, uint8_t * p_buffer, uint16_t length)
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{
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(void) rhport;
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_dcd.current_ioc = BIT_SET_(_dcd.current_ioc, ep_id);
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_dcd.current_td[ep_id].remaining_bytes = length;
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_dcd.current_td[ep_id].xferred_total = 0;
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queue_xfer_to_buffer(ep_id, 0, addr_offset(p_buffer), length);
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return true;
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_dcd.ep[ep_id][0].active = 1;
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}
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bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t* buffer, uint16_t total_bytes)
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{
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uint8_t const ep_id = edpt_addr2phy(ep_addr);
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uint8_t const ep_id = ep_addr2id(ep_addr);
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uint16_t buf_offset = addr_offset(buffer);
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if ( edpt_number(ep_addr) == 0 )
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{
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return dcd_control_xfer(rhport, ep_id, buffer, (uint8_t) total_bytes);
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}
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_dcd.current_td[ep_id].remaining_bytes = total_bytes;
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_dcd.current_td[ep_id].xferred_bytes = 0;
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_dcd.current_td[ep_id].nbytes = 0;
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// if( dcd_edpt_busy(ep_addr) || dcd_edpt_stalled(ep_addr) )
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// { // save this transfer data to next td if pipe is busy or already been stalled
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// dcd_data.next_td[ep_id].buff_addr_offset = addr_offset(buffer);
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// dcd_data.next_td[ep_id].total_bytes = total_bytes;
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//
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// dcd_data.next_ioc = BIT_SET_(dcd_data.next_ioc, ep_id);
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// }else
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{
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_dcd.current_ioc = BIT_SET_(_dcd.current_ioc, ep_id);
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pipe_queue_xfer(ep_id, addr_offset(buffer), total_bytes);
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}
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prepare_ep_xfer(ep_id, buf_offset, total_bytes);
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return true;
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}
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@ -390,13 +291,13 @@ static void bus_reset(void)
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// disable all non-control endpoints on bus reset
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for(uint8_t ep_id = 2; ep_id < EP_COUNT; ep_id++)
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{
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_dcd.qhd[ep_id][0].disable = _dcd.qhd[ep_id][1].disable = 1;
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_dcd.ep[ep_id][0].disable = _dcd.ep[ep_id][1].disable = 1;
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}
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_dcd.qhd[0][1].buffer_offset = addr_offset(_dcd.setup_packet);
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_dcd.ep[0][1].buffer_offset = addr_offset(_dcd.setup_packet);
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LPC_USB->EPINUSE = 0;
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LPC_USB->EPBUFCFG = 0; // all start with single buffer
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LPC_USB->EPBUFCFG = 0;
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LPC_USB->EPSKIP = 0xFFFFFFFF;
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LPC_USB->INTSTAT = LPC_USB->INTSTAT; // clear all pending interrupt
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@ -404,75 +305,44 @@ static void bus_reset(void)
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LPC_USB->INTEN = INT_DEVICE_STATUS_MASK | BIT_(0) | BIT_(1); // enable device status & control endpoints
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}
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static void endpoint_non_control_isr(uint32_t int_status)
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static void process_xfer_isr(uint32_t int_status)
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{
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for(uint8_t ep_id = 2; ep_id < EP_COUNT; ep_id++ )
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for(uint8_t ep_id = 0; ep_id < EP_COUNT; ep_id++ )
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{
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if ( BIT_TEST_(int_status, ep_id) )
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{
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ep_cmd_sts_t * const arr_qhd = _dcd.qhd[ep_id];
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ep_cmd_sts_t * ep_cs = &_dcd.ep[ep_id][0];
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// when double buffering, the complete buffer is opposed to the current active buffer in EPINUSE
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uint8_t const buff_idx = LPC_USB->EPINUSE & BIT_(ep_id) ? 0 : 1;
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uint16_t const xferred_bytes = _dcd.current_td[ep_id].queued_bytes_in_buff[buff_idx] - arr_qhd[buff_idx].nbytes;
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_dcd.current_td[ep_id].xferred_bytes += _dcd.current_td[ep_id].nbytes - ep_cs->nbytes;
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_dcd.current_td[ep_id].xferred_total += xferred_bytes;
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// there are still data to transfer.
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if ( (arr_qhd[buff_idx].nbytes == 0) && (_dcd.current_td[ep_id].remaining_bytes > 0) )
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if ( (ep_cs->nbytes == 0) && (_dcd.current_td[ep_id].remaining_bytes > 0) )
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{
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// NOTE although buff_addr_offset has been increased when xfer is completed
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// but we still need to increase it one more as we are using double buffering.
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queue_xfer_to_buffer(ep_id, buff_idx, arr_qhd[buff_idx].buffer_offset+1, _dcd.current_td[ep_id].remaining_bytes);
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// There is more data to transfer
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// buff_offset has been already increased by hw to correct value for next transfer
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prepare_ep_xfer(ep_id, ep_cs->buffer_offset, _dcd.current_td[ep_id].remaining_bytes);
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}
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else if ( (arr_qhd[buff_idx].nbytes > 0) || !arr_qhd[1-buff_idx].active )
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else
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{
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// short packet or (no more byte and both buffers are finished)
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// current TD (request) is completed
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LPC_USB->EPSKIP = BIT_SET_(LPC_USB->EPSKIP, ep_id); // skip other endpoint in case of short-package
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_dcd.current_td[ep_id].remaining_bytes = 0;
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if ( BIT_TEST_(_dcd.current_ioc, ep_id) )
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{
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_dcd.current_ioc = BIT_CLR_(_dcd.current_ioc, ep_id);
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uint8_t const ep_addr = (ep_id / 2) | ((ep_id & 0x01) ? TUSB_DIR_IN_MASK : 0);
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uint8_t const ep_addr = (ep_id / 2) | ((ep_id & 0x01) ? TUSB_DIR_IN_MASK : 0);
|
||||
|
||||
// TODO no way determine if the transfer is failed or not
|
||||
dcd_event_xfer_complete(0, ep_addr, _dcd.current_td[ep_id].xferred_total, XFER_RESULT_SUCCESS, true);
|
||||
}
|
||||
|
||||
//------------- Next TD is available -------------//
|
||||
if ( _dcd.next_td[ep_id].total_bytes != 0 )
|
||||
{
|
||||
queue_xfer_in_next_td(ep_id);
|
||||
}
|
||||
}else
|
||||
{
|
||||
// transfer complete, there is no more remaining bytes, but this buffer is not the last transaction (the other is)
|
||||
// TODO no way determine if the transfer is failed or not
|
||||
dcd_event_xfer_complete(0, ep_addr, _dcd.current_td[ep_id].xferred_bytes, XFER_RESULT_SUCCESS, true);
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
static void endpoint_control_isr(uint32_t int_status)
|
||||
{
|
||||
uint8_t const ep_id = ( int_status & BIT_(0) ) ? 0 : 1;
|
||||
|
||||
dcd_event_xfer_complete(0, ep_id ? TUSB_DIR_IN_MASK : 0, _dcd.expected_len[ep_id] - _dcd.qhd[ep_id][0].nbytes, XFER_RESULT_SUCCESS, true);
|
||||
}
|
||||
|
||||
void USB_IRQHandler(void)
|
||||
{
|
||||
uint32_t const int_enable = LPC_USB->INTEN;
|
||||
uint32_t const int_status = LPC_USB->INTSTAT & int_enable;
|
||||
uint32_t const dev_cmd_stat = LPC_USB->DEVCMDSTAT;
|
||||
|
||||
uint32_t int_status = LPC_USB->INTSTAT & LPC_USB->INTEN;
|
||||
LPC_USB->INTSTAT = int_status; // Acknowledge handled interrupt
|
||||
|
||||
if (int_status == 0) return;
|
||||
|
||||
uint32_t const dev_cmd_stat = LPC_USB->DEVCMDSTAT;
|
||||
|
||||
//------------- Device Status -------------//
|
||||
if ( int_status & INT_DEVICE_STATUS_MASK )
|
||||
{
|
||||
|
|
@ -512,30 +382,26 @@ void USB_IRQHandler(void)
|
|||
// }
|
||||
}
|
||||
|
||||
//------------- Setup Received -------------//
|
||||
// Setup Receive
|
||||
if ( BIT_TEST_(int_status, 0) && (dev_cmd_stat & CMDSTAT_SETUP_RECEIVED_MASK) )
|
||||
{
|
||||
// received control request from host
|
||||
// copy setup request & acknowledge so that the next setup can be received by hw
|
||||
dcd_event_setup_received(0, _dcd.setup_packet, true);
|
||||
|
||||
// NXP control flowchart clear Active & Stall on both Control IN/OUT endpoints
|
||||
_dcd.qhd[0][0].stall = _dcd.qhd[1][0].stall = 0;
|
||||
// Follow UM flowchart to clear Active & Stall on both Control IN/OUT endpoints
|
||||
_dcd.ep[0][0].active = _dcd.ep[1][0].active = 0;
|
||||
_dcd.ep[0][0].stall = _dcd.ep[1][0].stall = 0;
|
||||
|
||||
LPC_USB->DEVCMDSTAT |= CMDSTAT_SETUP_RECEIVED_MASK;
|
||||
_dcd.qhd[0][1].buffer_offset = addr_offset(_dcd.setup_packet);
|
||||
}
|
||||
//------------- Control Endpoint -------------//
|
||||
else if ( int_status & 0x03 )
|
||||
{
|
||||
endpoint_control_isr(int_status);
|
||||
|
||||
dcd_event_setup_received(0, _dcd.setup_packet, true);
|
||||
|
||||
// keep waiting for next setup
|
||||
_dcd.ep[0][1].buffer_offset = addr_offset(_dcd.setup_packet);
|
||||
|
||||
// clear bit0
|
||||
int_status = BIT_CLR_(int_status, 0);
|
||||
}
|
||||
|
||||
//------------- Non-Control Endpoints -------------//
|
||||
if( int_status & ~(0x03UL) )
|
||||
{
|
||||
endpoint_non_control_isr(int_status);
|
||||
}
|
||||
// Endpoint transfer complete interrupt
|
||||
process_xfer_isr(int_status);
|
||||
}
|
||||
|
||||
#endif
|
||||
|
|
|
|||
Loading…
Reference in New Issue