house keeping
This commit is contained in:
hathach
parent
e14864759d
commit
e6b8166a58
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@ -71,6 +71,16 @@ tusb_descriptor_endpoint_t const desc_ept_bulk_in =
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.bInterval = 0
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};
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tusb_descriptor_endpoint_t const desc_ept_bulk_out =
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{
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.bLength = sizeof(tusb_descriptor_endpoint_t),
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.bDescriptorType = TUSB_DESC_ENDPOINT,
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.bEndpointAddress = 0x01,
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.bmAttributes = { .xfer = TUSB_XFER_BULK },
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.wMaxPacketSize = 512,
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.bInterval = 0
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};
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//--------------------------------------------------------------------+
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// Setup/Teardown + helper declare
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//--------------------------------------------------------------------+
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@ -139,15 +149,6 @@ void verify_qtd(ehci_qtd_t *p_qtd, uint8_t p_data[], uint16_t length)
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void test_bulk_xfer_hs_ping_out(void)
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{
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tusb_descriptor_endpoint_t const desc_ept_bulk_out =
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{
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.bLength = sizeof(tusb_descriptor_endpoint_t),
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.bDescriptorType = TUSB_DESC_ENDPOINT,
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.bEndpointAddress = 0x01,
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.bmAttributes = { .xfer = TUSB_XFER_BULK },
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.wMaxPacketSize = 512,
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.bInterval = 0
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};
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usbh_device_info_pool[dev_addr].speed = TUSB_SPEED_HIGH;
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pipe_handle_t pipe_hdl = hcd_pipe_open(dev_addr, &desc_ept_bulk_out, TUSB_CLASS_MSC);
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@ -177,7 +178,6 @@ void test_bulk_xfer(void)
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void test_bulk_xfer_double(void)
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{
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//------------- Code Under Test -------------//
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hcd_pipe_xfer(pipe_hdl_bulk, xfer_data, sizeof(xfer_data), false);
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hcd_pipe_xfer(pipe_hdl_bulk, data2, sizeof(data2), true);
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@ -110,9 +110,6 @@ void verify_open_qhd(ehci_qhd_t *p_qhd, uint8_t endpoint_addr, uint16_t max_pack
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TEST_ASSERT_NULL(p_qhd->p_qtd_list_tail);
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}
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//--------------------------------------------------------------------+
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// PIPE OPEN
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//--------------------------------------------------------------------+
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void verify_control_open_qhd(ehci_qhd_t *p_qhd)
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{
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verify_open_qhd(p_qhd, 0, control_max_packet_size);
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@ -123,6 +120,9 @@ void verify_control_open_qhd(ehci_qhd_t *p_qhd)
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TEST_ASSERT_EQUAL(0, p_qhd->non_hs_interrupt_cmask);
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}
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//--------------------------------------------------------------------+
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// PIPE OPEN
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//--------------------------------------------------------------------+
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void test_control_open_addr0_qhd_data(void)
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{
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dev_addr = 0;
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@ -57,21 +57,12 @@ uint8_t hostid;
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uint8_t xfer_data [100];
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ehci_qhd_t *async_head;
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ehci_qhd_t *p_control_qhd;
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ehci_qtd_t *p_setup;
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ehci_qtd_t *p_data;
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ehci_qtd_t *p_status;
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tusb_descriptor_endpoint_t const desc_ept_bulk_in =
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{
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.bLength = sizeof(tusb_descriptor_endpoint_t),
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.bDescriptorType = TUSB_DESC_ENDPOINT,
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.bEndpointAddress = 0x81,
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.bmAttributes = { .xfer = TUSB_XFER_BULK },
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.wMaxPacketSize = 512,
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.bInterval = 0
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};
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//--------------------------------------------------------------------+
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// Setup/Teardown + helper declare
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//--------------------------------------------------------------------+
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@ -98,6 +89,8 @@ void setUp(void)
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async_head = get_async_head( hostid );
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p_control_qhd = &ehci_data.device[dev_addr-1].control.qhd;
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p_setup = &ehci_data.device[dev_addr-1].control.qtd[0];
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p_data = &ehci_data.device[dev_addr-1].control.qtd[1];
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p_status = &ehci_data.device[dev_addr-1].control.qtd[2];
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@ -117,6 +110,13 @@ tusb_std_request_t request_get_dev_desc =
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.wLength = 18
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};
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tusb_std_request_t request_set_dev_addr =
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{
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.bmRequestType = { .direction = TUSB_DIR_HOST_TO_DEV, .type = TUSB_REQUEST_TYPE_STANDARD, .recipient = TUSB_REQUEST_RECIPIENT_DEVICE },
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.bRequest = TUSB_REQUEST_SET_ADDRESS,
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.wValue = 3
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};
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void verify_qtd(ehci_qtd_t *p_qtd, uint8_t p_data[], uint16_t length)
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{
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TEST_ASSERT_TRUE(p_qtd->alternate.terminate); // not used, always invalid
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@ -137,6 +137,9 @@ void verify_qtd(ehci_qtd_t *p_qtd, uint8_t p_data[], uint16_t length)
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TEST_ASSERT_EQUAL_HEX(p_data, p_qtd->buffer[0]);
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}
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//--------------------------------------------------------------------+
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// Address 0
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//--------------------------------------------------------------------+
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void test_control_addr0_xfer_get_check_qhd_qtd_mapping(void)
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{
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dev_addr = 0;
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@ -160,17 +163,18 @@ void test_control_addr0_xfer_get_check_qhd_qtd_mapping(void)
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verify_qtd(p_setup, &request_get_dev_desc, 8);
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}
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//--------------------------------------------------------------------+
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// Normal Control
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//--------------------------------------------------------------------+
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void test_control_xfer_get(void)
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{
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ehci_qhd_t * const p_qhd = &ehci_data.device[dev_addr-1].control.qhd;
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hcd_pipe_control_open(dev_addr, control_max_packet_size);
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//------------- Code Under TEST -------------//
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hcd_pipe_control_xfer(dev_addr, &request_get_dev_desc, xfer_data);
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TEST_ASSERT_EQUAL_HEX( p_setup, p_qhd->qtd_overlay.next.address );
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TEST_ASSERT_EQUAL_HEX( p_setup , p_qhd->p_qtd_list_head);
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TEST_ASSERT_EQUAL_HEX( p_setup, p_control_qhd->qtd_overlay.next.address );
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TEST_ASSERT_EQUAL_HEX( p_setup , p_control_qhd->p_qtd_list_head);
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TEST_ASSERT_EQUAL_HEX( p_data , p_setup->next.address);
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TEST_ASSERT_EQUAL_HEX( p_status , p_data->next.address );
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TEST_ASSERT_TRUE( p_status->next.terminate );
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@ -195,27 +199,19 @@ void test_control_xfer_get(void)
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TEST_ASSERT_EQUAL(EHCI_PID_OUT, p_status->pid);
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TEST_ASSERT_TRUE(p_status->next.terminate);
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TEST_ASSERT_EQUAL_HEX(p_setup, p_qhd->p_qtd_list_head);
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TEST_ASSERT_EQUAL_HEX(p_status, p_qhd->p_qtd_list_tail);
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TEST_ASSERT_EQUAL_HEX(p_setup, p_control_qhd->p_qtd_list_head);
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TEST_ASSERT_EQUAL_HEX(p_status, p_control_qhd->p_qtd_list_tail);
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}
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void test_control_xfer_set(void)
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{
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tusb_std_request_t request_set_dev_addr =
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{
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.bmRequestType = { .direction = TUSB_DIR_HOST_TO_DEV, .type = TUSB_REQUEST_TYPE_STANDARD, .recipient = TUSB_REQUEST_RECIPIENT_DEVICE },
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.bRequest = TUSB_REQUEST_SET_ADDRESS,
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.wValue = 3
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};
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ehci_qhd_t * const p_qhd = &ehci_data.device[dev_addr-1].control.qhd;
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hcd_pipe_control_open(dev_addr, control_max_packet_size);
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//------------- Code Under TEST -------------//
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hcd_pipe_control_xfer(dev_addr, &request_set_dev_addr, xfer_data);
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TEST_ASSERT_EQUAL_HEX( p_setup, p_qhd->qtd_overlay.next.address );
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TEST_ASSERT_EQUAL_HEX( p_setup , p_qhd->p_qtd_list_head);
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TEST_ASSERT_EQUAL_HEX( p_setup, p_control_qhd->qtd_overlay.next.address );
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TEST_ASSERT_EQUAL_HEX( p_setup , p_control_qhd->p_qtd_list_head);
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TEST_ASSERT_EQUAL_HEX( p_status , p_setup->next.address );
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TEST_ASSERT_TRUE( p_status->next.terminate );
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@ -226,27 +222,26 @@ void test_control_xfer_set(void)
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TEST_ASSERT_EQUAL(EHCI_PID_IN, p_status->pid);
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TEST_ASSERT_TRUE(p_status->next.terminate);
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TEST_ASSERT_EQUAL_HEX(p_setup, p_qhd->p_qtd_list_head);
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TEST_ASSERT_EQUAL_HEX(p_status, p_qhd->p_qtd_list_tail);
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TEST_ASSERT_EQUAL_HEX(p_setup, p_control_qhd->p_qtd_list_head);
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TEST_ASSERT_EQUAL_HEX(p_status, p_control_qhd->p_qtd_list_tail);
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}
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void test_control_xfer_isr(void)
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void test_control_xfer_complete_isr(void)
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{
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ehci_qhd_t * const p_qhd = &ehci_data.device[dev_addr-1].control.qhd;
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hcd_pipe_control_open(dev_addr, control_max_packet_size);
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hcd_pipe_control_xfer(dev_addr, &request_get_dev_desc, xfer_data);
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ehci_controller_run(hostid);
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TEST_ASSERT_EQUAL_HEX(async_head, get_operational_register(hostid)->async_list_base);
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TEST_ASSERT_EQUAL_HEX((uint32_t) p_qhd, align32(async_head->next.address));
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TEST_ASSERT_EQUAL_HEX((uint32_t) p_control_qhd, align32(async_head->next.address));
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usbh_isr_Expect(((pipe_handle_t){.dev_addr = dev_addr}), 0);
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//------------- Code Under TEST -------------//
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hcd_isr(hostid);
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TEST_ASSERT_NULL(p_qhd->p_qtd_list_head);
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TEST_ASSERT_NULL(p_qhd->p_qtd_list_tail);
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TEST_ASSERT_NULL(p_control_qhd->p_qtd_list_head);
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TEST_ASSERT_NULL(p_control_qhd->p_qtd_list_tail);
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TEST_ASSERT_FALSE(p_setup->used);
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TEST_ASSERT_FALSE(p_data->used);
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@ -407,7 +407,6 @@ OSAL_TASK_DECLARE(usbh_enumeration_task)
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usbh_device_info_pool[new_addr].state = TUSB_DEVICE_STATE_CONFIGURED;
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tusbh_device_mount_succeed_cb(new_addr);
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// TODO invoke mounted callback
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OSAL_TASK_LOOP_END
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}
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