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esp32-s2_dfu
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Code Issues Releases Activity

remove duplicate link register bit macros 

Signed-off-by: Rafael Silva <rafaelsilva@ajtec.pt>
This commit is contained in:
Rafael Silva 2022-03-09 15:55:35 +00:00
parent e7027efe7a
commit c529d0b440
3 changed files with 136 additions and 168 deletions
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108
src/portable/renesas/link/dcd_link.c
View File

@ -32,7 +32,7 @@
#define USE_SOF 0
#if CFG_TUD_ENABLED && (CFG_TUSB_MCU == OPT_MCU_RX63X || CFG_TUSB_MCU == OPT_MCU_RX65X || CFG_TUSB_MCU == OPT_MCU_RX72N || \
CFG_TUSB_MCU == OPT_MCU_RAXXX)
CFG_TUSB_MCU == OPT_MCU_RAXXX)
#include "device/dcd.h"
#include "link_type.h"
@ -245,7 +245,7 @@ static bool pipe0_xfer_in(void)
}
}
if (len < mps)
LINK_REG->CFIFOCTR = USB_FIFOCTR_BVAL;
LINK_REG->CFIFOCTR = LINK_REG_CFIFOCTR_BVAL_Msk;
pipe->remaining = rem - len;
return false;
}
@ -268,7 +268,7 @@ static bool pipe0_xfer_out(void)
}
}
if (len < mps)
LINK_REG->CFIFOCTR = USB_FIFOCTR_BCLR;
LINK_REG->CFIFOCTR = LINK_REG_CFIFOCTR_BCLR_Msk;
pipe->remaining = rem - len;
if ((len < mps) || (rem == len)) {
pipe->buf = NULL;
@ -287,7 +287,7 @@ static bool pipe_xfer_in(unsigned num)
return true;
}
LINK_REG->D0FIFOSEL = num | USB_FIFOSEL_MBW_16 | (TU_BYTE_ORDER == TU_BIG_ENDIAN ? USB_FIFOSEL_BIGEND : 0);
LINK_REG->D0FIFOSEL = num | LINK_REG_FIFOSEL_MBW_16BIT | (TU_BYTE_ORDER == TU_BIG_ENDIAN ? LINK_REG_FIFOSEL_BIGEND : 0);
const unsigned mps = edpt_max_packet_size(num);
pipe_wait_for_ready(num);
const unsigned len = TU_MIN(rem, mps);
@ -301,7 +301,7 @@ static bool pipe_xfer_in(unsigned num)
}
}
if (len < mps)
LINK_REG->D0FIFOCTR = USB_FIFOCTR_BVAL;
LINK_REG->D0FIFOCTR = LINK_REG_CFIFOCTR_BVAL_Msk;
LINK_REG->D0FIFOSEL = 0;
while (LINK_REG->D0FIFOSEL_b.CURPIPE) continue; /* if CURPIPE bits changes, check written value */
pipe->remaining = rem - len;
@ -313,7 +313,7 @@ static bool pipe_xfer_out(unsigned num)
pipe_state_t *pipe = &_dcd.pipe[num];
const unsigned rem = pipe->remaining;
LINK_REG->D0FIFOSEL = num | USB_FIFOSEL_MBW_8;
LINK_REG->D0FIFOSEL = num | LINK_REG_FIFOSEL_MBW_8BIT;
const unsigned mps = edpt_max_packet_size(num);
pipe_wait_for_ready(num);
const unsigned vld = LINK_REG->D0FIFOCTR_b.DTLN;
@ -328,7 +328,7 @@ static bool pipe_xfer_out(unsigned num)
}
}
if (len < mps)
LINK_REG->D0FIFOCTR = USB_FIFOCTR_BCLR;
LINK_REG->D0FIFOCTR = LINK_REG_CFIFOCTR_BCLR_Msk;
LINK_REG->D0FIFOSEL = 0;
while (LINK_REG->D0FIFOSEL_b.CURPIPE) ; /* if CURPIPE bits changes, check written value */
pipe->remaining = rem - len;
@ -342,13 +342,13 @@ static bool pipe_xfer_out(unsigned num)
static void process_setup_packet(uint8_t rhport)
{
uint16_t setup_packet[4];
if (0 == (LINK_REG->INTSTS0 & USB_IS0_VALID)) return;
LINK_REG->CFIFOCTR = USB_FIFOCTR_BCLR;
if (0 == (LINK_REG->INTSTS0 & LINK_REG_INTSTS0_VALID_Msk)) return;
LINK_REG->CFIFOCTR = LINK_REG_CFIFOCTR_BCLR_Msk;
setup_packet[0] = tu_le16toh(LINK_REG->USBREQ);
setup_packet[1] = LINK_REG->USBVAL;
setup_packet[2] = LINK_REG->USBINDX;
setup_packet[3] = LINK_REG->USBLENG;
LINK_REG->INTSTS0 = ~USB_IS0_VALID;
LINK_REG->INTSTS0 = ~((uint16_t)LINK_REG_INTSTS0_VALID_Msk);
dcd_event_setup_received(rhport, (const uint8_t*)&setup_packet[0], true);
}
@ -356,7 +356,7 @@ static void process_status_completion(uint8_t rhport)
{
uint8_t ep_addr;
/* Check the data stage direction */
if (LINK_REG->CFIFOSEL & USB_FIFOSEL_TX) {
if (LINK_REG->CFIFOSEL & LINK_REG_CFIFOSEL_ISEL_WRITE) {
/* IN transfer. */
ep_addr = tu_edpt_addr(0, TUSB_DIR_IN);
} else {
@ -370,12 +370,12 @@ static bool process_pipe0_xfer(int buffer_type, uint8_t ep_addr, void* buffer, u
{
/* configure fifo direction and access unit settings */
if (ep_addr) { /* IN, 2 bytes */
LINK_REG->CFIFOSEL =
USB_FIFOSEL_TX | USB_FIFOSEL_MBW_16 | (TU_BYTE_ORDER == TU_BIG_ENDIAN ? USB_FIFOSEL_BIGEND : 0);
while (!(LINK_REG->CFIFOSEL & USB_FIFOSEL_TX)) ;
LINK_REG->CFIFOSEL = LINK_REG_CFIFOSEL_ISEL_WRITE | LINK_REG_FIFOSEL_MBW_16BIT |
(TU_BYTE_ORDER == TU_BIG_ENDIAN ? LINK_REG_FIFOSEL_BIGEND : 0);
while (!(LINK_REG->CFIFOSEL & LINK_REG_CFIFOSEL_ISEL_WRITE)) ;
} else { /* OUT, a byte */
LINK_REG->CFIFOSEL = USB_FIFOSEL_MBW_8;
while (LINK_REG->CFIFOSEL & USB_FIFOSEL_TX) ;
LINK_REG->CFIFOSEL = LINK_REG_FIFOSEL_MBW_8BIT;
while (LINK_REG->CFIFOSEL & LINK_REG_CFIFOSEL_ISEL_WRITE) ;
}
pipe_state_t *pipe = &_dcd.pipe[0];
@ -388,11 +388,11 @@ static bool process_pipe0_xfer(int buffer_type, uint8_t ep_addr, void* buffer, u
TU_ASSERT(LINK_REG->DCPCTR_b.BSTS && (LINK_REG->USBREQ & 0x80));
pipe0_xfer_in();
}
LINK_REG->DCPCTR = USB_PIPECTR_PID_BUF;
LINK_REG->DCPCTR = LINK_REG_PIPE_CTR_PID_BUF;
} else {
/* ZLP */
pipe->buf = NULL;
LINK_REG->DCPCTR = USB_PIPECTR_CCPL | USB_PIPECTR_PID_BUF;
LINK_REG->DCPCTR = LINK_REG_DCPCTR_CCPL_Msk | LINK_REG_PIPE_CTR_PID_BUF;
}
return true;
}
@ -416,7 +416,7 @@ static bool process_pipe_xfer(int buffer_type, uint8_t ep_addr, void* buffer, ui
} else { /* ZLP */
LINK_REG->D0FIFOSEL = num;
pipe_wait_for_ready(num);
LINK_REG->D0FIFOCTR = USB_FIFOCTR_BVAL;
LINK_REG->D0FIFOCTR = LINK_REG_CFIFOCTR_BVAL_Msk;
LINK_REG->D0FIFOSEL = 0;
while (LINK_REG->D0FIFOSEL_b.CURPIPE) ; /* if CURPIPE bits changes, check written value */
}
@ -429,11 +429,11 @@ static bool process_pipe_xfer(int buffer_type, uint8_t ep_addr, void* buffer, ui
if (pt) {
const unsigned mps = edpt_max_packet_size(num);
volatile uint16_t *ctr = get_pipectr(num);
if (*ctr & 0x3) *ctr = USB_PIPECTR_PID_NAK;
if (*ctr & 0x3) *ctr = LINK_REG_PIPE_CTR_PID_NAK;
pt->TRE = TU_BIT(8);
pt->TRN = (total_bytes + mps - 1) / mps;
pt->TRENB = 1;
*ctr = USB_PIPECTR_PID_BUF;
*ctr = LINK_REG_PIPE_CTR_PID_BUF;
}
}
// TU_LOG1("X %x %d %d\r\n", ep_addr, total_bytes, buffer_type);
@ -487,7 +487,7 @@ static void process_bus_reset(uint8_t rhport)
{
LINK_REG->BEMPENB = 1;
LINK_REG->BRDYENB = 1;
LINK_REG->CFIFOCTR = USB_FIFOCTR_BCLR;
LINK_REG->CFIFOCTR = LINK_REG_CFIFOCTR_BCLR_Msk;
LINK_REG->D0FIFOSEL = 0;
while (LINK_REG->D0FIFOSEL_b.CURPIPE) ; /* if CURPIPE bits changes, check written value */
LINK_REG->D1FIFOSEL = 0;
@ -497,7 +497,7 @@ static void process_bus_reset(uint8_t rhport)
for (int i = 1; i <= 5; ++i) {
LINK_REG->PIPESEL = i;
LINK_REG->PIPECFG = 0;
*ctr = USB_PIPECTR_ACLRM;
*ctr = LINK_REG_PIPE_CTR_ACLRM_Msk;
*ctr = 0;
++ctr;
*tre = TU_BIT(8);
@ -506,7 +506,7 @@ static void process_bus_reset(uint8_t rhport)
for (int i = 6; i <= 9; ++i) {
LINK_REG->PIPESEL = i;
LINK_REG->PIPECFG = 0;
*ctr = USB_PIPECTR_ACLRM;
*ctr = LINK_REG_PIPE_CTR_ACLRM_Msk;
*ctr = 0;
++ctr;
}
@ -553,8 +553,9 @@ void dcd_init(uint8_t rhport)
/* Setup default control pipe */
LINK_REG->DCPMAXP_b.MXPS = 64;
LINK_REG->INTENB0 = USB_IS0_VBINT | USB_IS0_BRDY | USB_IS0_BEMP | USB_IS0_DVST | USB_IS0_CTRT |
(USE_SOF ? USB_IS0_SOFR : 0) | USB_IS0_RESM;
LINK_REG->INTENB0 = LINK_REG_INTSTS0_VBINT_Msk | LINK_REG_INTSTS0_BRDY_Msk | LINK_REG_INTSTS0_BEMP_Msk |
LINK_REG_INTSTS0_DVST_Msk | LINK_REG_INTSTS0_CTRT_Msk | (USE_SOF ? LINK_REG_INTSTS0_SOFR_Msk : 0) |
LINK_REG_INTSTS0_RESM_Msk;
LINK_REG->BEMPENB = 1;
LINK_REG->BRDYENB = 1;
@ -633,21 +634,21 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * ep_desc)
LINK_REG->PIPESEL = num;
LINK_REG->PIPEMAXP = mps;
volatile uint16_t *ctr = get_pipectr(num);
*ctr = USB_PIPECTR_ACLRM | USB_PIPECTR_SQCLR;
*ctr = LINK_REG_PIPE_CTR_ACLRM_Msk | LINK_REG_PIPE_CTR_SQCLR_Msk;
*ctr = 0;
unsigned cfg = (dir << 4) | epn;
if (xfer == TUSB_XFER_BULK) {
cfg |= (USB_PIPECFG_BULK | USB_PIPECFG_SHTNAK | USB_PIPECFG_DBLB);
cfg |= (LINK_REG_PIPECFG_TYPE_BULK | LINK_REG_PIPECFG_SHTNAK_Msk | LINK_REG_PIPECFG_DBLB_Msk);
} else if (xfer == TUSB_XFER_INTERRUPT) {
cfg |= USB_PIPECFG_INT;
cfg |= LINK_REG_PIPECFG_TYPE_ISO;
} else {
cfg |= (USB_PIPECFG_ISO | USB_PIPECFG_DBLB);
cfg |= (LINK_REG_PIPECFG_TYPE_INT | LINK_REG_PIPECFG_DBLB_Msk);
}
LINK_REG->PIPECFG = cfg;
LINK_REG->BRDYSTS = 0x1FFu ^ TU_BIT(num);
LINK_REG->BRDYENB |= TU_BIT(num);
if (dir || (xfer != TUSB_XFER_BULK)) {
*ctr = USB_PIPECTR_PID_BUF;
*ctr = LINK_REG_PIPE_CTR_PID_BUF;
}
// TU_LOG1("O %d %x %x\r\n", LINK_REG->PIPESEL, LINK_REG->PIPECFG, LINK_REG->PIPEMAXP);
dcd_int_enable(rhport);
@ -709,8 +710,8 @@ void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr)
if (!ctr) return;
dcd_int_disable(rhport);
const uint32_t pid = *ctr & 0x3;
*ctr = pid | USB_PIPECTR_PID_STALL;
*ctr = USB_PIPECTR_PID_STALL;
*ctr = pid | LINK_REG_PIPE_CTR_PID_STALL;
*ctr = LINK_REG_PIPE_CTR_PID_STALL;
dcd_int_enable(rhport);
}
@ -719,15 +720,15 @@ void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr)
volatile uint16_t *ctr = ep_addr_to_pipectr(rhport, ep_addr);
if (!ctr) return;
dcd_int_disable(rhport);
*ctr = USB_PIPECTR_SQCLR;
*ctr = LINK_REG_PIPE_CTR_SQCLR_Msk;
if (tu_edpt_dir(ep_addr)) { /* IN */
*ctr = USB_PIPECTR_PID_BUF;
*ctr = LINK_REG_PIPE_CTR_PID_BUF;
} else {
const unsigned num = _dcd.ep[0][tu_edpt_number(ep_addr)];
LINK_REG->PIPESEL = num;
if (LINK_REG->PIPECFG_b.TYPE != 1) {
*ctr = USB_PIPECTR_PID_BUF;
*ctr = LINK_REG_PIPE_CTR_PID_BUF;
}
}
dcd_int_enable(rhport);
@ -742,39 +743,40 @@ void dcd_int_handler(uint8_t rhport)
unsigned is0 = LINK_REG->INTSTS0;
/* clear active bits except VALID (don't write 0 to already cleared bits according to the HW manual) */
LINK_REG->INTSTS0 = ~((USB_IS0_CTRT | USB_IS0_DVST | USB_IS0_SOFR | USB_IS0_RESM | USB_IS0_VBINT) & is0) | USB_IS0_VALID;
if (is0 & USB_IS0_VBINT) {
LINK_REG->INTSTS0 = ~((LINK_REG_INTSTS0_CTRT_Msk | LINK_REG_INTSTS0_DVST_Msk | LINK_REG_INTSTS0_SOFR_Msk |
LINK_REG_INTSTS0_RESM_Msk | LINK_REG_INTSTS0_VBINT_Msk) & is0) | LINK_REG_INTSTS0_VALID_Msk;
if (is0 & LINK_REG_INTSTS0_VBINT_Msk) {
if (LINK_REG->INTSTS0_b.VBSTS) {
dcd_connect(rhport);
} else {
dcd_disconnect(rhport);
}
}
if (is0 & USB_IS0_RESM) {
if (is0 & LINK_REG_INTSTS0_RESM_Msk) {
dcd_event_bus_signal(rhport, DCD_EVENT_RESUME, true);
#if (0==USE_SOF)
LINK_REG->INTENB0_b.SOFE = 0;
#endif
}
if ((is0 & USB_IS0_SOFR) && LINK_REG->INTENB0_b.SOFE) {
if ((is0 & LINK_REG_INTSTS0_SOFR_Msk) && LINK_REG->INTENB0_b.SOFE) {
// USBD will exit suspended mode when SOF event is received
dcd_event_bus_signal(rhport, DCD_EVENT_SOF, true);
#if (0 == USE_SOF)
LINK_REG->INTENB0_b.SOFE = 0;
#endif
}
if (is0 & USB_IS0_DVST) {
switch (is0 & USB_IS0_DVSQ) {
case USB_IS0_DVSQ_DEF:
if (is0 & LINK_REG_INTSTS0_DVST_Msk) {
switch (is0 & LINK_REG_INTSTS0_DVSQ_Msk) {
case LINK_REG_INTSTS0_DVSQ_STATE_DEF:
process_bus_reset(rhport);
break;
case USB_IS0_DVSQ_ADDR:
case LINK_REG_INTSTS0_DVSQ_STATE_ADDR:
process_set_address(rhport);
break;
case USB_IS0_DVSQ_SUSP0:
case USB_IS0_DVSQ_SUSP1:
case USB_IS0_DVSQ_SUSP2:
case USB_IS0_DVSQ_SUSP3:
case LINK_REG_INTSTS0_DVSQ_STATE_SUSP0:
case LINK_REG_INTSTS0_DVSQ_STATE_SUSP1:
case LINK_REG_INTSTS0_DVSQ_STATE_SUSP2:
case LINK_REG_INTSTS0_DVSQ_STATE_SUSP3:
dcd_event_bus_signal(rhport, DCD_EVENT_SUSPEND, true);
#if (0==USE_SOF)
LINK_REG->INTENB0_b.SOFE = 1;
@ -783,23 +785,23 @@ void dcd_int_handler(uint8_t rhport)
break;
}
}
if (is0 & USB_IS0_CTRT) {
if (is0 & USB_IS0_CTSQ_SETUP) {
if (is0 & LINK_REG_INTSTS0_CTRT_Msk) {
if (is0 & LINK_REG_INTSTS0_CTSQ_CTRL_RDATA) {
/* A setup packet has been received. */
process_setup_packet(rhport);
} else if (0 == (is0 & USB_IS0_CTSQ_MSK)) {
} else if (0 == (is0 & LINK_REG_INTSTS0_CTSQ_Msk)) {
/* A ZLP has been sent/received. */
process_status_completion(rhport);
}
}
if (is0 & USB_IS0_BEMP) {
if (is0 & LINK_REG_INTSTS0_BEMP_Msk) {
const unsigned s = LINK_REG->BEMPSTS;
LINK_REG->BEMPSTS = 0;
if (s & 1) {
process_pipe0_bemp(rhport);
}
}
if (is0 & USB_IS0_BRDY) {
if (is0 & LINK_REG_INTSTS0_BRDY_Msk) {
const unsigned m = LINK_REG->BRDYENB;
unsigned s = LINK_REG->BRDYSTS & m;
/* clear active bits (don't write 0 to already cleared bits according to the HW manual) */

98
src/portable/renesas/link/hcd_link.c
View File

@ -207,18 +207,18 @@ static bool pipe0_xfer_in(void)
const unsigned len = TU_MIN(TU_MIN(rem, mps), vld);
void *buf = pipe->buf;
if (len) {
LINK_REG->DCPCTR = USB_PIPECTR_PID_NAK;
LINK_REG->DCPCTR = LINK_REG_PIPE_CTR_PID_NAK;
pipe_read_packet(buf, (volatile void*)&LINK_REG->CFIFO, len);
pipe->buf = (uint8_t*)buf + len;
}
if (len < mps)
LINK_REG->CFIFOCTR = USB_FIFOCTR_BCLR;
LINK_REG->CFIFOCTR = LINK_REG_CFIFOCTR_BCLR_Msk;
pipe->remaining = rem - len;
if ((len < mps) || (rem == len)) {
pipe->buf = NULL;
return true;
}
LINK_REG->DCPCTR = USB_PIPECTR_PID_BUF;
LINK_REG->DCPCTR = LINK_REG_PIPE_CTR_PID_BUF;
return false;
}
@ -238,7 +238,7 @@ static bool pipe0_xfer_out(void)
pipe->buf = (uint8_t*)buf + len;
}
if (len < mps)
LINK_REG->CFIFOCTR = USB_FIFOCTR_BVAL;
LINK_REG->CFIFOCTR = LINK_REG_CFIFOCTR_BVAL_Msk;
pipe->remaining = rem - len;
return false;
}
@ -248,7 +248,7 @@ static bool pipe_xfer_in(unsigned num)
pipe_state_t *pipe = &_hcd.pipe[num];
const unsigned rem = pipe->remaining;
LINK_REG->D0FIFOSEL = num | USB_FIFOSEL_MBW_8;
LINK_REG->D0FIFOSEL = num | LINK_REG_FIFOSEL_MBW_8BIT;
const unsigned mps = edpt_max_packet_size(num);
pipe_wait_for_ready(num);
const unsigned vld = LINK_REG->D0FIFOCTR_b.DTLN;
@ -259,7 +259,7 @@ static bool pipe_xfer_in(unsigned num)
pipe->buf = (uint8_t*)buf + len;
}
if (len < mps)
LINK_REG->D0FIFOCTR = USB_FIFOCTR_BCLR;
LINK_REG->D0FIFOCTR = LINK_REG_CFIFOCTR_BCLR_Msk;
LINK_REG->D0FIFOSEL = 0;
while (LINK_REG->D0FIFOSEL_b.CURPIPE) ; /* if CURPIPE bits changes, check written value */
pipe->remaining = rem - len;
@ -280,7 +280,7 @@ static bool pipe_xfer_out(unsigned num)
return true;
}
LINK_REG->D0FIFOSEL = num | USB_FIFOSEL_MBW_16 | (TU_BYTE_ORDER == TU_BIG_ENDIAN ? USB_FIFOSEL_BIGEND : 0);
LINK_REG->D0FIFOSEL = num | LINK_REG_FIFOSEL_MBW_16BIT | (TU_BYTE_ORDER == TU_BIG_ENDIAN ? LINK_REG_FIFOSEL_BIGEND : 0);
const unsigned mps = edpt_max_packet_size(num);
pipe_wait_for_ready(num);
const unsigned len = TU_MIN(rem, mps);
@ -290,7 +290,7 @@ static bool pipe_xfer_out(unsigned num)
pipe->buf = (uint8_t*)buf + len;
}
if (len < mps)
LINK_REG->D0FIFOCTR = USB_FIFOCTR_BVAL;
LINK_REG->D0FIFOCTR = LINK_REG_CFIFOCTR_BVAL_Msk;
LINK_REG->D0FIFOSEL = 0;
while (LINK_REG->D0FIFOSEL_b.CURPIPE) ; /* if CURPIPE bits changes, check written value */
pipe->remaining = rem - len;
@ -304,12 +304,12 @@ static bool process_pipe0_xfer(uint8_t dev_addr, uint8_t ep_addr, void* buffer,
/* configure fifo direction and access unit settings */
if (dir_in) { /* IN, a byte */
LINK_REG->CFIFOSEL = USB_FIFOSEL_MBW_8;
while (LINK_REG->CFIFOSEL & USB_FIFOSEL_TX) ;
LINK_REG->CFIFOSEL = LINK_REG_FIFOSEL_MBW_8BIT;
while (LINK_REG->CFIFOSEL & LINK_REG_CFIFOSEL_ISEL_WRITE) ;
} else { /* OUT, 2 bytes */
LINK_REG->CFIFOSEL =
USB_FIFOSEL_TX | USB_FIFOSEL_MBW_16 | (TU_BYTE_ORDER == TU_BIG_ENDIAN ? USB_FIFOSEL_BIGEND : 0);
while (!(LINK_REG->CFIFOSEL & USB_FIFOSEL_TX)) ;
LINK_REG->CFIFOSEL = LINK_REG_CFIFOSEL_ISEL_WRITE | LINK_REG_FIFOSEL_MBW_16BIT |
(TU_BYTE_ORDER == TU_BIG_ENDIAN ? LINK_REG_FIFOSEL_BIGEND : 0);
while (!(LINK_REG->CFIFOSEL & LINK_REG_CFIFOSEL_ISEL_WRITE)) ;
}
pipe_state_t *pipe = &_hcd.pipe[0];
@ -325,15 +325,15 @@ static bool process_pipe0_xfer(uint8_t dev_addr, uint8_t ep_addr, void* buffer,
} else { /* ZLP */
pipe->buf = NULL;
if (!dir_in) { /* OUT */
LINK_REG->CFIFOCTR = USB_FIFOCTR_BVAL;
LINK_REG->CFIFOCTR = LINK_REG_CFIFOCTR_BVAL_Msk;
}
if (dir_in == LINK_REG->DCPCFG_b.DIR) {
TU_ASSERT(USB_PIPECTR_PID_NAK == LINK_REG->DCPCTR_b.PID);
TU_ASSERT(LINK_REG_PIPE_CTR_PID_NAK == LINK_REG->DCPCTR_b.PID);
LINK_REG->DCPCTR_b.SQSET = 1;
LINK_REG->DCPCFG_b.DIR = dir_in ^ 1;
}
}
LINK_REG->DCPCTR = USB_PIPECTR_PID_BUF;
LINK_REG->DCPCTR = LINK_REG_PIPE_CTR_PID_BUF;
return true;
}
@ -355,7 +355,7 @@ static bool process_pipe_xfer(uint8_t dev_addr, uint8_t ep_addr, void *buffer, u
} else { /* ZLP */
LINK_REG->D0FIFOSEL = num;
pipe_wait_for_ready(num);
LINK_REG->D0FIFOCTR = USB_FIFOCTR_BVAL;
LINK_REG->D0FIFOCTR = LINK_REG_CFIFOCTR_BVAL_Msk;
LINK_REG->D0FIFOSEL = 0;
while (LINK_REG->D0FIFOSEL_b.CURPIPE) continue; /* if CURPIPE bits changes, check written value */
}
@ -364,12 +364,12 @@ static bool process_pipe_xfer(uint8_t dev_addr, uint8_t ep_addr, void *buffer, u
volatile reg_pipetre_t *pt = get_pipetre(num);
if (pt) {
const unsigned mps = edpt_max_packet_size(num);
if (*ctr & 0x3) *ctr = USB_PIPECTR_PID_NAK;
if (*ctr & 0x3) *ctr = LINK_REG_PIPE_CTR_PID_NAK;
pt->TRE = TU_BIT(8);
pt->TRN = (buflen + mps - 1) / mps;
pt->TRENB = 1;
}
*ctr = USB_PIPECTR_PID_BUF;
*ctr = LINK_REG_PIPE_CTR_PID_BUF;
}
return true;
}
@ -403,10 +403,10 @@ static void process_pipe_nrdy(uint8_t rhport, unsigned num)
unsigned result;
uint16_t volatile *ctr = get_pipectr(num);
// TU_LOG1("NRDY %d %x\n", num, *ctr);
switch (*ctr & USB_PIPECTR_PID_MSK) {
switch (*ctr & LINK_REG_PIPE_CTR_PID_Msk) {
default: return;
case USB_PIPECTR_PID_STALL: result = XFER_RESULT_STALLED; break;
case USB_PIPECTR_PID_NAK: result = XFER_RESULT_FAILED; break;
case LINK_REG_PIPE_CTR_PID_STALL: result = XFER_RESULT_STALLED; break;
case LINK_REG_PIPE_CTR_PID_NAK: result = XFER_RESULT_FAILED; break;
}
pipe_state_t *pipe = &_hcd.pipe[num];
hcd_event_xfer_complete(pipe->dev, pipe->ep,
@ -464,10 +464,10 @@ bool hcd_init(uint8_t rhport)
LINK_REG->DPUSR0R_FS_b.FIXPHY0 = 0u; /* Transceiver Output fixed */
/* Setup default control pipe */
LINK_REG->DCPCFG = USB_PIPECFG_SHTNAK;
LINK_REG->DCPCFG = LINK_REG_PIPECFG_SHTNAK_Msk;
LINK_REG->DCPMAXP = 64;
LINK_REG->INTENB0 = USB_IS0_BRDY | USB_IS0_NRDY | USB_IS0_BEMP;
LINK_REG->INTENB1 = USB_IS1_SACK | USB_IS1_SIGN | USB_IS1_ATTCH | USB_IS1_DTCH;
LINK_REG->INTENB0 = LINK_REG_INTSTS0_BRDY_Msk | LINK_REG_INTSTS0_NRDY_Msk | LINK_REG_INTSTS0_BEMP_Msk;
LINK_REG->INTENB1 = LINK_REG_INTSTS1_SACK_Msk | LINK_REG_INTSTS1_SIGN_Msk | LINK_REG_INTSTS1_ATTCH_Msk | LINK_REG_INTSTS1_DTCH_Msk;
LINK_REG->BEMPENB = 1;
LINK_REG->NRDYENB = 1;
LINK_REG->BRDYENB = 1;
@ -505,7 +505,7 @@ bool hcd_port_connect_status(uint8_t rhport)
void hcd_port_reset(uint8_t rhport)
{
LINK_REG->DCPCTR = USB_PIPECTR_PID_NAK;
LINK_REG->DCPCTR = LINK_REG_PIPE_CTR_PID_NAK;
while (LINK_REG->DCPCTR_b.PBUSY) ;
hcd_int_disable(rhport);
LINK_REG->DVSTCTR0_b.UACT = 0;
@ -530,8 +530,8 @@ tusb_speed_t hcd_port_speed_get(uint8_t rhport)
(void)rhport;
switch (LINK_REG->DVSTCTR0_b.RHST) {
default: return TUSB_SPEED_INVALID;
case USB_DVSTCTR0_FULL: return TUSB_SPEED_FULL;
case USB_DVSTCTR0_LOW: return TUSB_SPEED_LOW;
case LINK_REG_DVSTCTR0_RHST_FS: return TUSB_SPEED_FULL;
case LINK_REG_DVSTCTR0_RHST_LS: return TUSB_SPEED_LOW;
}
}
@ -572,7 +572,7 @@ bool hcd_setup_send(uint8_t rhport, uint8_t dev_addr, uint8_t const setup_packet
TU_ASSERT(dev_addr < 6); /* USBa can only handle addresses from 0 to 5. */
TU_ASSERT(0 == LINK_REG->DCPCTR_b.SUREQ);
LINK_REG->DCPCTR = USB_PIPECTR_PID_NAK;
LINK_REG->DCPCTR = LINK_REG_PIPE_CTR_PID_NAK;
_hcd.pipe[0].buf = NULL;
_hcd.pipe[0].length = 8;
@ -605,14 +605,14 @@ bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const
const unsigned epn = tu_edpt_number(ep_addr);
const unsigned mps = tu_edpt_packet_size(ep_desc);
if (0 == epn) {
LINK_REG->DCPCTR = USB_PIPECTR_PID_NAK;
LINK_REG->DCPCTR = LINK_REG_PIPE_CTR_PID_NAK;
hcd_devtree_info_t devtree;
hcd_devtree_get_info(dev_addr, &devtree);
uint16_t volatile *devadd = (uint16_t volatile *)(uintptr_t) &LINK_REG->DEVADD[0];
devadd += dev_addr;
while (LINK_REG->DCPCTR_b.PBUSY) ;
LINK_REG->DCPMAXP = (dev_addr << 12) | mps;
*devadd = (TUSB_SPEED_FULL == devtree.speed) ? USB_DEVADD_FULL : USB_DEVADD_LOW;
*devadd = (TUSB_SPEED_FULL == devtree.speed) ? LINK_REG_DEVADD_USBSPD_FS : LINK_REG_DEVADD_USBSPD_LS;
_hcd.ctl_mps[dev_addr] = mps;
return true;
}
@ -634,22 +634,22 @@ bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const
LINK_REG->PIPESEL = num;
LINK_REG->PIPEMAXP = (dev_addr << 12) | mps;
volatile uint16_t *ctr = get_pipectr(num);
*ctr = USB_PIPECTR_ACLRM | USB_PIPECTR_SQCLR;
*ctr = LINK_REG_PIPE_CTR_ACLRM_Msk | LINK_REG_PIPE_CTR_SQCLR_Msk;
*ctr = 0;
unsigned cfg = ((1 ^ dir_in) << 4) | epn;
if (xfer == TUSB_XFER_BULK) {
cfg |= USB_PIPECFG_BULK | USB_PIPECFG_SHTNAK | USB_PIPECFG_DBLB;
cfg |= LINK_REG_PIPECFG_TYPE_BULK | LINK_REG_PIPECFG_SHTNAK_Msk | LINK_REG_PIPECFG_DBLB_Msk;
} else if (xfer == TUSB_XFER_INTERRUPT) {
cfg |= USB_PIPECFG_INT;
cfg |= LINK_REG_PIPECFG_TYPE_ISO;
} else {
cfg |= USB_PIPECFG_ISO | USB_PIPECFG_DBLB;
cfg |= LINK_REG_PIPECFG_TYPE_INT | LINK_REG_PIPECFG_DBLB_Msk;
}
LINK_REG->PIPECFG = cfg;
LINK_REG->BRDYSTS = 0x1FFu ^ TU_BIT(num);
LINK_REG->NRDYENB |= TU_BIT(num);
LINK_REG->BRDYENB |= TU_BIT(num);
if (!dir_in) {
*ctr = USB_PIPECTR_PID_BUF;
*ctr = LINK_REG_PIPE_CTR_PID_BUF;
}
hcd_int_enable(rhport);
@ -676,12 +676,12 @@ bool hcd_edpt_clear_stall(uint8_t dev_addr, uint8_t ep_addr)
*ctr = pid & 2;
*ctr = 0;
}
*ctr = USB_PIPECTR_SQCLR;
*ctr = LINK_REG_PIPE_CTR_SQCLR_Msk;
unsigned const epn = tu_edpt_number(ep_addr);
if (!epn) return true;
if (!tu_edpt_dir(ep_addr)) { /* OUT */
*ctr = USB_PIPECTR_PID_BUF;
*ctr = LINK_REG_PIPE_CTR_PID_BUF;
}
return true;
}
@ -702,44 +702,44 @@ void hcd_int_handler(uint8_t rhport)
unsigned is1 = LINK_REG->INTSTS1;
unsigned is0 = LINK_REG->INTSTS0;
/* clear active bits except VALID (don't write 0 to already cleared bits according to the HW manual) */
LINK_REG->INTSTS1 = ~((USB_IS1_SACK | USB_IS1_SIGN | USB_IS1_ATTCH | USB_IS1_DTCH) & is1);
LINK_REG->INTSTS0 = ~((USB_IS0_BRDY | USB_IS0_NRDY | USB_IS0_BEMP) & is0);
LINK_REG->INTSTS1 = ~((LINK_REG_INTSTS1_SACK_Msk | LINK_REG_INTSTS1_SIGN_Msk | LINK_REG_INTSTS1_ATTCH_Msk | LINK_REG_INTSTS1_DTCH_Msk) & is1);
LINK_REG->INTSTS0 = ~((LINK_REG_INTSTS0_BRDY_Msk | LINK_REG_INTSTS0_NRDY_Msk | LINK_REG_INTSTS0_BEMP_Msk) & is0);
// TU_LOG1("IS %04x %04x\n", is0, is1);
is1 &= LINK_REG->INTENB1;
is0 &= LINK_REG->INTENB0;
if (is1 & USB_IS1_SACK) {
if (is1 & LINK_REG_INTSTS1_SACK_Msk) {
/* Set DATA1 in advance for the next transfer. */
LINK_REG->DCPCTR_b.SQSET = 1;
hcd_event_xfer_complete(
LINK_REG->DCPMAXP_b.DEVSEL, tu_edpt_addr(0, TUSB_DIR_OUT), 8, XFER_RESULT_SUCCESS, true);
}
if (is1 & USB_IS1_SIGN) {
if (is1 & LINK_REG_INTSTS1_SIGN_Msk) {
hcd_event_xfer_complete(
LINK_REG->DCPMAXP_b.DEVSEL, tu_edpt_addr(0, TUSB_DIR_OUT), 8, XFER_RESULT_FAILED, true);
}
if (is1 & USB_IS1_ATTCH) {
if (is1 & LINK_REG_INTSTS1_ATTCH_Msk) {
LINK_REG->DVSTCTR0_b.UACT = 1;
_hcd.need_reset = true;
LINK_REG->INTENB1 = (LINK_REG->INTENB1 & ~USB_IS1_ATTCH) | USB_IS1_DTCH;
LINK_REG->INTENB1 = (LINK_REG->INTENB1 & ~LINK_REG_INTSTS1_ATTCH_Msk) | LINK_REG_INTSTS1_DTCH_Msk;
hcd_event_device_attach(rhport, true);
}
if (is1 & USB_IS1_DTCH) {
if (is1 & LINK_REG_INTSTS1_DTCH_Msk) {
LINK_REG->DVSTCTR0_b.UACT = 0;
if (LINK_REG->DCPCTR_b.SUREQ)
LINK_REG->DCPCTR_b.SUREQCLR = 1;
LINK_REG->INTENB1 = (LINK_REG->INTENB1 & ~USB_IS1_DTCH) | USB_IS1_ATTCH;
LINK_REG->INTENB1 = (LINK_REG->INTENB1 & ~LINK_REG_INTSTS1_DTCH_Msk) | LINK_REG_INTSTS1_ATTCH_Msk;
hcd_event_device_remove(rhport, true);
}
if (is0 & USB_IS0_BEMP) {
if (is0 & LINK_REG_INTSTS0_BEMP_Msk) {
const unsigned s = LINK_REG->BEMPSTS;
LINK_REG->BEMPSTS = 0;
if (s & 1) {
process_pipe0_bemp(rhport);
}
}
if (is0 & USB_IS0_NRDY) {
if (is0 & LINK_REG_INTSTS0_NRDY_Msk) {
const unsigned m = LINK_REG->NRDYENB;
unsigned s = LINK_REG->NRDYSTS & m;
LINK_REG->NRDYSTS = ~s;
@ -753,7 +753,7 @@ void hcd_int_handler(uint8_t rhport)
s &= ~TU_BIT(num);
}
}
if (is0 & USB_IS0_BRDY) {
if (is0 & LINK_REG_INTSTS0_BRDY_Msk) {
const unsigned m = LINK_REG->BRDYENB;
unsigned s = LINK_REG->BRDYSTS & m;
/* clear active bits (don't write 0 to already cleared bits according to the HW manual) */

98
src/portable/renesas/link/link_type.h
View File

@ -33,72 +33,6 @@
extern "C" {
#endif
//--------------------------------------------------------------------+
// MACRO TYPEDEF CONSTANT ENUM DECLARATION
//--------------------------------------------------------------------+
#define USB_DVSTCTR0_LOW (1u)
#define USB_DVSTCTR0_FULL (2u)
#define USB_FIFOSEL_TX ((uint16_t) (1u << 5))
#define USB_FIFOSEL_BIGEND ((uint16_t) (1u << 8))
#define USB_FIFOSEL_MBW_8 ((uint16_t) (0u << 10))
#define USB_FIFOSEL_MBW_16 ((uint16_t) (1u << 10))
#define USB_IS0_CTSQ ((uint16_t) (7u))
#define USB_IS0_DVSQ ((uint16_t) (7u << 4))
#define USB_IS0_VALID ((uint16_t) (1u << 3))
#define USB_IS0_BRDY ((uint16_t) (1u << 8))
#define USB_IS0_NRDY ((uint16_t) (1u << 9))
#define USB_IS0_BEMP ((uint16_t) (1u << 10))
#define USB_IS0_CTRT ((uint16_t) (1u << 11))
#define USB_IS0_DVST ((uint16_t) (1u << 12))
#define USB_IS0_SOFR ((uint16_t) (1u << 13))
#define USB_IS0_RESM ((uint16_t) (1u << 14))
#define USB_IS0_VBINT ((uint16_t) (1u << 15))
#define USB_IS1_SACK ((uint16_t) (1u << 4))
#define USB_IS1_SIGN ((uint16_t) (1u << 5))
#define USB_IS1_EOFERR ((uint16_t) (1u << 6))
#define USB_IS1_ATTCH ((uint16_t) (1u << 11))
#define USB_IS1_DTCH ((uint16_t) (1u << 12))
#define USB_IS1_BCHG ((uint16_t) (1u << 14))
#define USB_IS1_OVRCR ((uint16_t) (1u << 15))
#define USB_IS0_CTSQ_MSK (7u)
#define USB_IS0_CTSQ_SETUP (1u)
#define USB_IS0_DVSQ_DEF (1u << 4)
#define USB_IS0_DVSQ_ADDR (2u << 4)
#define USB_IS0_DVSQ_SUSP0 (4u << 4)
#define USB_IS0_DVSQ_SUSP1 (5u << 4)
#define USB_IS0_DVSQ_SUSP2 (6u << 4)
#define USB_IS0_DVSQ_SUSP3 (7u << 4)
#define USB_PIPECTR_PID_MSK (3u)
#define USB_PIPECTR_PID_NAK (0u)
#define USB_PIPECTR_PID_BUF (1u)
#define USB_PIPECTR_PID_STALL (2u)
#define USB_PIPECTR_CCPL (1u << 2)
#define USB_PIPECTR_SQMON (1u << 6)
#define USB_PIPECTR_SQCLR (1u << 8)
#define USB_PIPECTR_ACLRM (1u << 9)
#define USB_PIPECTR_INBUFM (1u << 14)
#define USB_PIPECTR_BSTS (1u << 15)
#define USB_FIFOCTR_DTLN (0x1FF)
#define USB_FIFOCTR_FRDY (1u << 13)
#define USB_FIFOCTR_BCLR (1u << 14)
#define USB_FIFOCTR_BVAL (1u << 15)
#define USB_PIPECFG_SHTNAK (1u << 7)
#define USB_PIPECFG_DBLB (1u << 9)
#define USB_PIPECFG_BULK (1u << 14)
#define USB_PIPECFG_ISO (3u << 14)
#define USB_PIPECFG_INT (2u << 14)
#define FIFO_REQ_CLR (1u)
#define FIFO_COMPLETE (1u << 1)
#define USB_DEVADD_LOW (1u << 6)
#define USB_DEVADD_FULL (2u << 6)
/*--------------------------------------------------------------------*/
/* Register Definitions */
/*--------------------------------------------------------------------*/
@ -1651,6 +1585,38 @@ TU_ATTR_PACKED_END /* End of definition of packed structs (used by the CCRX tool
#define LINK_REG_DPUSR1R_FS_DPINTE0_Pos (0UL) /* DPINTE0 (Bit 0) */
#define LINK_REG_DPUSR1R_FS_DPINTE0_Msk (0x1UL) /* DPINTE0 (Bitfield-Mask: 0x01) */
/*--------------------------------------------------------------------*/
/* Register Bit Utils */
/*--------------------------------------------------------------------*/
#define LINK_REG_PIPE_CTR_PID_NAK (0U << LINK_REG_PIPE_CTR_PID_Pos) /* NAK response */
#define LINK_REG_PIPE_CTR_PID_BUF (1U << LINK_REG_PIPE_CTR_PID_Pos) /* BUF response (depends buffer state) */
#define LINK_REG_PIPE_CTR_PID_STALL (2U << LINK_REG_PIPE_CTR_PID_Pos) /* STALL response */
#define LINK_REG_DVSTCTR0_RHST_LS (1U << LINK_REG_DVSTCTR0_RHST_Pos) /* Low-speed connection */
#define LINK_REG_DVSTCTR0_RHST_FS (2U << LINK_REG_DVSTCTR0_RHST_Pos) /* Full-speed connection */
#define LINK_REG_DEVADD_USBSPD_LS (1U << LINK_REG_DEVADD_USBSPD_Pos) /* Target Device Low-speed */
#define LINK_REG_DEVADD_USBSPD_FS (2U << LINK_REG_DEVADD_USBSPD_Pos) /* Target Device Full-speed */
#define LINK_REG_CFIFOSEL_ISEL_WRITE (1U << LINK_REG_CFIFOSEL_ISEL_Pos) /* FIFO write AKA TX*/
#define LINK_REG_FIFOSEL_BIGEND (1U << LINK_REG_CFIFOSEL_BIGEND_Pos) /* FIFO Big Endian */
#define LINK_REG_FIFOSEL_MBW_8BIT (0U << LINK_REG_CFIFOSEL_MBW_Pos) /* 8-bit width */
#define LINK_REG_FIFOSEL_MBW_16BIT (1U << LINK_REG_CFIFOSEL_MBW_Pos) /* 16-bit width */
#define LINK_REG_INTSTS0_CTSQ_CTRL_RDATA (1U << LINK_REG_INTSTS0_CTSQ_Pos)
#define LINK_REG_INTSTS0_DVSQ_STATE_DEF (1U << LINK_REG_INTSTS0_DVSQ_Pos) /* Default state */
#define LINK_REG_INTSTS0_DVSQ_STATE_ADDR (2U << LINK_REG_INTSTS0_DVSQ_Pos) /* Address state */
#define LINK_REG_INTSTS0_DVSQ_STATE_SUSP0 (4U << LINK_REG_INTSTS0_DVSQ_Pos) /* Suspend state */
#define LINK_REG_INTSTS0_DVSQ_STATE_SUSP1 (5U << LINK_REG_INTSTS0_DVSQ_Pos) /* Suspend state */
#define LINK_REG_INTSTS0_DVSQ_STATE_SUSP2 (6U << LINK_REG_INTSTS0_DVSQ_Pos) /* Suspend state */
#define LINK_REG_INTSTS0_DVSQ_STATE_SUSP3 (7U << LINK_REG_INTSTS0_DVSQ_Pos) /* Suspend state */
#define LINK_REG_PIPECFG_TYPE_BULK (1U << LINK_REG_PIPECFG_TYPE_Pos)
#define LINK_REG_PIPECFG_TYPE_INT (2U << LINK_REG_PIPECFG_TYPE_Pos)
#define LINK_REG_PIPECFG_TYPE_ISO (3U << LINK_REG_PIPECFG_TYPE_Pos)
#ifdef __cplusplus
}
#endif