add hw config struct
This commit is contained in:
hathach
parent
68fa9d4064
commit
bb5dab5c2e
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@ -96,7 +96,7 @@ void board_led_task(void)
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TU_ATTR_USED int sys_write (int fhdl, const void *buf, size_t count)
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{
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(void) fhdl;
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SEGGER_RTT_Write(0, (char*) buf, (int) count);
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SEGGER_RTT_Write(0, (const char*) buf, (int) count);
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return count;
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}
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@ -303,8 +303,8 @@ void tu_print_var(uint8_t const* buf, uint32_t bufsize)
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#define TU_LOG1 tu_printf
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#define TU_LOG1_MEM tu_print_mem
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#define TU_LOG1_VAR(_x) tu_print_var((uint8_t const*)(_x), sizeof(*(_x)))
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#define TU_LOG1_INT(_x) tu_printf(#_x " = %ld\r\n", (uint32_t) (_x) )
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#define TU_LOG1_HEX(_x) tu_printf(#_x " = %lX\r\n", (uint32_t) (_x) )
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#define TU_LOG1_INT(_x) tu_printf(#_x " = %ld\r\n", (unsigned long) (_x) )
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#define TU_LOG1_HEX(_x) tu_printf(#_x " = %lX\r\n", (unsigned long) (_x) )
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// Log Level 2: Warn
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#if CFG_TUSB_DEBUG >= 2
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@ -74,14 +74,14 @@ typedef struct {
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} xfer_ctl_t;
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xfer_ctl_t xfer_status[DWC2_EP_MAX][2];
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#define XFER_CTL_BASE(_ep, _dir) &xfer_status[_ep][_dir]
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#define XFER_CTL_BASE(_ep, _dir) (&xfer_status[_ep][_dir])
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// EP0 transfers are limited to 1 packet - larger sizes has to be split
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static uint16_t ep0_pending[2]; // Index determines direction as tusb_dir_t type
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// TX FIFO RAM allocation so far in words - RX FIFO size is readily available from dwc2->grxfsiz
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static uint16_t _allocated_fifo_words_tx; // TX FIFO size in words (IN EPs)
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static bool _out_ep_closed; // Flag to check if RX FIFO size needs an update (reduce its size)
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static bool _out_ep_closed; // Flag to check if RX FIFO size needs an update (reduce its size)
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// Calculate the RX FIFO size according to recommendations from reference manual
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static inline uint16_t calc_rx_ff_size(uint16_t ep_size)
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@ -120,14 +120,15 @@ static void bus_reset(uint8_t rhport)
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dwc2->dcfg &= ~DCFG_DAD_Msk;
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// 1. NAK for all OUT endpoints
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for(uint8_t n = 0; n < DWC2_EP_MAX; n++) {
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for ( uint8_t n = 0; n < DWC2_EP_MAX; n++ )
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{
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dwc2->epout[n].doepctl |= DOEPCTL_SNAK;
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}
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// 2. Un-mask interrupt bits
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dwc2->daintmsk = (1 << DAINTMSK_OEPM_Pos) | (1 << DAINTMSK_IEPM_Pos);
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dwc2->doepmsk = DOEPMSK_STUPM | DOEPMSK_XFRCM;
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dwc2->diepmsk = DIEPMSK_TOM | DIEPMSK_XFRCM;
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dwc2->diepmsk = DIEPMSK_TOM | DIEPMSK_XFRCM;
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// "USB Data FIFOs" section in reference manual
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// Peripheral FIFO architecture
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@ -188,7 +189,8 @@ static void bus_reset(uint8_t rhport)
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// Fixed control EP0 size to 64 bytes
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dwc2->epin[0].diepctl &= ~(0x03 << DIEPCTL_MPSIZ_Pos);
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xfer_status[0][TUSB_DIR_OUT].max_size = xfer_status[0][TUSB_DIR_IN].max_size = 64;
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xfer_status[0][TUSB_DIR_OUT].max_size = 64;
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xfer_status[0][TUSB_DIR_IN ].max_size = 64;
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dwc2->epout[0].doeptsiz |= (3 << DOEPTSIZ_STUPCNT_Pos);
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@ -210,7 +212,7 @@ static void set_speed(uint8_t rhport, tusb_speed_t speed)
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if ( rhport == 1 )
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{
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bitvalue = ((TUSB_SPEED_HIGH == speed) ? DCD_HIGH_SPEED : DCD_FULL_SPEED_USE_HS);
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bitvalue = (TUSB_SPEED_HIGH == speed ? DCD_HIGH_SPEED : DCD_FULL_SPEED_USE_HS);
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}
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else
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{
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@ -287,7 +289,7 @@ static void edpt_schedule_packets(uint8_t rhport, uint8_t const epnum, uint8_t c
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// A full IN transfer (multiple packets, possibly) triggers XFRC.
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epin[epnum].dieptsiz = (num_packets << DIEPTSIZ_PKTCNT_Pos) |
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((total_bytes << DIEPTSIZ_XFRSIZ_Pos) & DIEPTSIZ_XFRSIZ_Msk);
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((total_bytes << DIEPTSIZ_XFRSIZ_Pos) & DIEPTSIZ_XFRSIZ_Msk);
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epin[epnum].diepctl |= DIEPCTL_EPENA | DIEPCTL_CNAK;
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@ -311,10 +313,11 @@ static void edpt_schedule_packets(uint8_t rhport, uint8_t const epnum, uint8_t c
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// A full OUT transfer (multiple packets, possibly) triggers XFRC.
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epout[epnum].doeptsiz &= ~(DOEPTSIZ_PKTCNT_Msk | DOEPTSIZ_XFRSIZ);
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epout[epnum].doeptsiz |= (num_packets << DOEPTSIZ_PKTCNT_Pos) |
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((total_bytes << DOEPTSIZ_XFRSIZ_Pos) & DOEPTSIZ_XFRSIZ_Msk);
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((total_bytes << DOEPTSIZ_XFRSIZ_Pos) & DOEPTSIZ_XFRSIZ_Msk);
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epout[epnum].doepctl |= DOEPCTL_EPENA | DOEPCTL_CNAK;
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if ( (epout[epnum].doepctl & DOEPCTL_EPTYP) == DOEPCTL_EPTYP_0 && (XFER_CTL_BASE(epnum, dir))->interval == 1 )
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if ( (epout[epnum].doepctl & DOEPCTL_EPTYP) == DOEPCTL_EPTYP_0 &&
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XFER_CTL_BASE(epnum, dir)->interval == 1 )
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{
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// Take odd/even bit from frame counter.
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uint32_t const odd_frame_now = (dwc2->dsts & (1u << DSTS_FNSOF_Pos));
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@ -326,13 +329,82 @@ static void edpt_schedule_packets(uint8_t rhport, uint8_t const epnum, uint8_t c
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/*------------------------------------------------------------------*/
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/* Controller API
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*------------------------------------------------------------------*/
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void print_dwc2_info(dwc2_regs_t * dwc2)
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{
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dwc2_ghwcfg2_t const * hw_cfg2 = &dwc2->ghwcfg2_bm;
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dwc2_ghwcfg3_t const * hw_cfg3 = &dwc2->ghwcfg3_bm;
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dwc2_ghwcfg4_t const * hw_cfg4 = &dwc2->ghwcfg4_bm;
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TU_LOG_HEX(1, dwc2->guid);
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TU_LOG_HEX(1, dwc2->gsnpsid);
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TU_LOG_HEX(1, dwc2->ghwcfg1);
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// HW configure 2
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TU_LOG(1, "\r\n");
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TU_LOG_HEX(1, dwc2->ghwcfg2);
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TU_LOG_INT(1, hw_cfg2->op_mode );
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TU_LOG_INT(1, hw_cfg2->arch );
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TU_LOG_INT(1, hw_cfg2->point2point );
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TU_LOG_INT(1, hw_cfg2->hs_phy_type );
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TU_LOG_INT(1, hw_cfg2->fs_phy_type );
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TU_LOG_INT(1, hw_cfg2->num_dev_ep );
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TU_LOG_INT(1, hw_cfg2->num_host_ch );
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TU_LOG_INT(1, hw_cfg2->period_channel_support );
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TU_LOG_INT(1, hw_cfg2->enable_dynamic_fifo );
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TU_LOG_INT(1, hw_cfg2->mul_cpu_int );
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TU_LOG_INT(1, hw_cfg2->nperiod_tx_q_depth );
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TU_LOG_INT(1, hw_cfg2->host_period_tx_q_depth );
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TU_LOG_INT(1, hw_cfg2->dev_token_q_depth );
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TU_LOG_INT(1, hw_cfg2->otg_enable_ic_usb );
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// HW configure 3
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TU_LOG(1, "\r\n");
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TU_LOG_HEX(1, dwc2->ghwcfg3);
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TU_LOG_INT(1, hw_cfg3->xfer_size_width );
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TU_LOG_INT(1, hw_cfg3->packet_size_width );
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TU_LOG_INT(1, hw_cfg3->otg_enable );
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TU_LOG_INT(1, hw_cfg3->i2c_enable );
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TU_LOG_INT(1, hw_cfg3->vendor_ctrl_itf );
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TU_LOG_INT(1, hw_cfg3->optional_feature_removed );
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TU_LOG_INT(1, hw_cfg3->synch_reset );
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TU_LOG_INT(1, hw_cfg3->otg_adp_support );
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TU_LOG_INT(1, hw_cfg3->otg_enable_hsic );
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TU_LOG_INT(1, hw_cfg3->otg_bc_support );
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TU_LOG_INT(1, hw_cfg3->lpm_mode );
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TU_LOG_INT(1, hw_cfg3->total_fifo_size );
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// HW configure 4
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TU_LOG(1, "\r\n");
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TU_LOG_HEX(1, dwc2->ghwcfg4);
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TU_LOG_INT(1, hw_cfg4->num_dev_period_in_ep );
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TU_LOG_INT(1, hw_cfg4->power_optimized );
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TU_LOG_INT(1, hw_cfg4->ahb_freq_min );
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TU_LOG_INT(1, hw_cfg4->hibernation );
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TU_LOG_INT(1, hw_cfg4->service_interval_mode );
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TU_LOG_INT(1, hw_cfg4->ipg_isoc_en );
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TU_LOG_INT(1, hw_cfg4->acg_enable );
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TU_LOG_INT(1, hw_cfg4->utmi_phy_data_width );
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TU_LOG_INT(1, hw_cfg4->dev_ctrl_ep_num );
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TU_LOG_INT(1, hw_cfg4->iddg_filter_enabled );
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TU_LOG_INT(1, hw_cfg4->vbus_valid_filter_enabled );
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TU_LOG_INT(1, hw_cfg4->a_valid_filter_enabled );
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TU_LOG_INT(1, hw_cfg4->b_valid_filter_enabled );
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TU_LOG_INT(1, hw_cfg4->dedicated_fifos );
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TU_LOG_INT(1, hw_cfg4->num_dev_in_eps );
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TU_LOG_INT(1, hw_cfg4->dma_desc_enable );
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TU_LOG_INT(1, hw_cfg4->dma_dynamic );
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}
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void dcd_init (uint8_t rhport)
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{
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// Programming model begins in the last section of the chapter on the USB
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// peripheral in each Reference Manual.
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dwc2_regs_t * dwc2 = DWC2_REG(rhport);
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// check GSNPSID
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// check gsnpsid
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//TU_LOG_HEX(1, dwc2->gsnpsid);
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print_dwc2_info(dwc2);
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// No HNP/SRP (no OTG support), program timeout later.
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if ( rhport == 1 )
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@ -19,6 +19,27 @@
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#include "stdint.h"
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/* DWC OTG HW Release versions */
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#define DWC2_CORE_REV_2_71a 0x4f54271a
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#define DWC2_CORE_REV_2_72a 0x4f54272a
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#define DWC2_CORE_REV_2_80a 0x4f54280a
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#define DWC2_CORE_REV_2_90a 0x4f54290a
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#define DWC2_CORE_REV_2_91a 0x4f54291a
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#define DWC2_CORE_REV_2_92a 0x4f54292a
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#define DWC2_CORE_REV_2_94a 0x4f54294a
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#define DWC2_CORE_REV_3_00a 0x4f54300a
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#define DWC2_CORE_REV_3_10a 0x4f54310a
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#define DWC2_CORE_REV_4_00a 0x4f54400a
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#define DWC2_CORE_REV_4_20a 0x4f54420a
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#define DWC2_FS_IOT_REV_1_00a 0x5531100a
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#define DWC2_HS_IOT_REV_1_00a 0x5532100a
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#define DWC2_CORE_REV_MASK 0x0000ffff
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/* DWC OTG HW Core ID */
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#define DWC2_OTG_ID 0x4f540000
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#define DWC2_FS_IOT_ID 0x55310000
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#define DWC2_HS_IOT_ID 0x55320000
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#ifdef __cplusplus
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extern "C" {
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#endif
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@ -37,93 +58,165 @@ typedef struct
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} HS_PHYC_GlobalTypeDef;
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#endif
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typedef struct TU_ATTR_PACKED
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{
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uint32_t op_mode : 3; // 0: HNP and SRP | 1: SRP | 2: non-HNP, non-SRP
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uint32_t arch : 2; // 0: slave-only | 1: External DMA | 2: Internal DMA | 3: others
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uint32_t point2point : 1; // 0: support hub and split | 1: no hub, no split
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uint32_t hs_phy_type : 2; // 0: not supported | 1: UTMI+ | 2: ULPI | 3: UTMI+ and ULPI
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uint32_t fs_phy_type : 2; // 0: not supported | 1: dedicated | 2: UTMI+ | 3: ULPI
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uint32_t num_dev_ep : 4; // Number of device endpoints (not including EP0)
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uint32_t num_host_ch : 4; // Number of host channel
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uint32_t period_channel_support : 1; // Support Periodic OUT Host Channel
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uint32_t enable_dynamic_fifo : 1; // Dynamic FIFO Sizing Enabled
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uint32_t mul_cpu_int : 1; // Multi-Processor Interrupt Enabled
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uint32_t reserved21 : 1;
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uint32_t nperiod_tx_q_depth : 2; // Non-periodic request queue depth: 0 = 2. 1 = 4, 2 = 8
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uint32_t host_period_tx_q_depth : 2; // Host periodic request queue depth: 0 = 2. 1 = 4, 2 = 8
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uint32_t dev_token_q_depth : 5; // Device IN token sequence learning queue depth: 0-30
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uint32_t otg_enable_ic_usb : 1; // IC_USB mode specified for mode of operation
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} dwc2_ghwcfg2_t;
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TU_VERIFY_STATIC(sizeof(dwc2_ghwcfg2_t) == 4, "incorrect size");
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typedef struct TU_ATTR_PACKED
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{
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uint32_t xfer_size_width : 4; // Transfer size counter in bits = 11 + n (max 19 bits)
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uint32_t packet_size_width : 3; // Packet size counter in bits = 4 + n (max 10 bits)
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uint32_t otg_enable : 1; // 1 is OTG capable
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uint32_t i2c_enable : 1; // I2C interface is available
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uint32_t vendor_ctrl_itf : 1; // Vendor control interface is available
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uint32_t optional_feature_removed : 1; // remove User ID, GPIO, SOF toggle & counter
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uint32_t synch_reset : 1; // 0: async reset | 1: synch reset
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uint32_t otg_adp_support : 1; // ADP logic is present along with HSOTG controller
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uint32_t otg_enable_hsic : 1; // 1: HSIC-capable with shared UTMI PHY interface | 0: non-HSIC
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uint32_t otg_bc_support : 1; // support battery charger
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uint32_t lpm_mode : 1; // LPC mode
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uint32_t total_fifo_size : 16; // DFIFO depth value in terms of 32-bit words
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}dwc2_ghwcfg3_t;
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TU_VERIFY_STATIC(sizeof(dwc2_ghwcfg3_t) == 4, "incorrect size");
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typedef struct TU_ATTR_PACKED
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{
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uint32_t num_dev_period_in_ep : 4; // Number of Device Periodic IN Endpoints
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uint32_t power_optimized : 1; // Partial Power Down Enabled
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uint32_t ahb_freq_min : 1; // 1: minimum of AHB frequency is less than 60 MHz
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uint32_t hibernation : 1; // Hibernation feature is enabled
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uint32_t reserved7 : 3;
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uint32_t service_interval_mode : 1; // Service Interval supported
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uint32_t ipg_isoc_en : 1; // IPG ISOC supported
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uint32_t acg_enable : 1; // ACG enabled
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uint32_t reserved13 : 1;
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uint32_t utmi_phy_data_width : 2; // 0: 8 bits | 1: 16 bits | 2: 8/16 software selectable
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uint32_t dev_ctrl_ep_num : 4; // Number of Device control endpoints in addition to EP0
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uint32_t iddg_filter_enabled : 1;
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uint32_t vbus_valid_filter_enabled : 1;
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uint32_t a_valid_filter_enabled : 1;
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uint32_t b_valid_filter_enabled : 1;
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uint32_t dedicated_fifos : 1; // Dedicated tx fifo for device IN Endpoint is enabled
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uint32_t num_dev_in_eps : 4; // Number of Device IN Endpoints including EP0
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uint32_t dma_desc_enable : 1; // scatter/gather DMA configuration
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uint32_t dma_dynamic : 1; // Dynamic scatter/gather DMA
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}dwc2_ghwcfg4_t;
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TU_VERIFY_STATIC(sizeof(dwc2_ghwcfg4_t) == 4, "incorrect size");
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// Host Channel
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typedef struct
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{
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volatile uint32_t hcchar; // 500 + 20*ch Host Channel Characteristics Register
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volatile uint32_t hcsplt; // 504 + 20*ch Host Channel Split Control Register
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volatile uint32_t hcint; // 508 + 20*ch Host Channel Interrupt Register
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volatile uint32_t hcintmsk; // 50C + 20*ch Host Channel Interrupt Mask Register
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volatile uint32_t hctsiz; // 510 + 20*ch Host Channel Transfer Size Register
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volatile uint32_t hcdma; // 514 + 20*ch Host Channel DMA Address Register
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volatile uint32_t hcchar; // 500 + 20*ch Host Channel Characteristics
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volatile uint32_t hcsplt; // 504 + 20*ch Host Channel Split Control
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volatile uint32_t hcint; // 508 + 20*ch Host Channel Interrupt
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volatile uint32_t hcintmsk; // 50C + 20*ch Host Channel Interrupt Mask
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volatile uint32_t hctsiz; // 510 + 20*ch Host Channel Transfer Size
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volatile uint32_t hcdma; // 514 + 20*ch Host Channel DMA Address
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uint32_t reserved518; // 518 + 20*ch
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volatile uint32_t hcdmab; // 51C + 20*ch Host Channel DMA Address Register
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volatile uint32_t hcdmab; // 51C + 20*ch Host Channel DMA Address
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} dwc2_channel_t;
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// Endpoint IN
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typedef struct
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{
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volatile uint32_t diepctl; // 900 + 20*ep Device IN Endpoint Control
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uint32_t reserved04; // 904
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volatile uint32_t diepint; // 908 + 20*ep Device IN Endpoint Interrupt
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uint32_t reserved0c; // 90C
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volatile uint32_t dieptsiz; // 910 + 20*ep Device IN Endpoint Transfer Size
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volatile uint32_t diepdma; // 914 + 20*ep Device IN Endpoint DMA Address
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volatile uint32_t dtxfsts; // 918 + 20*ep Device IN Endpoint Tx FIFO Status
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uint32_t reserved1c; // 91C
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volatile uint32_t diepctl; // 900 + 20*ep Device IN Endpoint Control
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uint32_t reserved04; // 904
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volatile uint32_t diepint; // 908 + 20*ep Device IN Endpoint Interrupt
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uint32_t reserved0c; // 90C
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volatile uint32_t dieptsiz; // 910 + 20*ep Device IN Endpoint Transfer Size
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volatile uint32_t diepdma; // 914 + 20*ep Device IN Endpoint DMA Address
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volatile uint32_t dtxfsts; // 918 + 20*ep Device IN Endpoint Tx FIFO Status
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uint32_t reserved1c; // 91C
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} dwc2_epin_t;
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// Endpoint OUT
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typedef struct
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{
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volatile uint32_t doepctl; // B00 + 20*ep Device OUT Endpoint Control
|
||||
uint32_t reserved04; // B04
|
||||
volatile uint32_t doepint; // B08 + 20*ep Device OUT Endpoint Interrupt
|
||||
uint32_t reserved0c; // B0C
|
||||
volatile uint32_t doeptsiz; // B10 + 20*ep Device OUT Endpoint Transfer Size
|
||||
volatile uint32_t doepdma; // B14 + 20*ep Device OUT Endpoint DMA Address
|
||||
uint32_t reserved18[2]; // B18..B1C
|
||||
volatile uint32_t doepctl; // B00 + 20*ep Device OUT Endpoint Control
|
||||
uint32_t reserved04; // B04
|
||||
volatile uint32_t doepint; // B08 + 20*ep Device OUT Endpoint Interrupt
|
||||
uint32_t reserved0c; // B0C
|
||||
volatile uint32_t doeptsiz; // B10 + 20*ep Device OUT Endpoint Transfer Size
|
||||
volatile uint32_t doepdma; // B14 + 20*ep Device OUT Endpoint DMA Address
|
||||
uint32_t reserved18[2]; // B18..B1C
|
||||
} dwc2_epout_t;
|
||||
|
||||
typedef struct
|
||||
{
|
||||
//------------- Core Global -------------//
|
||||
volatile uint32_t gotgctl; // 000 OTG Control and Status Register
|
||||
volatile uint32_t gotgint; // 004 OTG Interrupt Register
|
||||
volatile uint32_t gahbcfg; // 008 AHB Configuration Register
|
||||
volatile uint32_t gusbcfg; // 00c USB Configuration Register
|
||||
volatile uint32_t grstctl; // 010 Reset Register
|
||||
volatile uint32_t gintsts; // 014 Interrupt Register
|
||||
volatile uint32_t gintmsk; // 018 Interrupt Mask Register
|
||||
volatile uint32_t grxstsr; // 01c Receive Status Debug Read Register
|
||||
volatile uint32_t grxstsp; // 020 Receive Status Read/Pop Register
|
||||
volatile uint32_t grxfsiz; // 024 Receive FIFO Size Register
|
||||
volatile uint32_t gotgctl; // 000 OTG Control and Status
|
||||
volatile uint32_t gotgint; // 004 OTG Interrupt
|
||||
volatile uint32_t gahbcfg; // 008 AHB Configuration
|
||||
volatile uint32_t gusbcfg; // 00c USB Configuration
|
||||
volatile uint32_t grstctl; // 010 Reset
|
||||
volatile uint32_t gintsts; // 014 Interrupt
|
||||
volatile uint32_t gintmsk; // 018 Interrupt Mask
|
||||
volatile uint32_t grxstsr; // 01c Receive Status Debug Read
|
||||
volatile uint32_t grxstsp; // 020 Receive Status Read/Pop
|
||||
volatile uint32_t grxfsiz; // 024 Receive FIFO Size
|
||||
union {
|
||||
volatile uint32_t dieptxf0; // 028 EP0 Tx FIFO Size Register
|
||||
volatile uint32_t gnptxfsiz; // 028 Non-periodic Transmit FIFO Size Register
|
||||
volatile uint32_t dieptxf0; // 028 EP0 Tx FIFO Size
|
||||
volatile uint32_t gnptxfsiz; // 028 Non-periodic Transmit FIFO Size
|
||||
};
|
||||
volatile uint32_t gnptxsts; // 02c Non-periodic Transmit FIFO/Queue Status Register
|
||||
volatile uint32_t gi2cctl; // 030 I2C Address Register
|
||||
volatile uint32_t gpvndctl; // 034 PHY Vendor Control Register
|
||||
volatile uint32_t gnptxsts; // 02c Non-periodic Transmit FIFO/Queue Status
|
||||
volatile uint32_t gi2cctl; // 030 I2C Address
|
||||
volatile uint32_t gpvndctl; // 034 PHY Vendor Control
|
||||
union {
|
||||
volatile uint32_t ggpio; // 038 General Purpose IO Register
|
||||
volatile uint32_t ggpio; // 038 General Purpose IO
|
||||
volatile uint32_t stm32_gccfg; // 038 STM32 General Core Configuration
|
||||
};
|
||||
volatile uint32_t guid; // 03C User ID Register
|
||||
volatile uint32_t gsnpsid; // 040 Synopsys ID Register
|
||||
volatile uint32_t ghwcfg1; // 044 User Hardware Configuration 1 Register
|
||||
volatile uint32_t ghwcfg2; // 048 User Hardware Configuration 2 Register
|
||||
volatile uint32_t ghwcfg3; // 04C User Hardware Configuration 3 Register
|
||||
volatile uint32_t ghwcfg4; // 050 User Hardware Configuration 4 Register
|
||||
volatile uint32_t glpmcfg; // 054 Core LPM Configuration Register
|
||||
volatile uint32_t gpwrdn; // 058 Power Down Register
|
||||
volatile uint32_t gdfifocfg; // 05C DFIFO Software Configuration Register
|
||||
volatile uint32_t gadpctl; // 060 ADP Timer, Control and Status Register
|
||||
|
||||
volatile uint32_t guid; // 03C User (Application programmable) ID
|
||||
volatile uint32_t gsnpsid; // 040 Synopsys ID + Release version
|
||||
volatile uint32_t ghwcfg1; // 044 User Hardware Configuration1: endpoint dir (2 bit per ep)
|
||||
union {
|
||||
volatile uint32_t ghwcfg2; // 048 User Hardware Configuration2
|
||||
dwc2_ghwcfg2_t ghwcfg2_bm;
|
||||
};
|
||||
union {
|
||||
volatile uint32_t ghwcfg3; // 04C User Hardware Configuration3
|
||||
dwc2_ghwcfg3_t ghwcfg3_bm;
|
||||
};
|
||||
union {
|
||||
volatile uint32_t ghwcfg4; // 050 User Hardware Configuration4
|
||||
dwc2_ghwcfg4_t ghwcfg4_bm;
|
||||
};
|
||||
volatile uint32_t glpmcfg; // 054 Core LPM Configuration
|
||||
volatile uint32_t gpwrdn; // 058 Power Down
|
||||
volatile uint32_t gdfifocfg; // 05C DFIFO Software Configuration
|
||||
volatile uint32_t gadpctl; // 060 ADP Timer, Control and Status
|
||||
uint32_t reserved64[39]; // 064..0FF
|
||||
volatile uint32_t hptxfsiz; // 100 Host Periodic Tx FIFO Size Register
|
||||
volatile uint32_t dieptxf[15]; // 104..13C Device Periodic Transmit FIFO Size Register
|
||||
volatile uint32_t hptxfsiz; // 100 Host Periodic Tx FIFO Size
|
||||
volatile uint32_t dieptxf[15]; // 104..13C Device Periodic Transmit FIFO Size
|
||||
uint32_t reserved140[176]; // 140..3FF
|
||||
|
||||
//------------- Host -------------//
|
||||
volatile uint32_t hcfg; // 400 Host Configuration Register
|
||||
volatile uint32_t hfir; // 404 Host Frame Interval Register
|
||||
volatile uint32_t hcfg; // 400 Host Configuration
|
||||
volatile uint32_t hfir; // 404 Host Frame Interval
|
||||
volatile uint32_t hfnum; // 408 Host Frame Number / Frame Remaining
|
||||
uint32_t reserved40c; // 40C
|
||||
volatile uint32_t hptxsts; // 410 Host Periodic TX FIFO / Queue Status
|
||||
volatile uint32_t haint; // 414 Host All Channels Interrupt Register
|
||||
volatile uint32_t haint; // 414 Host All Channels Interrupt
|
||||
volatile uint32_t haintmsk; // 418 Host All Channels Interrupt Mask
|
||||
volatile uint32_t hflbaddr; // 41C Host Frame List Base Address Register
|
||||
volatile uint32_t hflbaddr; // 41C Host Frame List Base Address
|
||||
uint32_t reserved420[8]; // 420..43F
|
||||
volatile uint32_t hprt; // 440 Host Port Control and Status
|
||||
uint32_t reserved444[47]; // 444..4FF
|
||||
|
|
@ -133,18 +226,18 @@ union {
|
|||
uint32_t reserved700[64]; // 700..7FF
|
||||
|
||||
//------------- Device -------------//
|
||||
volatile uint32_t dcfg; // 800 Device Configuration Register
|
||||
volatile uint32_t dctl; // 804 Device Control Register
|
||||
volatile uint32_t dsts; // 808 Device Status Register (RO)
|
||||
volatile uint32_t dcfg; // 800 Device Configuration
|
||||
volatile uint32_t dctl; // 804 Device Control
|
||||
volatile uint32_t dsts; // 808 Device Status (RO)
|
||||
uint32_t reserved80c; // 80C
|
||||
volatile uint32_t diepmsk; // 810 Device IN Endpoint Interrupt Mask
|
||||
volatile uint32_t doepmsk; // 814 Device OUT Endpoint Interrupt Mask
|
||||
volatile uint32_t daint; // 818 Device All Endpoints Interrupt
|
||||
volatile uint32_t daintmsk; // 81C Device All Endpoints Interrupt Mask
|
||||
volatile uint32_t dtknqr1; // 820 Device IN token sequence learning queue read register1
|
||||
volatile uint32_t dtknqr2; // 824 Device IN token sequence learning queue read register2
|
||||
volatile uint32_t dvbusdis; // 828 Device VBUS Discharge Time Register
|
||||
volatile uint32_t dvbuspulse; // 82C Device VBUS Pulsing Time Register
|
||||
volatile uint32_t dtknqr1; // 820 Device IN token sequence learning queue read1
|
||||
volatile uint32_t dtknqr2; // 824 Device IN token sequence learning queue read2
|
||||
volatile uint32_t dvbusdis; // 828 Device VBUS Discharge Time
|
||||
volatile uint32_t dvbuspulse; // 82C Device VBUS Pulsing Time
|
||||
volatile uint32_t dthrctl; // 830 Device threshold Control
|
||||
volatile uint32_t diepempmsk; // 834 Device IN Endpoint FIFO Empty Interrupt Mask
|
||||
volatile uint32_t deachint; // 838 Device Each Endpoint Interrupt
|
||||
|
|
@ -176,23 +269,6 @@ TU_VERIFY_STATIC(offsetof(dwc2_regs_t, epout ) == 0x0B00, "incorrect size");
|
|||
TU_VERIFY_STATIC(offsetof(dwc2_regs_t, pcgctrl) == 0x0E00, "incorrect size");
|
||||
TU_VERIFY_STATIC(offsetof(dwc2_regs_t, fifo ) == 0x1000, "incorrect size");
|
||||
|
||||
//--------------------------------------------------------------------+
|
||||
// Register Base Address
|
||||
//--------------------------------------------------------------------+
|
||||
|
||||
#define DWC2_GLOBAL_BASE 0x00000000UL
|
||||
#define DWC2_DEVICE_BASE 0x00000800UL
|
||||
#define DWC2_IN_ENDPOINT_BASE 0x00000900UL
|
||||
#define DWC2_OUT_ENDPOINT_BASE 0x00000B00UL
|
||||
#define DWC2_EP_REG_SIZE 0x00000020UL
|
||||
#define DWC2_HOST_BASE 0x00000400UL
|
||||
#define DWC2_HOST_PORT_BASE 0x00000440UL
|
||||
#define DWC2_HOST_CHANNEL_BASE 0x00000500UL
|
||||
#define DWC2_HOST_CHANNEL_SIZE 0x00000020UL
|
||||
#define DWC2_PCGCCTL_BASE 0x00000E00UL
|
||||
#define DWC2_FIFO_BASE 0x00001000UL
|
||||
#define DWC2_FIFO_SIZE 0x00001000UL
|
||||
|
||||
//--------------------------------------------------------------------+
|
||||
// Register Bit Definitions
|
||||
//--------------------------------------------------------------------+
|
||||
|
|
|
|||
Loading…
Reference in New Issue