fix EP0 data toggle issue
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2a479175ae
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ac3c645dc1
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@ -295,19 +295,6 @@ bool dcd_edpt_xfer (uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t
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xfer_desc_t* xfer = &_dcd_xfer[epnum];
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xfer_desc_t* xfer = &_dcd_xfer[epnum];
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xfer_begin(xfer, buffer, total_bytes);
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xfer_begin(xfer, buffer, total_bytes);
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// Control Status Stage if EP0 with len = 0 and direction is opposite of current Data Stage
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if ( (epnum == 0) && /*(total_bytes == 0) &&*/ (dir != ((UDP->UDP_CSR[epnum] & UDP_CSR_DIR_Msk) >> UDP_CSR_DIR_Pos)) )
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{
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TU_LOG2_INT(dir);
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if ( dir )
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{
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csr_set(0, UDP_CSR_DIR_Msk);
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}else
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{
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csr_clear(0, UDP_CSR_DIR_Msk);
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}
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}
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if (dir == TUSB_DIR_OUT)
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if (dir == TUSB_DIR_OUT)
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{
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{
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// Enable interrupt when starting OUT transfer
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// Enable interrupt when starting OUT transfer
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@ -388,10 +375,8 @@ void dcd_int_handler(uint8_t rhport)
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if ( intr_status & TU_BIT(0) )
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if ( intr_status & TU_BIT(0) )
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{
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{
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uint32_t csr0 = UDP->UDP_CSR[0];
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// setup packet
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// setup packet
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if (csr0 & UDP_CSR_RXSETUP)
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if ( UDP->UDP_CSR[0] & UDP_CSR_RXSETUP )
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{
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{
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// get setup from FIFO
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// get setup from FIFO
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uint8_t setup[8];
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uint8_t setup[8];
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@ -403,31 +388,19 @@ void dcd_int_handler(uint8_t rhport)
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// notify usbd
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// notify usbd
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dcd_event_setup_received(rhport, setup, true);
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dcd_event_setup_received(rhport, setup, true);
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// Reset FIFO
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// UDP->UDP_RST_EP |= (1 << 0);
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// UDP->UDP_RST_EP &= ~(1 << 0);
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csr0 &= ~(UDP_CSR_TXPKTRDY_Msk | UDP_CSR_TXCOMP_Msk | UDP_CSR_RX_DATA_BK0 | UDP_CSR_RX_DATA_BK1);
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// Set EP direction bit according to DATA stage
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// Set EP direction bit according to DATA stage
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// must be set before RXSETUP is clear per specs
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// MUST only be set before RXSETUP is clear per specs
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if ( tu_edpt_dir(setup[0]) )
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if ( tu_edpt_dir(setup[0]) )
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{
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{
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//csr_set(0, UDP_CSR_DIR_Msk);
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csr_set(0, UDP_CSR_DIR_Msk);
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csr0 |= UDP_CSR_DIR_Msk;
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}
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}
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else
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else
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{
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{
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//csr_clear(0, UDP_CSR_DIR_Msk);
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csr_clear(0, UDP_CSR_DIR_Msk);
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csr0 &= ~UDP_CSR_DIR_Msk;
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}
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}
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// Clear Setup bit & stall bit if needed
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// Clear Setup, stall and other on-going transfer bits
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//csr_clear(0, UDP_CSR_RXSETUP_Msk | UDP_CSR_FORCESTALL_Msk);
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csr_clear(0, UDP_CSR_RXSETUP_Msk | UDP_CSR_TXPKTRDY_Msk | UDP_CSR_TXCOMP_Msk | UDP_CSR_RX_DATA_BK0 | UDP_CSR_RX_DATA_BK1 | UDP_CSR_STALLSENT_Msk | UDP_CSR_FORCESTALL_Msk);
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csr0 &= ~(UDP_CSR_RXSETUP_Msk | UDP_CSR_STALLSENT_Msk | UDP_CSR_FORCESTALL_Msk);
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UDP->UDP_CSR[0] = csr0;
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for (uint32_t nop_count = 0; nop_count < 20; nop_count ++) __NOP();
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}
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}
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}
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}
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@ -450,8 +423,7 @@ void dcd_int_handler(uint8_t rhport)
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xact_ep_write(epnum, xfer->buffer, xact_len);
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xact_ep_write(epnum, xfer->buffer, xact_len);
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// TX ready for transfer
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// TX ready for transfer
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//csr_set(epnum, UDP_CSR_TXPKTRDY_Msk);
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csr_set(epnum, UDP_CSR_TXPKTRDY_Msk);
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UDP->UDP_CSR[epnum] |= UDP_CSR_TXPKTRDY_Msk;
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}else
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}else
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{
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{
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// xfer is complete
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// xfer is complete
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@ -462,8 +434,7 @@ void dcd_int_handler(uint8_t rhport)
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}
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}
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// Clear TX Complete bit
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// Clear TX Complete bit
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//csr_clear(epnum, UDP_CSR_TXCOMP_Msk);
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csr_clear(epnum, UDP_CSR_TXCOMP_Msk);
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UDP->UDP_CSR[epnum] &= ~UDP_CSR_TXCOMP_Msk;
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}
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}
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//------------- Endpoint OUT -------------//
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//------------- Endpoint OUT -------------//
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@ -488,15 +459,13 @@ void dcd_int_handler(uint8_t rhport)
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}
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}
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// Clear DATA Bank0/1 bit
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// Clear DATA Bank0/1 bit
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//csr_clear(epnum, banks_complete);
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csr_clear(epnum, banks_complete);
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UDP->UDP_CSR[epnum] &= ~banks_complete;
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}
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}
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// Stall sent to host
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// Stall sent to host
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if (UDP->UDP_CSR[epnum] & UDP_CSR_STALLSENT_Msk)
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if (UDP->UDP_CSR[epnum] & UDP_CSR_STALLSENT_Msk)
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{
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{
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//csr_clear(epnum, UDP_CSR_STALLSENT_Msk);
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csr_clear(epnum, UDP_CSR_STALLSENT_Msk);
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UDP->UDP_CSR[epnum] &= ~UDP_CSR_STALLSENT_Msk;
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}
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}
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}
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}
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}
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}
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