add hcd attr, add note for ehci framelist on NXP derivative
This commit is contained in:
hathach
parent
4ca176c291
commit
a490a3fe61
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@ -30,6 +30,7 @@
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#include "common/tusb_common.h"
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#include "osal/osal.h"
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#include "common/tusb_fifo.h"
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#include "hcd_attr.h"
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#ifdef __cplusplus
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extern "C" {
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@ -62,6 +63,7 @@ typedef struct
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struct {
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uint8_t hub_addr;
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uint8_t hub_port;
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uint8_t speed;
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} connection;
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// XFER_COMPLETE
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@ -140,7 +142,7 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t *
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bool hcd_edpt_clear_stall(uint8_t dev_addr, uint8_t ep_addr);
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//--------------------------------------------------------------------+
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// Event API (implemented by stack)
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// USBH implemented API
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//--------------------------------------------------------------------+
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// Called by HCD to notify stack
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@ -0,0 +1,104 @@
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/*
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* The MIT License (MIT)
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*
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* Copyright (c) 2021, Ha Thach (tinyusb.org)
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*
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* This file is part of the TinyUSB stack.
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*/
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#ifndef TUSB_HCD_ATTR_H_
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#define TUSB_HCD_ATTR_H_
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#include "tusb_option.h"
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// Attribute includes
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// - ENDPOINT_MAX: max (logical) number of endpoint
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// - PORT_HIGHSPEED: mask to indicate which port support highspeed mode, bit0 for port0 and so on.
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//------------- NXP -------------//
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#if TU_CHECK_MCU(LPC175X_6X) || TU_CHECK_MCU(LPC177X_8X) || TU_CHECK_MCU(LPC40XX)
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#elif TU_CHECK_MCU(LPC18XX) || TU_CHECK_MCU(LPC43XX)
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#define HCD_ATTR_EHCI_TRANSDIMENSION
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#elif TU_CHECK_MCU(LPC54XXX)
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// #define HCD_ATTR_EHCI_NXP_PTD
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#elif TU_CHECK_MCU(LPC55XX)
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// #define HCD_ATTR_EHCI_NXP_PTD
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#elif TU_CHECK_MCU(MIMXRT10XX)
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#define HCD_ATTR_EHCI_TRANSDIMENSION
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#elif TU_CHECK_MCU(MKL25ZXX)
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//------------- Microchip -------------//
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#elif TU_CHECK_MCU(SAMD21) || TU_CHECK_MCU(SAMD51) || TU_CHECK_MCU(SAME5X) || \
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TU_CHECK_MCU(SAMD11) || TU_CHECK_MCU(SAML21) || TU_CHECK_MCU(SAML22)
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#elif TU_CHECK_MCU(SAMG)
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#elif TU_CHECK_MCU(SAMX7X)
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//------------- ST -------------//
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#elif TU_CHECK_MCU(STM32F0) || TU_CHECK_MCU(STM32F1) || TU_CHECK_MCU(STM32F3) || \
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TU_CHECK_MCU(STM32L0) || TU_CHECK_MCU(STM32L1) || TU_CHECK_MCU(STM32L4)
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#elif TU_CHECK_MCU(STM32F2) || TU_CHECK_MCU(STM32F4) || TU_CHECK_MCU(STM32F3)
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#elif TU_CHECK_MCU(STM32F7)
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#elif TU_CHECK_MCU(STM32H7)
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//------------- Sony -------------//
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#elif TU_CHECK_MCU(CXD56)
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//------------- Nuvoton -------------//
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#elif TU_CHECK_MCU(NUC505)
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//------------- Espressif -------------//
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#elif TU_CHECK_MCU(ESP32S2) || TU_CHECK_MCU(ESP32S3)
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//------------- Raspberry Pi -------------//
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#elif TU_CHECK_MCU(RP2040)
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//------------- Silabs -------------//
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#elif TU_CHECK_MCU(EFM32GG) || TU_CHECK_MCU(EFM32GG11) || TU_CHECK_MCU(EFM32GG12)
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//------------- Renesas -------------//
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#elif TU_CHECK_MCU(RX63X) || TU_CHECK_MCU(RX65X) || TU_CHECK_MCU(RX72N)
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//#elif TU_CHECK_MCU(MM32F327X)
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// #define DCD_ATTR_ENDPOINT_MAX not known yet
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//------------- GigaDevice -------------//
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#elif TU_CHECK_MCU(GD32VF103)
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#else
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// #warning "DCD_ATTR_ENDPOINT_MAX is not defined for this MCU, default to 8"
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#endif
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// Default to fullspeed if not defined
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//#ifndef PORT_HIGHSPEED
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// #define DCD_ATTR_PORT_HIGHSPEED 0x00
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//#endif
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#endif
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@ -45,8 +45,8 @@ typedef struct
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hub_port_status_response_t port_status;
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} hub_interface_t;
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CFG_TUSB_MEM_SECTION static hub_interface_t hub_data[CFG_TUH_DEVICE_MAX];
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TU_ATTR_ALIGNED(4) CFG_TUSB_MEM_SECTION static uint8_t _hub_buffer[sizeof(descriptor_hub_desc_t)];
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CFG_TUSB_MEM_SECTION static hub_interface_t hub_data[CFG_TUH_HUB];
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CFG_TUSB_MEM_SECTION TU_ATTR_ALIGNED(4) static uint8_t _hub_buffer[sizeof(descriptor_hub_desc_t)];
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#if CFG_TUSB_DEBUG
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static char const* const _hub_feature_str[] =
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@ -144,7 +144,7 @@ bool hub_port_get_status(uint8_t hub_addr, uint8_t hub_port, void* resp, tuh_con
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//--------------------------------------------------------------------+
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void hub_init(void)
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{
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tu_memclr(hub_data, CFG_TUH_DEVICE_MAX*sizeof(hub_interface_t));
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tu_memclr(hub_data, sizeof(hub_data));
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}
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bool hub_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_interface_t const *itf_desc, uint16_t max_len)
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@ -128,7 +128,8 @@ enum { CONFIG_NUM = 1 }; // default to use configuration 1
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static bool _usbh_initialized = false;
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// including zero-address
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// all devices including hub and zero-address TODO exclude device0 to save space
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// hub address start from CFG_TUH_DEVICE_MAX
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CFG_TUSB_MEM_SECTION usbh_device_t _usbh_devices[CFG_TUH_DEVICE_MAX+1];
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// Event queue
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@ -24,11 +24,9 @@
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* This file is part of the TinyUSB stack.
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*/
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#include "common/tusb_common.h"
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#include "host/hcd_attr.h"
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#if TUSB_OPT_HOST_ENABLED && \
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(CFG_TUSB_MCU == OPT_MCU_LPC43XX || CFG_TUSB_MCU == OPT_MCU_LPC18XX || \
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CFG_TUSB_MCU == OPT_MCU_MIMXRT10XX )
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#if TUSB_OPT_HOST_ENABLED && defined(HCD_ATTR_EHCI_TRANSDIMENSION)
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//--------------------------------------------------------------------+
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// INCLUDE
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@ -47,21 +45,27 @@
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// Debug level of EHCI
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#define EHCI_DBG 2
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// Framelist size as small as possible
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// - Standard EHCI : 256 elements
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// - NXP Transdimension: 8 elements
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#define EHCI_CFG_FRAMELIST_SIZE_BITS 7
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#define EHCI_FRAMELIST_SIZE (1024 >> EHCI_CFG_FRAMELIST_SIZE_BITS)
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TU_VERIFY_STATIC(EHCI_CFG_FRAMELIST_SIZE_BITS <= 7, "incorrect value");
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// Framelist size as small as possible to save SRAM
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#ifdef HCD_ATTR_EHCI_TRANSDIMENSION
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// NXP Transdimension: 8 elements
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#define FRAMELIST_SIZE_BIT_VALUE 7u
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#define FRAMELIST_SIZE_USBCMD_VALUE (((FRAMELIST_SIZE_BIT_VALUE & 3) << EHCI_USBCMD_POS_FRAMELIST_SIZE) | \
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((FRAMELIST_SIZE_BIT_VALUE >> 2) << EHCI_USBCMD_POS_NXP_FRAMELIST_SIZE_MSB))
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#else
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// STD EHCI: 256 elements
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#define FRAMELIST_SIZE_BIT_VALUE 2u
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#define FRAMELIST_SIZE_USBCMD_VALUE ((FRAMELIST_SIZE_BIT_VALUE & 3) << EHCI_USBCMD_POS_FRAMELIST_SIZE)
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#endif
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#define FRAMELIST_SIZE (1024 >> FRAMELIST_SIZE_BIT_VALUE)
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typedef struct
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{
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ehci_link_t period_framelist[EHCI_FRAMELIST_SIZE];
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ehci_link_t period_framelist[FRAMELIST_SIZE];
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// for NXP ECHI, only implement 1 ms & 2 ms & 4 ms, 8 ms (framelist)
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// TODO only implement 1 ms & 2 ms & 4 ms, 8 ms (framelist)
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// [0] : 1ms, [1] : 2ms, [2] : 4ms, [3] : 8 ms
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// TODO better implementation without dummy head to save SRAM
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ehci_qhd_t period_head_arr[4];
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// Note control qhd of dev0 is used as head of async list
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@ -84,10 +88,10 @@ CFG_TUSB_MEM_SECTION TU_ATTR_ALIGNED(4096) static ehci_data_t ehci_data;
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//--------------------------------------------------------------------+
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// PROTOTYPE
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//--------------------------------------------------------------------+
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static inline ehci_link_t* get_period_head(uint8_t rhport, uint8_t interval_ms)
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static inline ehci_link_t* get_period_head(uint8_t rhport, uint32_t interval_ms)
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{
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(void) rhport;
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return (ehci_link_t*) &ehci_data.period_head_arr[ tu_log2( tu_min8(EHCI_FRAMELIST_SIZE, interval_ms) ) ];
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return (ehci_link_t*) &ehci_data.period_head_arr[ tu_log2( tu_min32(FRAMELIST_SIZE, interval_ms) ) ];
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}
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static inline ehci_qhd_t* qhd_control(uint8_t dev_addr)
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@ -260,37 +264,38 @@ bool ehci_init(uint8_t rhport, uint32_t capability_reg, uint32_t operatial_reg)
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//------------- Periodic List -------------//
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// Build the polling interval tree with 1 ms, 2 ms, 4 ms and 8 ms (framesize) only
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for(uint32_t i=0; i<4; i++)
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for ( uint32_t i = 0; i < TU_ARRAY_SIZE(ehci_data.period_head_arr); i++ )
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{
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ehci_data.period_head_arr[i].int_smask = 1; // queue head in period list must have smask non-zero
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ehci_data.period_head_arr[i].int_smask = 1; // queue head in period list must have smask non-zero
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ehci_data.period_head_arr[i].qtd_overlay.halted = 1; // dummy node, always inactive
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}
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ehci_link_t * const framelist = ehci_data.period_framelist;
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ehci_link_t * const period_1ms = get_period_head(rhport, 1);
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ehci_link_t * const period_1ms = get_period_head(rhport, 1u);
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// all links --> period_head_arr[0] (1ms)
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// 0, 2, 4, 6 etc --> period_head_arr[1] (2ms)
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// 1, 5 --> period_head_arr[2] (4ms)
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// 3 --> period_head_arr[3] (8ms)
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// TODO EHCI_FRAMELIST_SIZE with other size than 8
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for(uint32_t i=0; i<EHCI_FRAMELIST_SIZE; i++)
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for(uint32_t i=0; i<FRAMELIST_SIZE; i++)
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{
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framelist[i].address = (uint32_t) period_1ms;
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framelist[i].type = EHCI_QTYPE_QHD;
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}
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for(uint32_t i=0; i<EHCI_FRAMELIST_SIZE; i+=2)
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for(uint32_t i=0; i<FRAMELIST_SIZE; i+=2)
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{
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list_insert(framelist + i, get_period_head(rhport, 2), EHCI_QTYPE_QHD);
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list_insert(framelist + i, get_period_head(rhport, 2u), EHCI_QTYPE_QHD);
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}
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for(uint32_t i=1; i<EHCI_FRAMELIST_SIZE; i+=4)
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for(uint32_t i=1; i<FRAMELIST_SIZE; i+=4)
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{
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list_insert(framelist + i, get_period_head(rhport, 4), EHCI_QTYPE_QHD);
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list_insert(framelist + i, get_period_head(rhport, 4u), EHCI_QTYPE_QHD);
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}
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list_insert(framelist+3, get_period_head(rhport, 8), EHCI_QTYPE_QHD);
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list_insert(framelist+3, get_period_head(rhport, 8u), EHCI_QTYPE_QHD);
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period_1ms->terminate = 1;
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@ -300,10 +305,9 @@ bool ehci_init(uint8_t rhport, uint32_t capability_reg, uint32_t operatial_reg)
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regs->nxp_tt_control = 0;
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//------------- USB CMD Register -------------//
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regs->command |= TU_BIT(EHCI_USBCMD_POS_RUN_STOP) | TU_BIT(EHCI_USBCMD_POS_ASYNC_ENABLE)
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| TU_BIT(EHCI_USBCMD_POS_PERIOD_ENABLE) // TODO enable period list only there is int/iso endpoint
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| ((EHCI_CFG_FRAMELIST_SIZE_BITS & TU_BIN8(011)) << EHCI_USBCMD_POS_FRAMELIST_SZIE)
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| ((EHCI_CFG_FRAMELIST_SIZE_BITS >> 2) << EHCI_USBCMD_POS_NXP_FRAMELIST_SIZE_MSB);
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regs->command |= TU_BIT(EHCI_USBCMD_POS_RUN_STOP) | TU_BIT(EHCI_USBCMD_POS_ASYNC_ENABLE) |
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TU_BIT(EHCI_USBCMD_POS_PERIOD_ENABLE) | // TODO enable period list only there is int/iso endpoint
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FRAMELIST_SIZE_USBCMD_VALUE;
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//------------- ConfigFlag Register (skip) -------------//
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regs->portsc_bm.port_power = 1; // enable port power
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@ -530,10 +534,10 @@ static void async_list_xfer_complete_isr(ehci_qhd_t * const async_head)
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}while(p_qhd != async_head); // async list traversal, stop if loop around
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}
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static void period_list_xfer_complete_isr(uint8_t hostid, uint8_t interval_ms)
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static void period_list_xfer_complete_isr(uint8_t hostid, uint32_t interval_ms)
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{
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uint16_t max_loop = 0;
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uint32_t const period_1ms_addr = (uint32_t) get_period_head(hostid, 1);
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uint32_t const period_1ms_addr = (uint32_t) get_period_head(hostid, 1u);
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ehci_link_t next_item = * get_period_head(hostid, interval_ms);
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// TODO abstract max loop guard for period
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@ -616,8 +620,8 @@ static void xfer_error_isr(uint8_t hostid)
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}while(p_qhd != async_head); // async list traversal, stop if loop around
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//------------- TODO refractor period list -------------//
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uint32_t const period_1ms_addr = (uint32_t) get_period_head(hostid, 1);
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for (uint8_t interval_ms=1; interval_ms <= EHCI_FRAMELIST_SIZE; interval_ms *= 2)
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uint32_t const period_1ms_addr = (uint32_t) get_period_head(hostid, 1u);
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for (uint32_t interval_ms=1; interval_ms <= FRAMELIST_SIZE; interval_ms *= 2)
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{
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ehci_link_t next_item = * get_period_head(hostid, interval_ms);
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@ -660,7 +664,7 @@ void hcd_int_handler(uint8_t rhport)
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if (int_status & EHCI_INT_MASK_FRAMELIST_ROLLOVER)
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{
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ehci_data.uframe_number += (EHCI_FRAMELIST_SIZE << 3);
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ehci_data.uframe_number += (FRAMELIST_SIZE << 3);
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}
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if (int_status & EHCI_INT_MASK_PORT_CHANGE)
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@ -690,7 +694,7 @@ void hcd_int_handler(uint8_t rhport)
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if (int_status & EHCI_INT_MASK_NXP_PERIODIC)
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{
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for (uint8_t i=1; i <= EHCI_FRAMELIST_SIZE; i *= 2)
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for (uint32_t i=1; i <= FRAMELIST_SIZE; i *= 2)
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{
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period_list_xfer_complete_isr( rhport, i );
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}
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@ -289,7 +289,7 @@ enum ehci_interrupt_mask_{
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enum ehci_usbcmd_pos_ {
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EHCI_USBCMD_POS_RUN_STOP = 0,
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EHCI_USBCMD_POS_FRAMELIST_SZIE = 2,
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EHCI_USBCMD_POS_FRAMELIST_SIZE = 2,
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EHCI_USBCMD_POS_PERIOD_ENABLE = 4,
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EHCI_USBCMD_POS_ASYNC_ENABLE = 5,
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EHCI_USBCMD_POS_NXP_FRAMELIST_SIZE_MSB = 15,
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