ohci got device not response condition in control transfer
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@ -38,7 +38,7 @@
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#include <common/tusb_common.h>
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#include <common/tusb_common.h>
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#if MODE_HOST_SUPPORTED && (CFG_TUSB_MCU == OPT_MCU_LPC175X_6X)
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#if MODE_HOST_SUPPORTED && (CFG_TUSB_MCU == OPT_MCU_LPC175X_6X || CFG_TUSB_MCU == OPT_MCU_LPC40XX)
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//--------------------------------------------------------------------+
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//--------------------------------------------------------------------+
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// INCLUDE
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// INCLUDE
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//--------------------------------------------------------------------+
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//--------------------------------------------------------------------+
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@ -80,10 +80,6 @@ enum {
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OHCI_PERIODIC_START = 0x3E67
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OHCI_PERIODIC_START = 0x3E67
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};
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};
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#ifdef __CC_ARM
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#pragma diag_suppress 66 // Suppress Keil warnings #66-D: enumeration value is out of "int" range
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#endif
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enum {
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enum {
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OHCI_INT_SCHEDULING_OVERUN_MASK = BIT_(0),
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OHCI_INT_SCHEDULING_OVERUN_MASK = BIT_(0),
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OHCI_INT_WRITEBACK_DONEHEAD_MASK = BIT_(1),
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OHCI_INT_WRITEBACK_DONEHEAD_MASK = BIT_(1),
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@ -97,10 +93,6 @@ enum {
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OHCI_INT_MASTER_ENABLE_MASK = BIT_(31),
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OHCI_INT_MASTER_ENABLE_MASK = BIT_(31),
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};
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};
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#ifdef __CC_ARM
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#pragma diag_default 66 // return Keil 66 to normal severity
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#endif
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enum {
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enum {
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OHCI_RHPORT_CURRENT_CONNECT_STATUS_MASK = BIT_(0),
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OHCI_RHPORT_CURRENT_CONNECT_STATUS_MASK = BIT_(0),
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OHCI_RHPORT_PORT_ENABLE_STATUS_MASK = BIT_(1),
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OHCI_RHPORT_PORT_ENABLE_STATUS_MASK = BIT_(1),
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@ -238,7 +230,6 @@ void hcd_port_unplug(uint8_t hostid)
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//--------------------------------------------------------------------+
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//--------------------------------------------------------------------+
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// CONTROL PIPE API
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// CONTROL PIPE API
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//--------------------------------------------------------------------+
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//--------------------------------------------------------------------+
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static inline tusb_xfer_type_t ed_get_xfer_type(ohci_ed_t const * const p_ed) ATTR_PURE ATTR_ALWAYS_INLINE;
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static inline tusb_xfer_type_t ed_get_xfer_type(ohci_ed_t const * const p_ed)
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static inline tusb_xfer_type_t ed_get_xfer_type(ohci_ed_t const * const p_ed)
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{
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{
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return (p_ed->endpoint_number == 0 ) ? TUSB_XFER_CONTROL :
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return (p_ed->endpoint_number == 0 ) ? TUSB_XFER_CONTROL :
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@ -298,9 +289,59 @@ bool hcd_edpt_close(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr)
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return hcd_pipe_control_close(dev_addr);
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return hcd_pipe_control_close(dev_addr);
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}
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}
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bool hcd_setup_send(uint8_t rhport, uint8_t dev_addr, uint8_t const setup_packet[8])
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{
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(void) rhport;
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ohci_ed_t* p_ed = &ohci_data.control[dev_addr].ed;
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ohci_gtd_t *p_setup = &ohci_data.control[dev_addr].gtd[0];
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gtd_init(p_setup, (void*) setup_packet, 8);
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p_setup->index = dev_addr;
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p_setup->pid = OHCI_PID_SETUP;
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p_setup->data_toggle = BIN8(10); // DATA0
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p_setup->delay_interrupt = OHCI_INT_ON_COMPLETE_YES;
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//------------- Attach TDs list to Control Endpoint -------------//
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p_ed->td_head.address = (uint32_t) p_setup;
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OHCI_REG->command_status_bit.control_list_filled = 1;
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return true;
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}
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bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t * buffer, uint16_t buflen)
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{
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(void) rhport;
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uint8_t const epnum = edpt_number(ep_addr);
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uint8_t const dir = edpt_dir(ep_addr);
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// FIXME control only for now
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if ( epnum == 0 )
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{
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ohci_ed_t* const p_ed = &ohci_data.control[dev_addr].ed;
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ohci_gtd_t *p_data = &ohci_data.control[dev_addr].gtd[0];
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gtd_init(p_data, buffer, buflen);
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p_data->index = dev_addr;
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p_data->pid = dir ? OHCI_PID_IN : OHCI_PID_OUT;
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p_data->data_toggle = BIN8(11); // DATA1
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p_data->delay_interrupt = OHCI_INT_ON_COMPLETE_YES;
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p_ed->td_head.address = (uint32_t) p_data;
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OHCI_REG->command_status_bit.control_list_filled = 1;
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}
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return false;
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}
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tusb_error_t hcd_pipe_control_open(uint8_t dev_addr, uint8_t max_packet_size)
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tusb_error_t hcd_pipe_control_open(uint8_t dev_addr, uint8_t max_packet_size)
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{
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{
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ohci_ed_t* const p_ed = &ohci_data.control[dev_addr].ed;
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ohci_ed_t* p_ed = &ohci_data.control[dev_addr].ed;
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ed_init(p_ed, dev_addr, max_packet_size, 0, TUSB_XFER_CONTROL, 0); // TODO binterval of control is ignored
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ed_init(p_ed, dev_addr, max_packet_size, 0, TUSB_XFER_CONTROL, 0); // TODO binterval of control is ignored
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@ -193,14 +193,14 @@ bool usbh_init(void)
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bool usbh_control_xfer (uint8_t dev_addr, tusb_control_request_t* request, uint8_t* data)
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bool usbh_control_xfer (uint8_t dev_addr, tusb_control_request_t* request, uint8_t* data)
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{
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{
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usbh_device_t* dev = &_usbh_devices[dev_addr];
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usbh_device_t* dev = &_usbh_devices[dev_addr];
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//const uint8_t rhport = dev->core_id;
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const uint8_t rhport = dev->core_id;
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TU_ASSERT(osal_mutex_lock(dev->control.mutex_hdl, OSAL_TIMEOUT_NORMAL));
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TU_ASSERT(osal_mutex_lock(dev->control.mutex_hdl, OSAL_TIMEOUT_NORMAL));
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dev->control.request = *request;
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dev->control.request = *request;
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dev->control.pipe_status = 0;
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dev->control.pipe_status = 0;
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#if 1
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#if 0
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TU_ASSERT(hcd_pipe_control_xfer(dev_addr, &dev->control.request, data));
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TU_ASSERT(hcd_pipe_control_xfer(dev_addr, &dev->control.request, data));
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TU_ASSERT(osal_semaphore_wait(dev->control.sem_hdl, OSAL_TIMEOUT_NORMAL));
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TU_ASSERT(osal_semaphore_wait(dev->control.sem_hdl, OSAL_TIMEOUT_NORMAL));
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#else
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#else
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